sl@0: // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\euser\epoc\arm\uc_i64.cia
sl@0: // 
sl@0: //
sl@0: 
sl@0: #include <u32std.h>
sl@0: #include <e32math.h>
sl@0: 
sl@0: #if defined(__GCC32__)
sl@0: extern "C" void __division_by_zero();
sl@0: #define DIV_BY_ZERO " __division_by_zero "
sl@0: #elif defined(__ARMCC__)
sl@0: extern "C" void __rt_div0 (void);
sl@0: #define DIV_BY_ZERO " __cpp(__rt_div0) "
sl@0: #endif
sl@0: 
sl@0: 
sl@0: 
sl@0: 
sl@0: EXPORT_C __NAKED__ void Math::Mul64(Int64 /*aX*/, Int64 /*aY*/, Int64& /*aOutH*/, Uint64& /*aOutL*/)
sl@0: /**
sl@0: Multiply aX by aY to generate a 128 bit result.
sl@0: 
sl@0: The high order 64 bits of this calculation are stored in aOutH,
sl@0: and the low order 64 bits are stored in aOutL.
sl@0: 
sl@0: @param aX     The first 64-bit operand.
sl@0: @param aY     The second 64-bit operand.
sl@0: @param aOutH  The high order 64 bits of the result.
sl@0: @param aOutL  The low order  64 bits of the result.
sl@0: */
sl@0: 	{
sl@0: 	// Enter with r1:r0=aX, r3:r2=aY, [sp]=&aOutH, [sp+4]=&aOutL
sl@0: 	asm("stmfd sp!, {r4-r5,lr} ");
sl@0: 	asm("umull r4, r5, r0, r2 ");	// r5:r4 = x0 * y0
sl@0: 	asm("mov r12, #0 ");			// clear r12 initially
sl@0: 	asm("umlal r5, r12, r0, r3 ");	// r12:r5:r4 = x0 * y
sl@0: 	asm("mov r14, #0 ");			// clear r14 initially
sl@0: 	asm("smlal r12, r14, r1, r3 ");	// r14:r12:r5:r4 = x0 * y + (x1*y1)<<64
sl@0: 	asm("and r3, r0, r3, asr #32 ");	// if aY<0, r3=x0 else r3=0
sl@0: 	asm("and r0, r2, r1, asr #32 ");	// if aX<0, r0=y0 else r0=0
sl@0: 	asm("subs r12, r12, r3 ");
sl@0: 	asm("sbcs r14, r14, #0 ");
sl@0: 	asm("subs r12, r12, r0 ");
sl@0: 	asm("sbcs r14, r14, #0 ");
sl@0: 	asm("umull r0, r3, r1, r2 ");	// r3:r0 = x1 * y0
sl@0: 	asm("ldr r1, [sp, #12] ");		// r1=&aOutH
sl@0: 	asm("ldr r2, [sp, #16] ");		// r1=&aOutL
sl@0: 	asm("adds r5, r5, r0 ");		// shift left by 32 and add to give final result
sl@0: 	asm("adcs r12, r12, r3 ");
sl@0: 	asm("adcs r14, r14, #0 ");		// final result now in r14:r12:r5:r4
sl@0: 	asm("stmia r2, {r4,r5} ");		// store low 64
sl@0: 	asm("stmia r1, {r12,r14} ");	// store high 64
sl@0: 	__POPRET("r4-r5,");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: 
sl@0: 
sl@0: EXPORT_C __NAKED__ void Math::UMul64(Uint64 /*aX*/, Uint64 /*aY*/, Uint64& /*aOutH*/, Uint64& /*aOutL*/)
sl@0: /**
sl@0: Multiply aX by aY to generate a 128 bit result.
sl@0: 
sl@0: The high order 64 bits of this calculation are stored in aOutH,
sl@0: and the low order 64 bits are stored in aOutL.
sl@0: 
sl@0: @param aX     The first 64-bit operand.
sl@0: @param aY     The second 64-bit operand.
sl@0: @param aOutH  The high order 64 bits of the result.
sl@0: @param aOutL  The low order  64 bits of the result.
sl@0: */
sl@0: 	{
sl@0: 	// Enter with r1:r0=aX, r3:r2=aY, [sp]=&aOutH, [sp+4]=&aOutL
sl@0: 	asm("stmfd sp!, {r4-r5,lr} ");
sl@0: 	asm("umull r4, r5, r0, r2 ");	// r5:r4 = x0 * y0
sl@0: 	asm("mov r12, #0 ");			// clear r12 initially
sl@0: 	asm("umlal r5, r12, r0, r3 ");	// r12:r5:r4 = x0 * y
sl@0: 	asm("mov r14, #0 ");			// clear r14 initially
sl@0: 	asm("umlal r12, r14, r1, r3 ");	// r14:r12:r5:r4 = x0 * y + (x1*y1)<<64
sl@0: 									// r0, r3 no longer required
sl@0: 	asm("umull r0, r3, r1, r2 ");	// r3:r0 = x1 * y0
sl@0: 	asm("ldr r1, [sp, #12] ");		// r1=&aOutH
sl@0: 	asm("ldr r2, [sp, #16] ");		// r1=&aOutL
sl@0: 	asm("adds r5, r5, r0 ");		// shift left by 32 and add to give final result
sl@0: 	asm("adcs r12, r12, r3 ");
sl@0: 	asm("adcs r14, r14, #0 ");		// final result now in r14:r12:r5:r4
sl@0: 	asm("stmia r2, {r4,r5} ");		// store low 64
sl@0: 	asm("stmia r1, {r12,r14} ");	// store high 64
sl@0: 	__POPRET("r4-r5,");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: 
sl@0: 
sl@0: EXPORT_C __NAKED__ Int64 Math::DivMod64(Int64 /*aDividend*/, Int64 /*aDivisor*/, Int64& /*aRemainder*/)
sl@0: /**
sl@0: Divides aDividend by aDivisor.
sl@0: 
sl@0: The quotient is returned, and the remainder is stored in aRemainder.
sl@0: The remainder has same sign as the dividend.
sl@0: 
sl@0: @param aDividend The 64-bit dividend.
sl@0: @param aDivisor  The 64-bit divisor.
sl@0: @param aRemainder The 64-bit remainder.
sl@0: 
sl@0: @return The 64-bit quotient.
sl@0: */
sl@0: 	{
sl@0: 	// Enter with: r1:r0=dividend, r3:r2=divisor, [sp]=&aRemainder
sl@0: 	// Return quotient in r1:r0
sl@0: 	asm("stmfd sp!, {r4-r8,lr} ");
sl@0: 	__EH_FRAME_PUSH2(r4-r8,lr)
sl@0: 	asm("mov r8, r1, asr #1 ");		// r8 bit 31 =  r8 bit 30 = dividend sign
sl@0: 	asm("eor r8, r8, r3, lsr #1 ");	// r8 bit 31 = dividend sign, r8 bit 30 = quotient sign
sl@0: 	asm("cmp r1, #0 ");
sl@0: 	asm("bpl 1f ");
sl@0: 	asm("rsbs r0, r0, #0 ");		// r1:r0=ABS(dividend)
sl@0: 	asm("rscs r1, r1, #0 ");
sl@0: 	asm("1: ");
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("bpl 2f ");
sl@0: 	asm("rsbs r2, r2, #0 ");		// r3:r2=ABS(divisor)
sl@0: 	asm("rscs r3, r3, #0 ");
sl@0: 	asm("2: ");
sl@0: #ifndef __EABI__
sl@0: 	asm(".extern UDiv01 ");
sl@0: 	asm("bl UDiv01 ");				// do division, quotient->r5:r4, rem->r6:r3
sl@0: 	asm("mov r2, r3");				// move to make regs same as EABI function
sl@0: 	asm("mov r0, r4");
sl@0: 	asm("mov r1, r5");
sl@0: 	asm("mov r3, r6");
sl@0: #else //__EABI__
sl@0: 	asm(".extern __aeabi_uldivmod ");
sl@0: 	asm("bl __aeabi_uldivmod ");	// do division, quotient->r1:r0, rem->r3:r2
sl@0: #endif //__EABI__
sl@0: 	asm("add ip, r8, r8 ");			// ip bit 31 = quotient sign
sl@0: 	asm("ldr r6, [sp, #24] ");		// r6 = &aRemainder
sl@0: 	asm("eors r4, r0, ip, asr #32 ");	// quotient into r5:r4, inverted if quotient -ve
sl@0: 	asm("eors r5, r1, ip, asr #32 ");
sl@0: 	asm("adcs r0, r4, #0 ");		// if quotient -ve, add 1 whilst moving back to r1:r0
sl@0: 	asm("adcs r1, r5, #0 ");
sl@0: 	asm("cmp r8, #0 ");
sl@0: 	asm("bpl 3f ");
sl@0: 	asm("rsbs r2, r2, #0 ");		// if dividend -ve, negate remainder
sl@0: 	asm("rscs r3, r3, #0 ");
sl@0: 	asm("3: ");
sl@0: 	asm("stmia r6, {r2,r3} ");		// store remainder
sl@0: 	__POPRET("r4-r8,");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: 
sl@0: 
sl@0: EXPORT_C __NAKED__ Uint64 Math::UDivMod64(Uint64 /*aDividend*/, Uint64 /*aDivisor*/, Uint64& /*aRemainder*/)
sl@0: /**
sl@0: Divides aDividend by aDivisor.
sl@0: 
sl@0: The quotient is returned, and the remainder is stored in aRemainder.
sl@0: 
sl@0: @param aDividend The 64-bit dividend.
sl@0: @param aDivisor  The 64-bit divisor.
sl@0: @param aRemainder The 64-bit remainder.
sl@0: 
sl@0: @return The 64-bit quotient.
sl@0: */
sl@0: 	{
sl@0: 	// Enter with: r1:r0=dividend, r3:r2=divisor, [sp]=&aRemainder
sl@0: 	// Return quotient in r1:r0
sl@0: #ifdef __EABI__
sl@0: 	// need to keep sp 8-byte aligned
sl@0: 	asm("stmfd sp!, {r4-r8,lr} ");
sl@0: 	__EH_FRAME_PUSH2(r4-r8,lr)
sl@0: #else
sl@0: 	asm("stmfd sp!, {r4-r7,lr} ");
sl@0: #endif
sl@0: 
sl@0: #ifndef __EABI__
sl@0: 	asm(".extern UDiv01 ");
sl@0: 	asm("bl UDiv01 ");				// do division, quotient->r5:r4, rem->r6:r3
sl@0: 	asm("mov r2, r3");				// move to make regs same as EABI function
sl@0: 	asm("mov r0, r4");
sl@0: 	asm("mov r1, r5");
sl@0: 	asm("mov r3, r6");
sl@0: #else //__EABI__
sl@0: 	asm("bl __aeabi_uldivmod ");	// do division, quotient->r1:r0, rem->r3:r2
sl@0: #endif //__EABI__
sl@0: 
sl@0: #ifdef __EABI__
sl@0: 	asm("ldr r6, [sp, #24] ");		// r6 = &aRemainder
sl@0: #else 
sl@0: 	asm("ldr r6, [sp, #20] ");		// r6 = &aRemainder
sl@0: #endif 
sl@0: 
sl@0: 	asm("stmia r6, {r2,r3} ");		// store remainder
sl@0: 
sl@0: #ifdef __EABI__
sl@0: 	__POPRET("r4-r8,");
sl@0: #else
sl@0: 	__POPRET("r4-r7,");
sl@0: #endif
sl@0: 	}