sl@0: // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: //
sl@0: 
sl@0: 
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @internalComponent
sl@0:  @released
sl@0: */
sl@0: 
sl@0: #ifndef D_RMD_STEPPING_INL
sl@0: #define D_RMD_STEPPING_INL
sl@0: 
sl@0: //
sl@0: // IsBitSet
sl@0: //
sl@0: // Returns 1 if the bit 'aNum' is set within aBitset, 0 otherwise
sl@0: inline TUint32 DRMDStepping::IsBitSet(const TUint32 aBitset, const TUint8 aNum)
sl@0: 	{
sl@0: 	return (aBitset & (1 << aNum) );
sl@0: 	}
sl@0: 
sl@0: // 
sl@0: // BitCount
sl@0: //
sl@0: // Count number of bits in aVal
sl@0: inline TUint32 DRMDStepping::BitCount(const TUint32 aVal)
sl@0: 	{
sl@0: 	TUint32 num = 0;
sl@0: 
sl@0: 	for(TInt i = 0; i < 32; i++)
sl@0: 		{
sl@0: 		if ((1 << i) & aVal)
sl@0: 			{
sl@0: 			num++;
sl@0: 			}
sl@0: 		}
sl@0: 	return num;
sl@0: 	}
sl@0: 
sl@0: //
sl@0: // Thumb2 opcode decoding
sl@0: //
sl@0: // Special data instructions and branch and exchange.
sl@0: //
sl@0: // Returns Opcode as defined in ARM ARM DDI0406A, section A6.2.3
sl@0: inline TUint16 DRMDStepping::t2opcode16special(const TUint16 aInst)
sl@0: 	{
sl@0: 	TUint8 aVal = (aInst & 0x03C0) >> 5;
sl@0: 
sl@0: 	return aVal;
sl@0: 	}
sl@0: 
sl@0: 
sl@0: // Thumb2 opcode decoding instructions
sl@0: // 
sl@0: // Returns Opcode as defined in ARM ARM DDI0406A, section A6.2
sl@0: // 16-bit Thumb instruction encoding
sl@0: inline TUint16 DRMDStepping::t2opcode16(const TUint16 aInst)
sl@0: {
sl@0: 	TUint16 aVal = (aInst & 0xFC00) >> 9;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // ARM opcode decoding functions
sl@0: inline TUint32 DRMDStepping::arm_opcode(const TUint32 aInst)
sl@0: {
sl@0: // #define ARM_OPCODE(x)		(((TUint32)(x) & 0x0E000000) >> 25)
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x0E000000) >> 25;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping:: arm_rm(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_RM(x)				((TUint32)(x) & 0x0000000F)			// bit 0- 4
sl@0: 
sl@0: 	TUint32 aVal = (aInst) & 0x0000000F;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping:: arm_rs(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_RS(x)				(((TUint32)(x) & 0x00000F00) >> 8)	// bit 8-11
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00000F00) >> 8;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping:: arm_rd(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_RD(x)				(((TUint32)(x) & 0x0000F000) >> 12)	// bit 12-15
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x0000F000) >> 12;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping:: arm_rn(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_RN(x)				(((TUint32)(x) & 0x000F0000) >> 16)	// bit 16-19
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x000F0000) >> 16;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_load(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_LOAD(x)				(((TUint32)(x) & 0x00100000) >> 20)	// bit 20
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00100000) >> 20;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // Data processing instruction defines
sl@0: inline TUint32 DRMDStepping::arm_data_shift(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_DATA_SHIFT(x)		(((TUint32)(x) & 0x00000060) >> 5) 	// bit 5- 6
sl@0: 	
sl@0: 	TUint32 aVal = ((aInst) & 0x00000060) >> 5;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_data_c(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_DATA_C(x)			(((TUint32)(x) & 0x00000F80) >> 7) 	// bit 7-11
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00000F80) >> 7;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_data_imm(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_DATA_IMM(x)			((TUint32)(x) & 0x000000FF)			// bit 0-7
sl@0: 
sl@0: 	TUint32 aVal = (aInst) & 0x000000FF;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_data_rot(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_DATA_ROT(x)			(((TUint32)(x) & 0x00000F00) >> 8) 	// bit 8-11
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00000F00) >> 8;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // Single date transfer instruction defines
sl@0: inline TUint32 DRMDStepping::arm_single_imm(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_SINGLE_IMM(x)		((TUint32)(x) & 0x00000FFF)			// bit 0-11
sl@0: 
sl@0: 	TUint32 aVal = (aInst) & 0x00000FFF;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_single_byte(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_SINGLE_BYTE(x)		(((TUint32)(x) & 0x00400000) >> 22)	// bit 22
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00400000) >> 22;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_single_u(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_SINGLE_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00800000) >> 23;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_single_pre(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_SINGLE_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x01000000) >> 24;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // Block data transfer instruction defines
sl@0: inline TUint32 DRMDStepping::arm_block_reglist(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_BLOCK_REGLIST(x)	((TUint32)(x) & 0x0000FFFF)		// bit 0-15
sl@0: 
sl@0: 	TUint32 aVal = (aInst) & 0x0000FFFF;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_block_u(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_BLOCK_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x00800000) >> 23;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_block_pre(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_BLOCK_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24
sl@0: 
sl@0: 	TUint32 aVal = ((aInst) & 0x01000000) >> 24;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // Branch instruction defines
sl@0: inline TUint32 DRMDStepping::arm_b_addr(const TUint32 aInst)
sl@0: {
sl@0: //#define ARM_B_ADDR(x)			((x & 0x00800000) ? ((TUint32)(x) & 0x00FFFFFF | 0xFF000000) : (TUint32)(x) & 0x00FFFFFF)
sl@0: 
sl@0: 	TUint32 aVal = ((aInst & 0x00800000) ? ((TUint32)(aInst) & 0x00FFFFFF | 0xFF000000) : (TUint32)(aInst) & 0x00FFFFFF);
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_instr_b_dest(const TUint32 aInst, TUint32& aAddress)
sl@0: {
sl@0: //#define ARM_INSTR_B_DEST(x,a)	(ARM_B_ADDR(x) << 2) + ((TUint32)(a) + 8)
sl@0: 
sl@0: 	TUint32 aVal = (arm_b_addr(aInst) << 2) + ((TUint32)(aAddress) + 8);
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::thumb_b_addr(const TUint32 aInst)
sl@0: {
sl@0: //#define THUMB_B_ADDR(x) ((x & 0x0400) ? ((((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16) | 0xFFC00000) :\
sl@0:                                             ((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16)
sl@0: 
sl@0: 	TUint32 aVal = ((((TUint32)(aInst) & 0x07FF)<<11) | ((TUint32)(aInst) & 0x07FF0000)>>16);
sl@0: 
sl@0: 	return ((aInst & 0x0400) ? (aVal | 0xFFC00000) : aVal);
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::thumb_instr_b_dest(const TUint32 aInst, TUint32& aAddress)
sl@0: {
sl@0: //#define THUMB_INSTR_B_DEST(x,a)	(THUMB_B_ADDR(x) << 1) + ((TUint32)(a) + 4)
sl@0: 
sl@0: 	TUint32 aVal = (thumb_b_addr(aInst) << 1) + ((TUint32)(aAddress) + 4);
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint32 DRMDStepping::arm_carry_bit(void)
sl@0: {
sl@0: //#define ARM_CARRY_BIT			0x20000000	// bit 30
sl@0: 
sl@0: 	TUint32 aVal = 0x20000000;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: // Thumb instruction bitmasks
sl@0: inline TUint16 DRMDStepping::thumb_opcode(const TUint16 aInst)
sl@0: {
sl@0: //	#define THUMB_OPCODE(x)		(((TUint16)(x) & 0xF800) >> 11)
sl@0: 
sl@0: 	TUint16 aVal = ((aInst) & 0xF800) >> 11;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint16 DRMDStepping::thumb_inst_7_15(const TUint16 aInst)
sl@0: {
sl@0: //	#define THUMB_INST_7_15(x)	(((TUint16)(x) & 0xFF80) >> 7)
sl@0: 
sl@0: 	TUint16 aVal = ((aInst) & 0xFF80) >> 7;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: inline TUint16 DRMDStepping::thumb_inst_8_15(const TUint16 aInst)
sl@0: {
sl@0: //	#define THUMB_INST_8_15(x)	(((TUint16)(x) & 0xFF00) >> 8)
sl@0: 
sl@0: 	TUint16 aVal = ((aInst) & 0xFF00) >> 8;
sl@0: 
sl@0: 	return aVal;
sl@0: }
sl@0: 
sl@0: #endif	// D_RMD_STEPPPING_INL
sl@0: 
sl@0: // End of file - d-rmd-stepping.inl