sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // template/template_variant/variant.mmh sl@0: // TO DO: (mandatory) sl@0: // Add here a definition for your CPU (list in CONFIG.INC) sl@0: // sl@0: // sl@0: sl@0: macro __CPU_ARM1176__ sl@0: sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Add here a definition for your Memory Model sl@0: // sl@0: #define MM_MULTIPLE sl@0: sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Macro which generates the names for the binaries for this platform sl@0: // sl@0: #define VariantTarget(name,ext) _template_##name##.##ext sl@0: #define VariantMediaDefIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(template) sl@0: sl@0: //Include debug support. Some e32 tests require debug support sl@0: macro __DEBUGGER_SUPPORT__ sl@0: sl@0: // sl@0: // TO DO: sl@0: // sl@0: // If euser is built from the variant, uncomment the following line to build it sl@0: // as ARM rather than Thumb sl@0: // sl@0: // #define __BUILD_VARIANT_EUSER_AS_ARM__ sl@0: sl@0: // TO DO: (optional) sl@0: // sl@0: // To replace some of the generic utility functions with variant specific sl@0: // versions (eg to replace memcpy with a version optimised for the hardware), sl@0: // uncomment the two lines below and edit the files in the replacementUtils sl@0: // directory. sl@0: // sl@0: // #define REPLACE_GENERIC_UTILS sl@0: // #define VariantReplacementUtilsPath template/template_variant/replacement_utils sl@0: sl@0: // TO DO: (optional) sl@0: // sl@0: // Enable BTrace support in release versions of the kernel by adding sl@0: // the following BTRACE macro declarations sl@0: // sl@0: // macro BTRACE_KERNEL_ALL sl@0: sl@0: // TO DO: sl@0: // sl@0: // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor. sl@0: // sl@0: // macro __CPU_ARM1136_IS_R1__ sl@0: sl@0: // TO DO: sl@0: // sl@0: // Include the following line if default memory mapping should use shared memory. sl@0: // Should be on for multicore (SMP) devices. sl@0: // sl@0: // macro __CPU_USE_SHARED_MEMORY sl@0: // sl@0: sl@0: // TO DO: sl@0: // sl@0: // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973 sl@0: // "CLREX instruction might be ignored during data cache line fill" sl@0: // is fixed on this hardware. sl@0: // sl@0: // macro __CPU_ARM1136_ERRATUM_406973_FIXED sl@0: sl@0: // Uncomment next line if: sl@0: // 1) using the ARM1136 processor and ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID" sl@0: // is fixed on this hardware, or sl@0: // 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" sl@0: // is fixed on this hardware. sl@0: // sl@0: // macro __CPU_ARM1136_ERRATUM_408022_FIXED sl@0: sl@0: // Uncomment if: sl@0: // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache sl@0: // operation might fail to invalidate some lines if coincident with linefill" sl@0: // is fixed on this hardware, or sl@0: // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache sl@0: // operation might fail to invalidate some lines if coincident with linefill sl@0: // is fixed on this hardware. sl@0: // Workaround: sl@0: // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. sl@0: // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. sl@0: // If this macro is enabled, it should be accompanied by: sl@0: // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh sl@0: // sl@0: // macro __CPU_ARM1136_ERRATUM_411920_FIXED sl@0: sl@0: // Uncomment next line if using the ARM1176 processor and ARM1176 Erratum 720013 "Invalidate Instruction sl@0: // Cache operations can fail" is fixed on this hardware. sl@0: // sl@0: // macro __CPU_ARM1176_ERRATUM_720013_FIXED sl@0: sl@0: // TO DO: sl@0: // sl@0: // Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136 sl@0: // Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly" sl@0: // is fixed on this hardware. sl@0: // sl@0: // macro __CPU_ARM1136_ERRATUM_317041_FIXED sl@0: sl@0: // Uncomment the following line if Page Tables/Dirs have to be updated in main memory. sl@0: // Standard platforms shouldn't have this feature switched on. sl@0: // This must be accompanied by __ARM_L210_CACHE__ or __ARM_L220_CACHE__ macro. sl@0: // Omission:: The solution doesn't update temporary mappings sl@0: // of inter-process communication (IPC) - aka aliasing. sl@0: // sl@0: // macro __FLUSH_PT_INTO_RAM__ sl@0: sl@0: // Uncomment the following line if Symbian OS is running in TrustZone non-secure state and the sl@0: // secure state has prevented code executing in non-secure state from being able to mask FIQs by sl@0: // setting the SCR.FW bit in the secure configuration register. sl@0: // sl@0: // macro __FIQ_RESERVED_FOR_SECURE_STATE__ sl@0: sl@0: // Various PlatSec configuration options cannot be disabled even by clearing the appropriate sl@0: // bits in the kernel configuration flags - they are enforced at compile time. Uncomment the sl@0: // following to allow the clearing of bits in the kernel config flags to disable the relevant sl@0: // options at run time. sl@0: // sl@0: //macro __PLATSEC_UNLOCKED__ sl@0: sl@0: // If this macro is enabled then EMapAttrBufferedNC memory will be remapped as EMapAttrFullyBlocking sl@0: //macro FAULTY_NONSHARED_DEVICE_MEMORY sl@0: sl@0: // Uncomment the following line if L210/20 cache is running in forced-WT mode. sl@0: // (Forced_WT bit set in Debug Control Register of L210/20 cache controller.) sl@0: // macro __ARM_L2_CACHE_WT_MODE sl@0: sl@0: // For the status of errata of L210 & L220 cache, see the header of source file: sl@0: // e32\kernel\arm\cachel2.cpp sl@0: sl@0: #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__) sl@0: library VariantTarget(katemplate,lib) sl@0: #endif sl@0: sl@0: // Uncomment the following if IIC Controller is required sl@0: // library iic.lib // commented out as this iic.lib is now included from iic_channel.mmh sl@0: