sl@0: // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // template\template_variant\specific\variant.cia
sl@0: // 
sl@0: //
sl@0: 
sl@0: #include <e32cia.h>
sl@0: #include "variant.h"
sl@0: #include "mconf.h"
sl@0: 
sl@0: /******************************************************************************
sl@0:  * Interrupt handling/dispatch
sl@0:  ******************************************************************************/
sl@0: __NAKED__ void XIntDispatch(TAny*)
sl@0: 	{
sl@0: 	// Service second-level Variant Interrupts
sl@0: 	// Enter with r0->{Variant int controller base; Handlers;}
sl@0: 	asm("stmfd sp!, {r4,lr} ");
sl@0: 	asm("ldmia r0, {r3,r4} ");										// r3=Variant interrupt controller base, r4->handlers
sl@0: 	asm("0: ");
sl@0: 	asm("ldr r0, [r3, #%a0]" : : "i" ((TInt)KHoIntContEnable));		// r0=bitmask with enabled interrupts
sl@0: 	asm("ldr r1, [r3, #%a0]" : : "i" ((TInt)KHoIntContPending));	// r1=bitmask with pending interrupts
sl@0: 	asm("mov r2, #31 ");											// int id
sl@0: 	asm("and r0, r0, r1 ");
sl@0: 	asm("bics r0, r0, #0xf8000000 ");								// mask unused bits (only 26 2nd-level ints defined)
sl@0: 	asm("ldmeqfd sp!, {r4,pc} ");									// if no 2nd level interrupts pending, exit
sl@0: 	asm("cmp r0, #0x00010000 ");
sl@0: 	asm("movcc r0, r0, lsl #16 ");
sl@0: 	asm("subcc r2, r2, #16 ");
sl@0: 	asm("cmp r0, #0x01000000 ");
sl@0: 	asm("movcc r0, r0, lsl #8 ");
sl@0: 	asm("subcc r2, r2, #8 ");
sl@0: 	asm("cmp r0, #0x10000000 ");
sl@0: 	asm("movcc r0, r0, lsl #4 ");
sl@0: 	asm("subcc r2, r2, #4 ");
sl@0: 	asm("cmp r0, #0x40000000 ");
sl@0: 	asm("movcc r0, r0, lsl #2 ");
sl@0: 	asm("subcc r2, r2, #2 ");
sl@0: 	asm("cmp r0, #0x80000000 ");
sl@0: 	asm("subcc r2, r2, #1 ");										// r2=bit no. of MS 1
sl@0: 	asm("add r0, r4, r2, lsl #3 ");									// r0->handler for this interrupt
sl@0: 	asm("adr lr, 0b ");												// look again after calling handler
sl@0: 	asm("ldmia r0, {r0,pc} ");										// jump to handler
sl@0: 	}