sl@0: ; template\config.inc sl@0: ; sl@0: ; Copyright (c) 1998-2001 Symbian Ltd. All rights reserved. sl@0: ; sl@0: ; Template bootstrap configuration file sl@0: sl@0: ; Include to enable tracing sl@0: ; GBLL CFG_DebugBootRom sl@0: sl@0: ; Include one of these to select the CPU sl@0: ; GBLL CFG_CPU_GENERIC_ARM4 sl@0: ; GBLL CFG_CPU_ARM710T sl@0: ; GBLL CFG_CPU_ARM720T sl@0: ; GBLL CFG_CPU_SA1 sl@0: ; GBLL CFG_CPU_ARM920T sl@0: ; GBLL CFG_CPU_ARM925T sl@0: ; GBLL CFG_CPU_ARM926J sl@0: ; GBLL CFG_CPU_XSCALE sl@0: ; GBLL CFG_CPU_ARM1136 sl@0: GBLL CFG_CPU_ARM1176 sl@0: ; GBLL CFG_CORTEX_A8 sl@0: sl@0: ; Include the following line if this is a bootloader bootstrap sl@0: ; GBLL CFG_BootLoader sl@0: ; TO DO: sl@0: ; The following line needs to be removed for target hardware sl@0: GBLL CFG_Template sl@0: sl@0: ; If you want to supply a custom set of initial vectors (including reset vector) include the following line sl@0: ; GBLL CFG_CustomVectors sl@0: ; sl@0: ; and provide a custom_vectors.inc file sl@0: sl@0: ; Variant Number, just an example: sl@0: INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001 sl@0: sl@0: ; On ARM architecture 6 processors, include the following line to override the threshold sl@0: ; on total physical RAM size at which the multiple memory model switches into large address space mode sl@0: ; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process sl@0: ; Defaults to 32Mb. sl@0: ; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, sl@0: sl@0: ; For the direct memory model only, include the following line if you wish the exception vectors at the sl@0: ; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option sl@0: ; is mandatory if not. sl@0: ; GBLL CFG_UseBootstrapVectors sl@0: ; sl@0: ; If the above option is in use (including if no MMU is present) the following symbol should be defined sl@0: ; to specify the offset from the bootstrap to the kernel image. sl@0: INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000 sl@0: sl@0: ; Include the following line if you wish to include the ROM autodetection code based on data bus sl@0: ; capacitance and image repeats. sl@0: ; GBLL CFG_AutoDetectROM sl@0: sl@0: ; Include the following line to minimise the initial kernel heap size sl@0: ; On the direct memory model the size of the kernel data area (super page to end of kernel heap) sl@0: ; is rounded up to the next 1Mb if this is not included, 4K if it is. sl@0: ; On the moving and multiple models, the size of the initial kernel heap area is rounded up to sl@0: ; the next 64K if this is not included, 4K if it is. sl@0: ; GBLL CFG_MinimiseKernelHeap sl@0: sl@0: ; Include the following line if default memory mapping should use shared memory. sl@0: ; Should be defined on multicore (SMP) devices. sl@0: ; GBLL CFG_USE_SHARED_MEMORY sl@0: sl@0: ; On the moving or multiple memory models, include either or both of the following lines to sl@0: ; specify the size of the initial kernel heap sl@0: ; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, sl@0: ; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, sl@0: ; sl@0: ; The initial kernel heap size is MAX( + * N / 16, value specified in ROMBUILD ) sl@0: ; where N is the total physical RAM size in pages. sl@0: ; defaults to 24K and defaults to 9*16 (ie 9 bytes per page). sl@0: sl@0: ; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494 sl@0: ; "Rare conditions can cause corruption of the Instruction Cache" sl@0: ; is fixed on this hardware. sl@0: ; sl@0: ; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions sl@0: ; are used for the exception vectors. If the erratum is not fixed, RORO must be used. sl@0: ; sl@0: ; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED sl@0: sl@0: ; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296 sl@0: ; "Possible Cache Data Corruption with Hit-Under-Miss" sl@0: ; is fixed on this hardware. sl@0: ; sl@0: ; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED sl@0: sl@0: ; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234 sl@0: ; "Write back data cache entry evicted by write through entry causes data corruption" sl@0: ; is fixed on this hardware. sl@0: ; Workaround sl@0: ; The erratum may be avoided by marking all cacheable memory as one of write through or write back. sl@0: ; This requires the memory attributes described in the translation tables to be modified by software sl@0: ; appropriately, or the use of the remapping capability to remap write through regions to non cacheable. sl@0: ; sl@0: ; If this macro is enabled, it should be accompanied by: sl@0: ; "macro __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh sl@0: ; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED sl@0: sl@0: sl@0: ; Uncomment if: sl@0: ; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache sl@0: ; operation might fail to invalidate some lines if coincident with linefill" sl@0: ; is fixed on this hardware, or sl@0: ; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache sl@0: ; operation might fail to invalidate some lines if coincident with linefill sl@0: ; is fixed on this hardware. sl@0: ; Workaround: sl@0: ; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. sl@0: ; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. sl@0: ; If this macro is enabled, it should be accompanied by: sl@0: ; "macro __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh sl@0: ; sl@0: ; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED sl@0: sl@0: sl@0: ; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by sl@0: ; Index might corrupt cache when used with background prefetch range" is fixed on this hardware. sl@0: ; Workaround: sl@0: ; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. sl@0: ; sl@0: ; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED sl@0: sl@0: sl@0: sl@0: ; These are deduced from the supplied configuration sl@0: ; CFG_ARMV6 sl@0: ; CFG_MMUPresent sl@0: ; CFG_CachePresent sl@0: ; CFG_WriteBufferPresent sl@0: ; CFG_SplitCache sl@0: ; CFG_SplitTLB sl@0: ; CFG_AltDCachePresent sl@0: ; CFG_WriteBackCache sl@0: ; CFG_CacheWriteAllocate sl@0: ; CFG_CachePhysicalTag sl@0: ; CFG_CacheFlushByDataRead sl@0: ; CFG_CacheFlushByWaySetIndex sl@0: ; CFG_CacheFlushByLineAlloc sl@0: ; CFG_CachePolicyInPTE sl@0: ; CFG_TEX sl@0: ; CFG_SingleEntryDCacheFlush sl@0: ; CFG_SingleEntryICacheFlush sl@0: ; CFG_SingleEntryITLBFlush sl@0: ; CFG_SingleEntryTLBFlush sl@0: ; CFG_CacheTypeReg sl@0: ; CFG_BTBPresent sl@0: ; CFG_CARPresent sl@0: ; CFG_PrefetchBuffer sl@0: ; CFG_FCSE_Present sl@0: ; CFG_ASID_Present sl@0: ; CFG_IncludeRAMAllocator sl@0: sl@0: END