sl@0: EXPORTS
sl@0: 	WriteTransmitRegister__3I2siQ23I2s14TI2sFramePhasei @ 1 NONAME R3UNUSED ; I2s::WriteTransmitRegister(int, I2s::TI2sFramePhase, int)
sl@0: 	DisableDMA__3I2sii @ 2 NONAME R3UNUSED ; I2s::DisableDMA(int, int)
sl@0: 	DisableFIFOInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 3 NONAME R3UNUSED ; I2s::DisableFIFOInterrupts(int, I2s::TI2sFramePhase, int)
sl@0: 	DisableFIFO__3I2siQ23I2s14TI2sFramePhasei @ 4 NONAME R3UNUSED ; I2s::DisableFIFO(int, I2s::TI2sFramePhase, int)
sl@0: 	DisableRegisterInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 5 NONAME R3UNUSED ; I2s::DisableRegisterInterrupts(int, I2s::TI2sFramePhase, int)
sl@0: 	EnableDMA__3I2sii @ 6 NONAME R3UNUSED ; I2s::EnableDMA(int, int)
sl@0: 	EnableFIFOInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 7 NONAME R3UNUSED ; I2s::EnableFIFOInterrupts(int, I2s::TI2sFramePhase, int)
sl@0: 	EnableFIFO__3I2siQ23I2s14TI2sFramePhasei @ 8 NONAME R3UNUSED ; I2s::EnableFIFO(int, I2s::TI2sFramePhase, int)
sl@0: 	EnableRegisterInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 9 NONAME R3UNUSED ; I2s::EnableRegisterInterrupts(int, I2s::TI2sFramePhase, int)
sl@0: 	GetDelayCycles__3I2siQ23I2s14TI2sFramePhaseRi @ 10 NONAME R3UNUSED ; I2s::GetDelayCycles(int, I2s::TI2sFramePhase, int &)
sl@0: 	GetFrameFormat__3I2siRiT2 @ 11 NONAME R3UNUSED ; I2s::GetFrameFormat(int, int &, int &)
sl@0: 	GetInterfaceConfiguration__3I2siR5TDes8 @ 12 NONAME R3UNUSED ; I2s::GetInterfaceConfiguration(int, TDes8 &)
sl@0: 	GetSampleLength__3I2siQ23I2s14TI2sFramePhaseRi @ 13 NONAME R3UNUSED ; I2s::GetSampleLength(int, I2s::TI2sFramePhase, int &)
sl@0: 	GetSamplingRate__3I2siRi @ 14 NONAME R3UNUSED ; I2s::GetSamplingRate(int, int &)
sl@0: 	IsDMAEnabled__3I2siRi @ 15 NONAME R3UNUSED ; I2s::IsDMAEnabled(int, int &)
sl@0: 	IsFIFOEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 16 NONAME R3UNUSED ; I2s::IsFIFOEnabled(int, I2s::TI2sFramePhase, int &)
sl@0: 	IsFIFOInterruptEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 17 NONAME R3UNUSED ; I2s::IsFIFOInterruptEnabled(int, I2s::TI2sFramePhase, int &)
sl@0: 	IsRegisterInterruptEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 18 NONAME R3UNUSED ; I2s::IsRegisterInterruptEnabled(int, I2s::TI2sFramePhase, int &)
sl@0: 	IsStarted__3I2siQ23I2s13TI2sDirectionRi @ 19 NONAME R3UNUSED ; I2s::IsStarted(int, I2s::TI2sDirection, int &)
sl@0: 	ReadFIFOLevel__3I2siQ23I2s14TI2sFramePhaseQ23I2s13TI2sDirectionRi @ 20 NONAME ; I2s::ReadFIFOLevel(int, I2s::TI2sFramePhase, I2s::TI2sDirection, int &)
sl@0: 	ReadFIFOModeStatus__3I2siQ23I2s14TI2sFramePhaseRi @ 21 NONAME R3UNUSED ; I2s::ReadFIFOModeStatus(int, I2s::TI2sFramePhase, int &)
sl@0: 	ReadReceiveRegister__3I2siQ23I2s14TI2sFramePhaseRi @ 22 NONAME R3UNUSED ; I2s::ReadReceiveRegister(int, I2s::TI2sFramePhase, int &)
sl@0: 	ReadRegisterModeStatus__3I2siQ23I2s14TI2sFramePhaseRi @ 23 NONAME R3UNUSED ; I2s::ReadRegisterModeStatus(int, I2s::TI2sFramePhase, int &)
sl@0: 	ReadTransmitRegister__3I2siQ23I2s14TI2sFramePhaseRi @ 24 NONAME R3UNUSED ; I2s::ReadTransmitRegister(int, I2s::TI2sFramePhase, int &)
sl@0: 	SetDelayCycles__3I2siQ23I2s14TI2sFramePhasei @ 25 NONAME R3UNUSED ; I2s::SetDelayCycles(int, I2s::TI2sFramePhase, int)
sl@0: 	SetFIFOThreshold__3I2siQ23I2s14TI2sFramePhaseQ23I2s13TI2sDirectioni @ 26 NONAME ; I2s::SetFIFOThreshold(int, I2s::TI2sFramePhase, I2s::TI2sDirection, int)
sl@0: 	SetFrameLengthAndFormat__3I2siQ23I2s15TI2sFrameLengthi @ 27 NONAME R3UNUSED ; I2s::SetFrameLengthAndFormat(int, I2s::TI2sFrameLength, int)
sl@0: 	SetSampleLength__3I2siQ23I2s14TI2sFramePhaseQ23I2s16TI2sSampleLength @ 28 NONAME R3UNUSED ; I2s::SetSampleLength(int, I2s::TI2sFramePhase, I2s::TI2sSampleLength)
sl@0: 	SetSamplingRate__3I2siQ23I2s16TI2sSamplingRate @ 29 NONAME R3UNUSED ; I2s::SetSamplingRate(int, I2s::TI2sSamplingRate)
sl@0: 	Start__3I2sii @ 30 NONAME R3UNUSED ; I2s::Start(int, int)
sl@0: 	Stop__3I2sii @ 31 NONAME R3UNUSED ; I2s::Stop(int, int)
sl@0: 	ConfigureInterface__3I2siP5TDes8 @ 32 NONAME R3UNUSED ; I2s::ConfigureInterface(int, TDes8 *)
sl@0: