sl@0: // Copyright (c) 1996-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // f32\sfat32\inc\sl_cache.h sl@0: // sl@0: // sl@0: sl@0: /** sl@0: @file sl@0: @internalTechnology sl@0: */ sl@0: sl@0: //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! sl@0: //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! sl@0: //!! sl@0: //!! WARNING!! DO NOT edit this file !! '\sfat' component is obsolete and is not being used. '\sfat32'replaces it sl@0: //!! sl@0: //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! sl@0: //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! sl@0: sl@0: sl@0: #ifndef SL_CACHE_H sl@0: #define SL_CACHE_H sl@0: sl@0: sl@0: //--------------------------------------------------------------------------------------------------------------------------------- sl@0: //-- dedicated FAT directory cache related stuff sl@0: sl@0: //-- if defined, a dedicated cache will be used for FAT directories sl@0: #define ENABLE_DEDICATED_DIR_CACHE sl@0: sl@0: //--------------------------------------------------------------------------------------------------------------------------------- sl@0: sl@0: sl@0: /** sl@0: An abstract interface to the media Write-Through cache sl@0: */ sl@0: class MWTCacheInterface sl@0: { sl@0: public: sl@0: sl@0: /** Enums for control functions. See Control() */ sl@0: enum TControl sl@0: { sl@0: EDisableCache = 0, ///< disable/enable cache, can be used for debug purposes sl@0: EDumpCache = 1, ///< print full cache content, can be used for debug purposes sl@0: ECacheInfo = 2, ///< print cache info, can be used for debug purposes sl@0: }; sl@0: sl@0: virtual ~MWTCacheInterface() {} sl@0: sl@0: /** the same meaning and parameters as in CRawDisk::ReadL */ sl@0: virtual void ReadL(TInt64 aPos, TInt aLength, TDes8& aDes)=0; sl@0: sl@0: /** the same meaning and parameters as in CRawDisk::WriteL */ sl@0: virtual void WriteL(TInt64 aPos,const TDesC8& aDes)=0; sl@0: sl@0: /** Invalidates whole directory cache*/ sl@0: virtual void InvalidateCache(void)=0; sl@0: sl@0: /** invalidate a single cache page if the aPos is cached*/ sl@0: virtual void InvalidateCachePage(TUint64 aPos)=0; sl@0: sl@0: /** sl@0: Finds out if the media position "aPosToSearch" is in the cache and returns cache page information in this case. sl@0: sl@0: @param aPosToSearch linear media position to lookup in the cache sl@0: @param aCachedPosStart if "aPosToSearch" is cached, here will be media position of this page start sl@0: sl@0: @return 0 if aPosToSearch isn't cached, otherwise cache page size in bytes (see also aCachedPosStart). sl@0: */ sl@0: virtual TUint32 PosCached(const TInt64& aPosToSearch, TInt64& aCachedPosStart) = 0; sl@0: sl@0: /** sl@0: @return size of the cache in bytes. Can be 0. sl@0: */ sl@0: virtual TUint32 CacheSizeInBytes() const = 0; sl@0: sl@0: /** sl@0: Make the page indexed by aPos the MRU page in the cache. sl@0: Assumes cache evicts pages according to LRU algorithm. sl@0: */ sl@0: virtual void MakePageMRU(TInt64 aPos) = 0; sl@0: sl@0: /** sl@0: @return log2 number of the size of the cache in bytes. sl@0: */ sl@0: virtual TUint32 PageSizeInBytesLog2() const = 0; sl@0: sl@0: /** sl@0: Control method. sl@0: sl@0: @param aFunction control function sl@0: @param aParam1 just arbitrary parameter sl@0: @param aParam2 just arbitrary parameter sl@0: @return Standard error code. sl@0: */ sl@0: virtual TInt Control(TUint32 aFunction, TUint32 aParam1, TAny* aParam2)=0; sl@0: sl@0: /** sl@0: Set cache base position at aBasePos sl@0: @param aBasePos base position of the cache pages. Affects pages alignment. sl@0: */ sl@0: virtual void SetCacheBasePos(TInt64 aBasePos)=0; sl@0: sl@0: }; sl@0: sl@0: //--------------------------------------------------------------------------------------------------------------------------------- sl@0: sl@0: /** sl@0: This class represents the media Write-Through cache page sl@0: */ sl@0: class CWTCachePage sl@0: { sl@0: public: sl@0: sl@0: static CWTCachePage* NewL(TUint32 aPageSizeLog2); sl@0: void ConstructL(TUint32 aPageSizeLog2); sl@0: sl@0: ~CWTCachePage(); sl@0: sl@0: inline TBool PosCached(TInt64 aPos) const; sl@0: inline TUint32 PosInCachePage(TInt64 aPos) const; sl@0: inline TUint8* PtrInCachePage(TInt64 aPos) const; sl@0: inline TUint32 PageSize() const; sl@0: sl@0: protected: sl@0: sl@0: CWTCachePage(); sl@0: CWTCachePage(const CWTCachePage&); sl@0: CWTCachePage& operator=(const CWTCachePage&); sl@0: sl@0: public: sl@0: sl@0: TInt32 iValid; ///< 0 if the page doesn't contain valid data sl@0: TInt64 iStartPos; ///< cache page base media position sl@0: RBuf8 iData; ///< page Data sl@0: }; sl@0: sl@0: //--------------------------------------------------------------------------------------------------------------------------------- sl@0: sl@0: /** sl@0: Media Write-through cache. sl@0: */ sl@0: class CMediaWTCache : public CBase, public MWTCacheInterface sl@0: { sl@0: public: sl@0: ~CMediaWTCache(); sl@0: sl@0: static CMediaWTCache* NewL(TFatDriveInterface& aDrive, TUint32 aNumPages, TUint32 aPageSizeLog2); sl@0: sl@0: void ConstructL(TUint32 aNumPages, TUint32 aPageSizeLog2); sl@0: sl@0: //-- overloads from the base class sl@0: void ReadL (TInt64 aPos,TInt aLength,TDes8& aDes); sl@0: void WriteL(TInt64 aPos,const TDesC8& aDes); sl@0: void InvalidateCache(void); sl@0: void InvalidateCachePage(TUint64 aPos); sl@0: sl@0: sl@0: TUint32 PosCached(const TInt64& aPosToSearch, TInt64& aCachedPosStart); sl@0: TUint32 CacheSizeInBytes() const; sl@0: void MakePageMRU(TInt64 aPos); sl@0: TUint32 PageSizeInBytesLog2() const; sl@0: TInt Control(TUint32 aFunction, TUint32 aParam1, TAny* aParam2); sl@0: inline void SetCacheBasePos(TInt64 aBasePos); sl@0: //-- sl@0: sl@0: protected: sl@0: CMediaWTCache(); sl@0: CMediaWTCache(TFatDriveInterface& aDrive); sl@0: sl@0: inline TInt64 CalcPageStartPos(TInt64 aPos) const; sl@0: inline TUint32 PageSize() const; sl@0: sl@0: void MakePageLRU(TInt aPageNo); sl@0: sl@0: TInt FindPageByPos(TInt64 aPos) const; sl@0: TUint32 GrabPage() const; sl@0: TUint32 GrabReadPageL(TInt64 aPos); sl@0: TUint32 FindOrGrabReadPageL(TInt64 aPos); sl@0: sl@0: protected: sl@0: TFatDriveInterface& iDrive; ///< reference to the driver for media access sl@0: TUint32 iPageSizeLog2; ///< Log2 (cache page size) sl@0: mutable TBool iAllPagesValid;///< ETrue if all cache pages have valid data sl@0: TInt64 iCacheBasePos; ///< Cache pages base position, used to align them at cluster size sl@0: RPointerArray iPages; ///< array of pointers to the cache pages. Used for organising LRU list sl@0: TUint32 iCacheDisabled :1; ///< if not 0 the cache is disabled totally and all reads and writes go via TFatDriveInterface directly sl@0: }; sl@0: sl@0: sl@0: sl@0: sl@0: #include"sl_cache.inl" sl@0: sl@0: #endif //SL_CACHE_H sl@0: sl@0: sl@0: sl@0: