sl@0: /*
sl@0: * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: * All rights reserved.
sl@0: * This component and the accompanying materials are made available
sl@0: * under the terms of the License "Eclipse Public License v1.0"
sl@0: * which accompanies this distribution, and is available
sl@0: * at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: *
sl@0: * Initial Contributors:
sl@0: * Nokia Corporation - initial contribution.
sl@0: *
sl@0: * Contributors:
sl@0: *
sl@0: * Description:
sl@0: *
sl@0: */
sl@0: //
sl@0: // TO DO: (mandatory)
sl@0: //
sl@0: // Add here a definition for your CPU (list in CONFIG.INC)
sl@0: //
sl@0: macro __CPU_ARM11MP__
sl@0: //
sl@0: // TO DO: (mandatory)
sl@0: //
sl@0: // Add here a definition for your Memory Model
sl@0: //
sl@0: #define MM_MULTIPLE
sl@0: //
sl@0: // TO DO: (mandatory)
sl@0: //
sl@0: // Macro which generates the names for the binaries for this platform
sl@0: //
sl@0: #ifndef VariantTarget
sl@0: #define VariantTarget(name,ext) _ne1_tb_##name##.##ext
sl@0: #endif
sl@0: 
sl@0: #ifndef VariantMediaDefIncludePath
sl@0: #define VariantMediaDefIncludePath /epoc32/include/ne1_tb
sl@0: #endif
sl@0: 
sl@0: // Used in MMP files for include paths e.g. to hcrconfig.h header
sl@0: #ifndef VariantIncludePath
sl@0: #define VariantIncludePath /epoc32/include/ne1_tb
sl@0: #endif
sl@0: 
sl@0: 
sl@0: //Include debug support
sl@0: macro __DEBUGGER_SUPPORT__
sl@0: 
sl@0: //
sl@0: // TO DO: 
sl@0: //
sl@0: // If euser is built from the variant, uncomment the following line to build it
sl@0: // as ARM rather than Thumb
sl@0: // 
sl@0: //#define __BUILD_VARIANT_EUSER_AS_ARM__
sl@0: //
sl@0: // TO DO: (optional)
sl@0: //
sl@0: // To replace some of the generic utility functions with variant specific
sl@0: // versions (eg to replace memcpy with a version optimised for the hardware),
sl@0: // uncomment the two lines below and edit the files in the replacementUtils
sl@0: // directory.
sl@0: //
sl@0: //#define REPLACE_GENERIC_UTILS
sl@0: //#define VariantReplacementUtilsPath ne1_tb/replacement_utils
sl@0: //
sl@0: // TO DO: (optional)
sl@0: //
sl@0: // Enable BTrace support in release versions of the kernel by adding
sl@0: // the following BTRACE macro declarations
sl@0: //
sl@0: macro BTRACE_KERNEL_ALL
sl@0: //
sl@0: // TO DO:
sl@0: //
sl@0: // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
sl@0: // 
sl@0: //#define __CPU_ARM1136_IS_R1__
sl@0: //
sl@0: 
sl@0: // Include the following line if default memory mapping should use shared memory.
sl@0: // Should be on for multicore (SMP) devices.
sl@0: 
sl@0: macro	__CPU_USE_SHARED_MEMORY
sl@0: 
sl@0: // Include the following line if CPU cannot tolerate the presence of nonshared
sl@0: // cached memory. This seems to be the case for the ARM11 MPCore - corruption
sl@0: // of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY
sl@0: // is used.
sl@0: 
sl@0: macro	__CPU_FORCE_SHARED_MEMORY_IF_CACHED
sl@0: 
sl@0: 
sl@0: 
sl@0: // TO DO:
sl@0: //
sl@0: // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
sl@0: // "CLREX instruction might be ignored during data cache line fill"
sl@0: // is fixed on this hardware.
sl@0: // 
sl@0: //#define __CPU_ARM1136_ERRATUM_406973_FIXED
sl@0: 
sl@0: // Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022 
sl@0: // "Cancelled write to CONTEXTID register might update ASID" 
sl@0: // is fixed on this hardware.
sl@0: //
sl@0: //#define __CPU_ARM1136_ERRATUM_408022_FIXED
sl@0: 
sl@0: 
sl@0: // Uncomment if:
sl@0: //	1)	using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
sl@0: //	  	operation might fail to invalidate some lines if coincident with linefill"
sl@0: //  	  	is fixed on this hardware, or
sl@0: //	2)	using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
sl@0: // 	  	operation might fail to invalidate some lines if coincident with linefill
sl@0: //	  	is fixed on this hardware.
sl@0: // Workaround:
sl@0: //	1)	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
sl@0: //	2)	Replaces Invalidate ICache operation with the sequence defined in the errata document.
sl@0: // If this macro is enabled, it should be accompanied by:
sl@0: // 	"GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
sl@0: //
sl@0: // #define __CPU_ARM1136_ERRATUM_411920_FIXED
sl@0: 
sl@0: macro FAULTY_NONSHARED_DEVICE_MEMORY
sl@0: 
sl@0: #define AsspNKernIncludePath		/epoc32/include/assp/naviengine/nkern
sl@0: 
sl@0: // FIQ can not be disabled on naviengine, tell kernel to ignore it...
sl@0: macro __FIQ_IS_UNCONTROLLED__
sl@0: 
sl@0: macro MONITOR_THREAD_CPU_TIME
sl@0: 
sl@0: #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
sl@0: library	VariantTarget(kanaviengine,lib)
sl@0: #endif
sl@0: