sl@0: ; Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: ; All rights reserved.
sl@0: ; This component and the accompanying materials are made available
sl@0: ; under the terms of the License "Eclipse Public License v1.0"
sl@0: ; which accompanies this distribution, and is available
sl@0: ; at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: ;
sl@0: ; Initial Contributors:
sl@0: ; Nokia Corporation - initial contribution.
sl@0: ;
sl@0: ; Contributors:
sl@0: ;
sl@0: ; Description:
sl@0: ;
sl@0: 
sl@0:         AREA |d-rmdebug-bkpt$$Code|, CODE, READONLY, ALIGN=6
sl@0: 
sl@0: 	CODE32
sl@0: 
sl@0: 	; ARM tests
sl@0: 	
sl@0: ; 
sl@0: ; Non-PC modifying
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_Non_PC_Modifying
sl@0: 	EXPORT RMDebug_StepTest_Non_PC_Modifying_OK
sl@0:  
sl@0: RMDebug_StepTest_Non_PC_Modifying
sl@0: 	mov		r0,r0		; nop
sl@0: RMDebug_StepTest_Non_PC_Modifying_OK
sl@0: 	bx		lr			; should return to normal execution of the test thread
sl@0: 
sl@0: ;
sl@0: ; Branch
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_Branch
sl@0: 	EXPORT RMDebug_StepTest_Branch_1
sl@0: 
sl@0: RMDebug_StepTest_Branch
sl@0: 	b		RMDebug_StepTest_Branch_1		
sl@0: 	mov		r0, #2		; if the pc ends up here, we know its gone wrong
sl@0: RMDebug_StepTest_Branch_1
sl@0: 	bx		lr			; return
sl@0: 
sl@0: ;
sl@0: ; Branch and Link
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_Branch_And_Link
sl@0: 	EXPORT RMDebug_StepTest_Branch_And_Link_1
sl@0: 	EXPORT RMDebug_StepTest_Branch_And_Link_2
sl@0: 
sl@0: RMDebug_StepTest_Branch_And_Link		
sl@0: 	mov		r0, lr		; preserve lr for the moment
sl@0: RMDebug_StepTest_Branch_And_Link_1
sl@0: 	bl		RMDebug_StepTest_Branch_And_Link_2
sl@0: 	mov		r1, #1		; insert a gap in the instruction stream so we know we branched.
sl@0: RMDebug_StepTest_Branch_And_Link_2
sl@0: 	mov		lr, r0		; restore lr			
sl@0: 	bx		lr			; should return to normal execution of the test thread
sl@0: 
sl@0: ;
sl@0: ; MOV PC
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_MOV_PC
sl@0: 	EXPORT RMDebug_StepTest_MOV_PC_1
sl@0: 	EXPORT RMDebug_StepTest_MOV_PC_2
sl@0: 
sl@0: RMDebug_StepTest_MOV_PC
sl@0: 	mov		r0, #4
sl@0: RMDebug_StepTest_MOV_PC_1
sl@0: 	add		pc, pc, r0	; should be a jump (bear in mind reading pc = current inst + 8bytes for arm)
sl@0: 	mov		r0, #1		; Simple instructions which allow us to test where the PC really is
sl@0: 	mov		r0, #2		; just by reading r0.
sl@0: RMDebug_StepTest_MOV_PC_2
sl@0: 	mov		r0, #3		; 
sl@0: 	mov		r0, #4		; 
sl@0: 	bx		lr			; should return to normal execution of the test thread
sl@0: 
sl@0: ; 
sl@0: ; LDR PC
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_LDR_PC
sl@0: 	EXPORT RMDebug_StepTest_LDR_PC_1
sl@0: 
sl@0: RMDebug_StepTest_LDR_PC
sl@0: 	ldr		pc, =RMDebug_StepTest_LDR_PC_1
sl@0: 	mov		r0, #1		;  separate the branch target so we can prove it works
sl@0: RMDebug_StepTest_LDR_PC_1
sl@0: 	bx		lr			; should return to normal execution of the test thread
sl@0: 	
sl@0: ;
sl@0: ; ARM -> Thumb -> ARM interworking test
sl@0: ;
sl@0: ; Note: We always start and finish this test
sl@0: ; in ARM mode.
sl@0: 	EXPORT RMDebug_StepTest_Interwork
sl@0: 	EXPORT RMDebug_StepTest_Interwork_1
sl@0: 	EXPORT RMDebug_StepTest_Interwork_2
sl@0: 	EXPORT RMDebug_StepTest_Interwork_3	
sl@0: RMDebug_StepTest_Interwork
sl@0: 	mov		r0, lr	; preserve lr
sl@0: RMDebug_StepTest_Interwork_1
sl@0: 	blx		RMDebug_StepTest_Interwork_2
sl@0: 
sl@0: 	CODE16
sl@0: RMDebug_StepTest_Interwork_2
sl@0: 	blx		RMDebug_StepTest_Interwork_3
sl@0: 
sl@0: 	CODE32
sl@0: 
sl@0: RMDebug_StepTest_Interwork_3
sl@0: 	bx		r0
sl@0: 
sl@0: ;
sl@0: ; Stepping performance tests
sl@0: ;
sl@0: ; This counts down from 100000 to 0
sl@0: ; This means that for all practical purposes
sl@0: ; we can single-step as much as we like
sl@0: ; in less than one second and have some likelyhood
sl@0: ; that we will not step too far from our loop
sl@0: 
sl@0: 	EXPORT RMDebug_StepTest_Count
sl@0: 	EXPORT RMDebug_StepTest_Count_1
sl@0: 	EXPORT RMDebug_StepTest_Count_2
sl@0: 
sl@0: RMDebug_StepTest_Count
sl@0: 	ldr		r2, =100000
sl@0: RMDebug_StepTest_Count_1
sl@0: 	subs	r2, r2, #1
sl@0: RMDebug_StepTest_Count_2
sl@0: 	bne		RMDebug_StepTest_Count_1
sl@0: 	bx		lr
sl@0: 
sl@0: ; Thumb tests
sl@0: 
sl@0: ; Thumb non-pc modifying
sl@0: ;
sl@0: ;
sl@0: RMDebug_StepTest_Thumb_Non_PC_Modifying
sl@0: 	mov		r0, lr	; preserve lr
sl@0: 	blx		RMDebug_StepTest_Thumb_Non_PC_Modifying_1
sl@0: 	bx		r0
sl@0: 
sl@0: ;
sl@0: ; Thumb Branch
sl@0: ;
sl@0: RMDebug_StepTest_Thumb_Branch
sl@0: 	mov		r0, lr	; preserve lr
sl@0: 	blx		RMDebug_StepTest_Thumb_Branch_1
sl@0: 	bx		r0		
sl@0: 
sl@0: ;
sl@0: ; Thumb Branch and link
sl@0: ;
sl@0: RMDebug_StepTest_Thumb_Branch_And_Link
sl@0: 	mov		r0, lr	; preserve lr
sl@0: 	blx		RMDebug_StepTest_Thumb_Branch_And_Link_1
sl@0: 	bx		r0 
sl@0: 
sl@0: ;
sl@0: ; Thumb Back Branch and link
sl@0: ;
sl@0: RMDebug_StepTest_Thumb_Back_Branch_And_Link
sl@0: 	mov		r0, lr	; preserve lr
sl@0: 	blx		RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
sl@0: 	bx		r0 
sl@0: 
sl@0: ;
sl@0: ; Thumb ADD PC,PC, #0
sl@0: ;
sl@0: RMDebug_StepTest_Thumb_AddPC
sl@0: 	mov		r0, lr	; preserve lr
sl@0: 	blx		RMDebug_StepTest_Thumb_AddPC_1
sl@0: 	bx		r0 
sl@0: 
sl@0: 	CODE16
sl@0: 
sl@0: 	; Thumb tests
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying_1
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying_2
sl@0: 
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_1
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_2
sl@0: 
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_And_Link
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_1
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_2
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_3
sl@0: 
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_2
sl@0: 	EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
sl@0: 
sl@0: RMDebug_StepTest_Thumb_Non_PC_Modifying_1
sl@0: 	mov		r0, r0	; nop
sl@0: RMDebug_StepTest_Thumb_Non_PC_Modifying_2
sl@0: 	bx		lr	
sl@0: 
sl@0: RMDebug_StepTest_Thumb_Branch_1
sl@0: 	b		RMDebug_StepTest_Thumb_Branch_2
sl@0: 	mov		r0, r0
sl@0: RMDebug_StepTest_Thumb_Branch_2
sl@0: 	bx		lr
sl@0: 
sl@0: RMDebug_StepTest_Thumb_Branch_And_Link_1
sl@0: 	mov		r1, lr
sl@0: RMDebug_StepTest_Thumb_Branch_And_Link_2
sl@0: 	bl		RMDebug_StepTest_Thumb_Branch_And_Link_3
sl@0: 	mov		r0, r0
sl@0: RMDebug_StepTest_Thumb_Branch_And_Link_3
sl@0: 	bx		r1
sl@0: 
sl@0: RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
sl@0: 	bx		r1
sl@0: 
sl@0: RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
sl@0: 	mov		r1, lr
sl@0: RMDebug_StepTest_Thumb_Back_Branch_And_Link_2
sl@0: 	bl		RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
sl@0: 	bx		r1
sl@0: 
sl@0: ;
sl@0: ; ADD PC
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_Thumb_AddPC
sl@0: 	EXPORT RMDebug_StepTest_Thumb_AddPC_1
sl@0: 	EXPORT RMDebug_StepTest_Thumb_AddPC_2
sl@0: 	EXPORT RMDebug_StepTest_Thumb_AddPC_3
sl@0: 
sl@0: RMDebug_StepTest_Thumb_AddPC_1
sl@0: 	mov		r1, lr
sl@0: 	mov		r2, #4
sl@0: RMDebug_StepTest_Thumb_AddPC_2
sl@0: 	add		pc, pc, r2	; should arrive at RMDebug_StepTest_Thumb_AddPC_3
sl@0: 	mov		r0, r0
sl@0: 	mov		r0, r0
sl@0: 	mov		r0, r0
sl@0: RMDebug_StepTest_Thumb_AddPC_3
sl@0: 	bx		r1
sl@0: 
sl@0: 	ALIGN 4
sl@0: 
sl@0: 	CODE32
sl@0: 
sl@0: ;
sl@0: ; ARM multiple-step ( 5 steps )
sl@0: ;
sl@0: 	EXPORT RMDebug_StepTest_ARM_Step_Multiple
sl@0: 	EXPORT RMDebug_StepTest_ARM_Step_Multiple_1
sl@0: 
sl@0: RMDebug_StepTest_ARM_Step_Multiple
sl@0: 	mov		r0,r0		; nop
sl@0: 	mov		r0,r0		; nop
sl@0: 	mov		r0,r0		; nop
sl@0: 	mov		r0,r0		; nop
sl@0: 	mov		r0,r0		; nop
sl@0: RMDebug_StepTest_ARM_Step_Multiple_1
sl@0: 	bx		lr
sl@0: 
sl@0: 	END
sl@0: 
sl@0: ; End of file - d_rmdebug_bkpt.s