sl@0: // Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\nkernsmp\x86\ncirq.cpp
sl@0: // 
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @internalTechnology
sl@0: */
sl@0: 
sl@0: #include "nk_priv.h"
sl@0: #include "nk_plat.h"
sl@0: #include <nk_irq.h>
sl@0: #include <apic.h>
sl@0: 
sl@0: #ifdef _DEBUG
sl@0: #define DMEMDUMP(base,size)	DbgMemDump((TLinAddr)base,size)
sl@0: void DbgMemDump(TLinAddr aBase, TInt aSize)
sl@0: 	{
sl@0: 	TInt off;
sl@0: 	const TUint8* p=(const TUint8*)aBase;
sl@0: 	NKern::Lock();
sl@0: 	for (off=0; off<aSize; off+=16, p+=16)
sl@0: 		{
sl@0: 		DEBUGPRINT("%08x: %02x %02x %02x %02x  %02x %02x %02x %02x | %02x %02x %02x %02x  %02x %02x %02x %02x",
sl@0: 			p,		p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
sl@0: 					p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
sl@0: 		}
sl@0: 	NKern::Unlock();
sl@0: 	}
sl@0: #else
sl@0: #define DMEMDUMP(base,size)
sl@0: #endif
sl@0: 
sl@0: #define	IO_APIC_BASE			0xFEC00000
sl@0: #define	IO_APIC_REGSEL_OFFSET	0x00
sl@0: #define	IO_APIC_IOWIN_OFFSET	0x10
sl@0: 
sl@0: #define	IO_APIC_REG_ID			0x00
sl@0: #define	IO_APIC_REG_VER			0x01
sl@0: #define	IO_APIC_REG_ARB			0x02
sl@0: 
sl@0: #define IO_APIC_CTRL_IMASK			0x10000		// 1 = masked
sl@0: #define	IO_APIC_CTRL_LEVEL			0x08000		// 1 = level triggered, 0 = edge
sl@0: #define	IO_APIC_CTRL_REMOTE_IRR		0x04000		//
sl@0: #define	IO_APIC_CTRL_INTPOL_LOW		0x02000		// 1 = active low
sl@0: #define	IO_APIC_CTRL_DELIVS			0x01000		//
sl@0: #define	IO_APIC_CTRL_DESTMOD		0x00800		// 1 = logical, 0 = physical
sl@0: #define	IO_APIC_CTRL_DELMOD_MASK	0x00700
sl@0: #define	IO_APIC_CTRL_DELMOD_FIXED	0x00000
sl@0: #define	IO_APIC_CTRL_DELMOD_LOWP	0x00100
sl@0: #define	IO_APIC_CTRL_DELMOD_SMI		0x00200
sl@0: #define	IO_APIC_CTRL_DELMOD_NMI		0x00400
sl@0: #define	IO_APIC_CTRL_DELMOD_INIT	0x00500
sl@0: #define	IO_APIC_CTRL_DELMOD_EXTINT	0x00700
sl@0: #define	IO_APIC_CTRL_INTVEC_MASK	0x000FF
sl@0: 
sl@0: 
sl@0: /******************************************************************************
sl@0:  * IO APIC
sl@0:  ******************************************************************************/
sl@0: 
sl@0: #define IO_APIC_SELECT(x)		((void)(*(volatile TUint32*)(iAddr + IO_APIC_REGSEL_OFFSET) = (x)))
sl@0: #define	IO_APIC_REG				(*(volatile TUint32*)(iAddr + IO_APIC_IOWIN_OFFSET))
sl@0: 
sl@0: class TIoApic
sl@0: 	{
sl@0: public:
sl@0: 	TIoApic(TLinAddr aAddr);
sl@0: 	TUint32 Id();
sl@0: 	TUint32 Ver();
sl@0: 	TUint32 Arb();
sl@0: 	TUint32 Dest(TInt aIndex);
sl@0: 	TUint32 Control(TInt aIndex);
sl@0: 	TUint32 ModifyDest(TInt aIndex, TUint32 aNewDest);
sl@0: 	TUint32 ModifyControl(TInt aIndex, TUint32 aClear, TUint32 aSet);
sl@0: 
sl@0: 	void Dump();
sl@0: public:
sl@0: 	TSpinLock iLock;
sl@0: 	TLinAddr iAddr;
sl@0: 	};
sl@0: 
sl@0: TIoApic TheIoApic(IO_APIC_BASE);
sl@0: 
sl@0: TIoApic::TIoApic(TLinAddr aAddr)
sl@0: 	: iLock(TSpinLock::EOrderBTrace)
sl@0: 	{
sl@0: 	iAddr = aAddr;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::Id()
sl@0: 	{
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(IO_APIC_REG_ID);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::Ver()
sl@0: 	{
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(IO_APIC_REG_VER);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::Arb()
sl@0: 	{
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(IO_APIC_REG_ARB);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::Dest(TInt aIndex)
sl@0: 	{
sl@0: 	TUint32 reg = 2*aIndex + 0x11;
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(reg);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x>>24;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::Control(TInt aIndex)
sl@0: 	{
sl@0: 	TUint32 reg = 2*aIndex + 0x10;
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(reg);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::ModifyDest(TInt aIndex, TUint32 aNewDest)
sl@0: 	{
sl@0: 	TUint32 reg = 2*aIndex + 0x11;
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(reg);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	IO_APIC_REG = (x&0x00ffffffu) | (aNewDest<<24);
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x>>24;
sl@0: 	}
sl@0: 
sl@0: TUint32 TIoApic::ModifyControl(TInt aIndex, TUint32 aClear, TUint32 aSet)
sl@0: 	{
sl@0: 	TUint32 reg = 2*aIndex + 0x10;
sl@0: 	TInt irq = __SPIN_LOCK_IRQSAVE(iLock);
sl@0: 	IO_APIC_SELECT(reg);
sl@0: 	TUint32 x = IO_APIC_REG;
sl@0: 	x &= ~aClear;
sl@0: 	x |= aSet;
sl@0: 	IO_APIC_SELECT(reg);
sl@0: 	IO_APIC_REG = x;
sl@0: 	__SPIN_UNLOCK_IRQRESTORE(iLock,irq);
sl@0: 	return x;
sl@0: 	}
sl@0: 
sl@0: void TIoApic::Dump()
sl@0: 	{
sl@0: 	TUint32 id = Id();
sl@0: 	TUint32 ver = Ver();
sl@0: 	TUint32 arb = Arb();
sl@0: 	__KTRACE_OPT(KBOOT,DEBUGPRINT("IOAPIC ID=%08x VER=%08x ARB=%08x", id, ver, arb));
sl@0: 
sl@0: 	TInt max = (ver>>16)&0xff;
sl@0: 	TInt i;
sl@0: 	for (i=0; i<=max; ++i)
sl@0: 		{
sl@0: 		TUint32 dest = Dest(i);
sl@0: 		TUint32 ctrl = Control(i);
sl@0: 		__KTRACE_OPT(KBOOT,DEBUGPRINT("IOAPIC[%02x] DEST=%02x CTRL=%08x", i, dest, ctrl));
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: 
sl@0: void NIrq::HwEoi()
sl@0: 	{
sl@0: 	if (iX && iX->iEoiFn)
sl@0: 		(*iX->iEoiFn)(this);
sl@0: 	else
sl@0: 		{
sl@0: 		volatile TUint32* const apic_eoi = (volatile TUint32*)(X86_LOCAL_APIC_BASE + X86_LOCAL_APIC_OFFSET_EOI);
sl@0: 		*apic_eoi = 0;
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwEnable()
sl@0: 	{
sl@0: 	if (iX && iX->iEnableFn)
sl@0: 		(*iX->iEnableFn)(this);
sl@0: 	else
sl@0: 		{
sl@0: //		if ((iStaticFlags & ELevel) || (iIState & ERaw))
sl@0: 			TheIoApic.ModifyControl(iIndex, IO_APIC_CTRL_IMASK, 0);
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwDisable()
sl@0: 	{
sl@0: 	if (iX && iX->iDisableFn)
sl@0: 		(*iX->iDisableFn)(this);
sl@0: 	else
sl@0: 		{
sl@0: 		if ((iStaticFlags & ELevel) || (iIState & ERaw))
sl@0: 			TheIoApic.ModifyControl(iIndex, 0, IO_APIC_CTRL_IMASK);
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwSetCpu(TInt aCpu)
sl@0: 	{
sl@0: 	if (iX && iX->iSetCpuFn)
sl@0: 		(*iX->iSetCpuFn)(this, 1u<<aCpu);
sl@0: 	else
sl@0: 		{
sl@0: 		TheIoApic.ModifyDest(iIndex, 1u<<aCpu);
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwSetCpuMask(TUint32 aMask)
sl@0: 	{
sl@0: 	if (iX && iX->iSetCpuFn)
sl@0: 		(*iX->iSetCpuFn)(this, aMask);
sl@0: 	else
sl@0: 		{
sl@0: 		TheIoApic.ModifyDest(iIndex, aMask);
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwInit()
sl@0: 	{
sl@0: 	if (iX && iX->iInitFn)
sl@0: 		(*iX->iInitFn)(this);
sl@0: 	else
sl@0: 		{
sl@0: 		__KTRACE_OPT(KBOOT,DEBUGPRINT("NIrq %02x HwInit", iIndex));
sl@0: 		TUint32 clear = IO_APIC_CTRL_INTVEC_MASK;
sl@0: 		TUint32 set = iVector & IO_APIC_CTRL_INTVEC_MASK;
sl@0: 		set |= IO_APIC_CTRL_IMASK;
sl@0: 		if (iStaticFlags & ELevel)
sl@0: 			set |= (IO_APIC_CTRL_LEVEL /*| IO_APIC_CTRL_IMASK*/);
sl@0: 		else
sl@0: 			clear |= (IO_APIC_CTRL_LEVEL /*| IO_APIC_CTRL_IMASK*/);
sl@0: 		if (iStaticFlags & EPolarity)
sl@0: 			clear |= IO_APIC_CTRL_INTPOL_LOW;
sl@0: 		else
sl@0: 			set |= IO_APIC_CTRL_INTPOL_LOW;
sl@0: 		TheIoApic.ModifyControl(iIndex, clear, set);
sl@0: 		TheIoApic.Dump();
sl@0: 		}
sl@0: 	}
sl@0: 
sl@0: TBool NIrq::HwPending()
sl@0: 	{
sl@0: 	if (iX && iX->iPendingFn)
sl@0: 		return (*iX->iPendingFn)(this);
sl@0: 	return FALSE;
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwWaitCpus()
sl@0: 	{
sl@0: 	if (iX && iX->iWaitFn)
sl@0: 		(*iX->iWaitFn)(this);
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwInit0()
sl@0: 	{
sl@0: 	TheIoApic.Dump();
sl@0: 	TInt n = 1 + (TheIoApic.Ver() >> 16);
sl@0: 	TInt i;
sl@0: 	for (i=0; i<n; ++i)
sl@0: 		{
sl@0: 		TheIoApic.ModifyControl(i,
sl@0: 			IO_APIC_CTRL_DELMOD_MASK | IO_APIC_CTRL_INTVEC_MASK | IO_APIC_CTRL_LEVEL | IO_APIC_CTRL_INTPOL_LOW,
sl@0: 			IO_APIC_CTRL_DESTMOD | IO_APIC_CTRL_IMASK | 0xff);
sl@0: 		TheIoApic.ModifyDest(i, 0x01);
sl@0: 		if (i>15)
sl@0: 			{
sl@0: 			TheIoApic.ModifyControl(i, 0, IO_APIC_CTRL_LEVEL | IO_APIC_CTRL_INTPOL_LOW);
sl@0: 			}
sl@0: 		}
sl@0: 	TheIoApic.Dump();
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwInit1()
sl@0: 	{
sl@0: 	write_apic_reg(SIVR, 0x300 | SPURIOUS_INTERRUPT_VECTOR);
sl@0: 	write_apic_reg(DIVCNF, 10);				// APIC timer clock divide by 128 (bus clock freq / 128)
sl@0: 	write_apic_reg(LVTTMR, 0x10000|TIMESLICE_VECTOR);
sl@0: 	write_apic_reg(DFR, 0xf0000000u);		// set flat logical destination mode
sl@0: 	write_apic_reg(LDR, 0x01000000u);		// this CPU will be selected by logical destination with bit 0 set
sl@0: 	}
sl@0: 
sl@0: void NIrq::HwInit2AP()
sl@0: 	{
sl@0: 	TInt cpu = NKern::CurrentCpu();
sl@0: 	write_apic_reg(SIVR, 0x300 | SPURIOUS_INTERRUPT_VECTOR);
sl@0: 	write_apic_reg(DIVCNF, 10);
sl@0: 	write_apic_reg(LVTTMR, 0x10000|TIMESLICE_VECTOR);
sl@0: 	write_apic_reg(DFR, 0xf0000000u);		// set flat logical destination mode
sl@0: 	write_apic_reg(LDR, 0x01000000u<<cpu);	// this CPU will be selected by logical destination with bit n set
sl@0: 	}