sl@0: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\nkernsmp\arm\ncthrd.cia
sl@0: // 
sl@0: //
sl@0: 
sl@0: #define __INCLUDE_NTHREADBASE_DEFINES__
sl@0: 
sl@0: #include <arm.h>
sl@0: #include <e32cia.h>
sl@0: 
sl@0: #undef	iDfcState
sl@0: #define	iDfcState		i8816.iHState16
sl@0: 
sl@0: extern "C" void send_accumulated_resched_ipis();
sl@0: 
sl@0: /******************************************************************************
sl@0:  * Thread
sl@0:  ******************************************************************************/
sl@0: extern "C" __NAKED__ void __StartThread()
sl@0: 	{
sl@0: 	// On entry:
sl@0: 	//		R0->TSubScheduler, R1=0, R2=1, R3->current thread
sl@0: 	//		R12=resched IPIs
sl@0: 	// Interrupts disabled
sl@0: 
sl@0: 	// need to send any outstanding reschedule IPIs
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("blne " CSM_CFUNC(send_accumulated_resched_ipis));
sl@0: #ifdef __USER_MEMORY_GUARDS_ENABLED__
sl@0: 	asm("ldr	r0, [sp, #%a0]" : : "i" _FOFF(SThreadExcStack, iCPSR));
sl@0: 	asm("tst	r0, #0x0f ");
sl@0: 	asm("bne	2f ");
sl@0: 	USER_MEMORY_GUARD_OFF(,r0,r0);
sl@0: 	asm("2:		");
sl@0: #endif
sl@0: 	asm("ldmia	sp, {r0-r14}^ ");			// load initial values for R0-R12, R13_usr, R14_usr
sl@0: 	asm("nop	");							// don't access banked register immediately after
sl@0: 	asm("add	sp, sp, #64 ");				// point to saved PC, CPSR (skip iExcCode)
sl@0: 	asm("adr	lr, 1f ");					// set lr_svc in case thread returns
sl@0: 	RFEIAW(13);								// restore PC and CPSR - jump to thread entry point
sl@0: 
sl@0: 	asm("1:		");
sl@0: 	asm("b "	CSM_ZN5NKern4ExitEv);		// if control returns, call NKern::Exit()
sl@0: 	}
sl@0: 
sl@0: 
sl@0: extern "C" __NAKED__ TInt get_kernel_context_type(TLinAddr /*aReschedReturn*/)
sl@0: 	{
sl@0: 	asm("adr	r1, 9f ");
sl@0: 	asm("mov	r3, r0 ");
sl@0: 	asm("mvn	r0, #0 ");
sl@0: 	asm("1:		");
sl@0: 	asm("ldr	r2, [r1], #4 ");
sl@0: 	asm("add	r0, r0, #1 ");
sl@0: 	asm("cmp	r2, r3 ");
sl@0: 	asm("beq	2f ");
sl@0: 	asm("cmp	r2, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("mvn	r0, #0 ");
sl@0: 	asm("2:		");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("9:		");
sl@0: 	asm(".word " CSM_CFUNC(__StartThread));
sl@0: 	asm(".word	nkern_unlock_resched_return ");
sl@0: 	asm(".word	nkern_preemption_point_resched_return ");
sl@0: 	asm(".word	nkern_wfar_resched_return ");
sl@0: 	asm(".word	irq_resched_return ");
sl@0: 	asm(".word	exec_wfar_resched_return ");
sl@0: 	asm(".word	0 ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Mark the beginning of an event handler tied to a thread or thread group
sl@0: 
sl@0: 	Return the number of the CPU on which the event handler should run
sl@0: */
sl@0: __NAKED__ TInt NSchedulable::BeginTiedEvent()
sl@0: 	{
sl@0: 	asm("add r1, r0, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("1: ");
sl@0: 	LDREX(0,1);						// r0 = original value of iEventState
sl@0: 	asm("add r2, r0, #%a0" : : "i" ((TInt)EEventCountInc));
sl@0: 	STREX(3,2,1);
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r3);
sl@0: 	asm("tst r0, #%a0" : : "i" ((TInt)EEventParent));
sl@0: 	asm("ldrne r2, [r1, #%a0]" : : "i" (_FOFF(NSchedulable,iParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("beq bte0 ");				// EEventParent not set so don't look at group
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("addne r2, r2, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("beq bte_bad ");
sl@0: 	asm("cmp r2, r1 ");
sl@0: 	asm("beq bte2 ");				// parent not yet updated, use iNewParent
sl@0: 	asm("bte1: ");
sl@0: 	LDREX(0,2);						// r0 = original value of iEventState
sl@0: 	asm("add r3, r0, #%a0" : : "i" ((TInt)EEventCountInc));
sl@0: 	STREX(12,3,2);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("bte0: ");
sl@0: 	asm("and r0, r0, #%a0" : : "i" ((TInt)EEventCpuMask));
sl@0: 	__JUMP(,lr);					// return event CPU
sl@0: 
sl@0: 	asm("bte2: ");
sl@0: 	__DATA_MEMORY_BARRIER__(r3);	// make sure iNewParent is read after iParent
sl@0: 	asm("ldr r2, [r1, #%a0]" : : "i" (_FOFF(NThreadBase,iNewParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("addne r2, r2, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("bne bte1 ");				// iNewParent set so OK
sl@0: 	__DATA_MEMORY_BARRIER__(r3);	// make sure iParent is read after iNewParent
sl@0: 	asm("ldr r2, [r1, #%a0]" : : "i" (_FOFF(NSchedulable,iParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("addne r2, r2, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("cmp r2, r1 ");
sl@0: 	asm("bne bte1 ");				// iParent now set so OK, otherwise something is wrong
sl@0: 
sl@0: 	asm("bte_bad: ");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Mark the end of an event handler tied to a thread or thread group
sl@0: 
sl@0: */
sl@0: __NAKED__ void NSchedulable::EndTiedEvent()
sl@0: 	{
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("ldr r1, [r0, #%a0]!" : : "i" _FOFF(NSchedulable, iEventState));
sl@0: 	asm("tst r1, #%a0" : : "i" ((TInt)EEventParent));
sl@0: 	asm("bne etep0 ");				// branch out if EEventParent set
sl@0: 
sl@0: 	// r0->NSchedulable::iEventState
sl@0: 	asm("ete1: ");
sl@0: 	LDREX(1,0);
sl@0: 	asm("sub r1, r1, #%a0" : : "i" ((TInt)EEventCountInc));	// decrement event count
sl@0: 	asm("cmp r1, #%a0" : : "i" ((TInt)EEventCountInc));		// check if now zero
sl@0: 	asm("biccc r1, r1, #0xFF ");	// if so, mask event CPU ...
sl@0: 	asm("andcc r2, r1, #0x1F00 ");	// ... and r2 = thread CPU << 8 ...
sl@0: 	asm("orrcc r1, r1, r2, lsr #8 ");	// ... and event CPU = thread CPU
sl@0: 	STREX(12,1,0);
sl@0: 	asm("teq r12, #0 ");			// test for success, leave carry alone
sl@0: 	asm("bne ete1 ");				// retry if STREX failed
sl@0: 	asm("bcs ete2 ");				// if not last tied event, finish
sl@0: 	asm("tst r1, #%a0" : : "i" ((TInt)EDeferredReady));
sl@0: 	asm("addne r0, r0, #%a0" : : "i" (_FOFF(NSchedulable,i_IDfcMem) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("bne " CSM_ZN4TDfc3AddEv );	// if deferred ready, add IDFC to action it
sl@0: 	asm("ete2: ");					// ready not deferred so finish
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("etep0: ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);	// make sure iParent is read after seeing parent flag set
sl@0: 	asm("ldr r3, [r0, #%a0]" : : "i" (_FOFF(NSchedulable,iParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("addne r3, r3, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("beq ete_bad ");			// no parent - shouldn't happen
sl@0: 	asm("cmp r3, r0 ");				// parent == this ?
sl@0: 	asm("beq etep1 ");				// if so, parent not yet updated so use iNewParent
sl@0: 
sl@0: 	asm("etep2: ");
sl@0: 	asm("stmfd sp!, {r0,lr} ");		// save this and return address
sl@0: 	asm("mov r0, r3 ");				// operate on parent
sl@0: 	asm("bl ete1 ");				// update parent state
sl@0: 	asm("ldmfd sp!, {r0,lr} ");
sl@0: 	asm("1: ");
sl@0: 	LDREX(1,0);
sl@0: 	asm("sub r1, r1, #%a0" : : "i" ((TInt)EEventCountInc));	// decrement event count
sl@0: 	STREX(12,1,0);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("etep1: ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);	// make sure iNewParent is read after iParent
sl@0: 	asm("ldr r3, [r0, #%a0]" : : "i" (_FOFF(NThreadBase,iNewParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("addne r3, r3, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("bne etep2 ");				// iNewParent set so OK
sl@0: 	__DATA_MEMORY_BARRIER__(r12);	// make sure iParent is read after iNewParent
sl@0: 	asm("ldr r3, [r0, #%a0]" : : "i" (_FOFF(NSchedulable,iParent) - _FOFF(NSchedulable,iEventState)));
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("addne r3, r3, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("cmp r3, r0 ");
sl@0: 	asm("bne etep2 ");				// iParent now set so OK, otherwise something is wrong
sl@0: 
sl@0: 	asm("ete_bad: ");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Check for concurrent tied events when a thread/group becomes ready
sl@0: 
sl@0: 	This is only ever called on a lone thread or a group, not on a thread
sl@0: 	which is part of a group.
sl@0: 
sl@0: 	Update the thread CPU field in iEventState
sl@0: 	If thread CPU != event CPU and event count nonzero, atomically
sl@0: 	set the ready deferred flag and return TRUE, else return FALSE.
sl@0: 	If event count zero, set event CPU = thread CPU atomically.
sl@0: 
sl@0: 	@param aCpu the CPU on which the thread/group is to become ready
sl@0: 	@return	TRUE if the ready must be deferred.
sl@0: */
sl@0: __NAKED__ TBool NSchedulable::TiedEventReadyInterlock(TInt /*aCpu*/)
sl@0: 	{
sl@0: 	asm("add r0, r0, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,0);						// r2 = original iEventState
sl@0: 	asm("bic r3, r2, #0x1F00 ");	// r3 = original iEventState with thread CPU zeroed out
sl@0: 	asm("orr r3, r3, r1, lsl #8 ");	// set thread CPU field = aCpu
sl@0: 	asm("cmp r3, #%a0" : : "i" ((TInt)EEventCountInc));
sl@0: 	asm("bhs 2f ");					// branch if event count nonzero
sl@0: 	asm("bic r3, r3, #0xFF ");		// else mask event CPU ...
sl@0: 	asm("orr r3, r3, r1 ");			// ... and set event CPU = thread CPU = aCpu
sl@0: 	asm("3: ");
sl@0: 	STREX(12,3,0);
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	asm("eor r0, r2, r3 ");			// r0 = old event state ^ new event state
sl@0: 	asm("and r0, r0, #%a0" : : "i" ((TInt)EDeferredReady));
sl@0: 	__JUMP(,lr);					// return TRUE if we just set EDeferredReady
sl@0: 
sl@0: 	// event count is nonzero
sl@0: 	asm("2: ");
sl@0: 	asm("eor r12, r3, r3, lsr #8 ");	// r12 bottom 5 bits = thread CPU ^ event CPU
sl@0: 	asm("tst r12, #0x1F ");				// thread CPU == event CPU?
sl@0: 	asm("orrne r3, r3, #%a0" : : "i" ((TInt)EDeferredReady));	// if not, set EDeferredReady
sl@0: 	asm("b 3b ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Check for concurrent tied events when a thread leaves a group
sl@0: 
sl@0: 	If event count zero, atomically	set the event and thread CPUs to the
sl@0: 	current CPU, clear the parent flag and return TRUE, else return FALSE.
sl@0: 
sl@0: 	@return	TRUE if the parent flag has been cleared
sl@0: 	@pre	Preemption disabled
sl@0: */
sl@0: __NAKED__ TBool NThreadBase::TiedEventLeaveInterlock()
sl@0: 	{
sl@0: 	GET_RWNO_TID(, r1);					// R1->SubScheduler
sl@0: 	asm("ldr r1, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, iCpuNum));
sl@0: 	asm("add r0, r0, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("orr r1, r1, r1, lsl #8 ");		// event CPU = thread CPU = this CPU, EDeferredReady, EEventParent clear
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,0);
sl@0: 	asm("cmp r2, #%a0" : : "i" ((TInt)EEventCountInc));		// check if event count zero
sl@0: 	asm("bhs 0f ");						// if not, finish and return FALSE
sl@0: 	STREX(3,1,0);						// else update CPUs and clear parent flag
sl@0: 								// NOTE: Deferred ready flag must have been clear since thread is running
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__JUMP(,lr);				// return TRUE (assumes this!=0)
sl@0: 	asm("0:");
sl@0: 	asm("mov r0, #0 ");
sl@0: 	__JUMP(,lr);				// return FALSE
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Check for concurrent tied events when a thread joins a group
sl@0: 
sl@0: 	If event count zero, atomically	set the parent flag and return TRUE,
sl@0: 	else return FALSE.
sl@0: 
sl@0: 	@return	TRUE if the parent flag has been set
sl@0: 	@pre	Preemption disabled
sl@0: */
sl@0: __NAKED__ TBool NThreadBase::TiedEventJoinInterlock()
sl@0: 	{
sl@0: 	asm("add r0, r0, #%a0" : : "i" _FOFF(NSchedulable,iEventState));
sl@0: 	asm("1: ");
sl@0: 	LDREX(1,0);
sl@0: 	asm("cmp r1, #%a0" : : "i" ((TInt)EEventCountInc));		// check if event count zero
sl@0: 	asm("bhs 0f ");						// if not, finish and return FALSE
sl@0: 	asm("orr r2, r1, #%a0" : : "i" ((TInt)EEventParent));	// else set parent flag
sl@0: 	STREX(3,2,0);
sl@0: 	asm("cmp r3, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__JUMP(,lr);				// return TRUE (assumes this!=0)
sl@0: 	asm("0:");
sl@0: 	asm("mov r0, #0 ");
sl@0: 	__JUMP(,lr);				// return FALSE
sl@0: 	}
sl@0: 
sl@0: 
sl@0: #ifdef __FAST_SEM_MACHINE_CODED__
sl@0: /******************************************************************************
sl@0:  * Fast semaphore
sl@0:  ******************************************************************************/
sl@0: 
sl@0: /** Waits on a fast semaphore.
sl@0: 
sl@0:     Decrements the signal count for the semaphore and
sl@0: 	removes the calling thread from the ready-list if the semaphore becomes
sl@0: 	unsignalled. Only the thread that owns a fast semaphore can wait on it.
sl@0: 	
sl@0: 	Note that this function does not block, it merely updates the NThread state,
sl@0: 	rescheduling will only occur when the kernel is unlocked. Generally threads
sl@0: 	would use NKern::FSWait() which manipulates the kernel lock for you.
sl@0: 
sl@0: 	@pre The calling thread must own the semaphore.
sl@0: 	@pre No fast mutex can be held.
sl@0: 	@pre Kernel must be locked.
sl@0: 	
sl@0: 	@post Kernel is locked.
sl@0: 	
sl@0: 	@see NFastSemaphore::Signal()
sl@0: 	@see NKern::FSWait()
sl@0: 	@see NKern::Unlock()
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NFastSemaphore::Wait()
sl@0: 	{
sl@0: 	ASM_DEBUG1(FSWait,r0);
sl@0: 
sl@0: 	GET_RWNO_TID(,r1);
sl@0: 	asm("stmfd	sp!, {r4-r7} ");
sl@0: 	asm("ldr	r6, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("mov	r3, r0 ");
sl@0: 	asm("mov	r2, #%a0" : : "i" ((TInt)NThreadBase::EWaitFastSemaphore << 8));
sl@0: 	asm("add	r7, r6, #%a0" : : "i" _FOFF(NThreadBase, iWaitState));
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)NThreadWaitState::EWtStWaitPending));
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,7);
sl@0: 	STREXD(		12,2,7);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r12, [r7, #%a0]" : : "i" _FOFF(NThreadWaitState, iTimer.iTriggerTime));
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("bne	0f ");
sl@0: 
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,0);					// count
sl@0: 	asm("mov	r5, r6, lsr #2 ");		// thread>>2
sl@0: 	asm("orr	r5, r5, #0x80000000 ");
sl@0: 	asm("subs	r4, r2, #1 ");
sl@0: 	asm("movlt	r4, r5 ");				// if --count<0, r4=(thread>>2)|0x80000000
sl@0: 	STREX(		12,4,0);
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 
sl@0: 	asm("cmp	r2, #0 ");				// original count zero ?
sl@0: 	asm("bne	2f ");					// if yes, don't need to wait
sl@0: 	asm("mov	r2, #1 ");
sl@0: 	asm("strb	r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iRescheduleNeededFlag));	// else we need to reschedule
sl@0: 	asm("ldmfd	sp!, {r4-r7} ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,7);
sl@0: 	STREXD(		12,2,7);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)(NThreadWaitState::EWtStDead|NThreadWaitState::EWtStWaitActive)));
sl@0: 	asm("bne	0f ");
sl@0: 	asm("ldmfd	sp!, {r4-r7} ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Waits on a fast semaphore.
sl@0: 
sl@0:     Decrements the signal count for the semaphore
sl@0: 	and waits for a signal if the semaphore becomes unsignalled. Only the
sl@0: 	thread that owns a fast	semaphore can wait on it.
sl@0: 
sl@0: 	@param aSem The semaphore to wait on.
sl@0: 	
sl@0: 	@pre The calling thread must own the semaphore.
sl@0: 	@pre No fast mutex can be held.
sl@0: 	
sl@0: 	@see NFastSemaphore::Wait()
sl@0: */
sl@0: EXPORT_C __NAKED__ void NKern::FSWait(NFastSemaphore* /*aSem*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKFSWait,r0);
sl@0: 
sl@0: 	__ASM_CLI();							// all interrupts off
sl@0: 	GET_RWNO_TID(,r1);
sl@0: 	asm("stmfd	sp!, {r4,r5,r11,lr} ");
sl@0: 	asm("ldr	r11, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("mov	r2, #%a0" : : "i" ((TInt)NThreadBase::EWaitFastSemaphore << 8));
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)NThreadWaitState::EWtStWaitPending));
sl@0: 	asm("mov	r3, r0 ");
sl@0: 	asm("add	r0, r11, #%a0" : : "i" _FOFF(NThreadBase, iWaitState));
sl@0: 	asm("b		nkfswait1 ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Waits for a signal on the current thread's I/O semaphore.
sl@0: 
sl@0: 	@pre No fast mutex can be held.
sl@0: 	@pre Call in a thread context.
sl@0: 	@pre Kernel must be unlocked
sl@0: 	@pre interrupts enabled
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NKern::WaitForAnyRequest()
sl@0: 	{
sl@0: 	ASM_DEBUG0(WFAR);
sl@0: 
sl@0: 	__ASM_CLI();							// all interrupts off
sl@0: 	GET_RWNO_TID(,r1);
sl@0: 	asm("stmfd	sp!, {r4,r5,r11,lr} ");
sl@0: 	asm("ldr	r11, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("mov	r2, #%a0" : : "i" ((TInt)NThreadBase::EWaitFastSemaphore << 8));
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)NThreadWaitState::EWtStWaitPending));
sl@0: 	asm("add	r0, r11, #%a0" : : "i" _FOFF(NThreadBase, iWaitState));
sl@0: 	asm("add	r3, r11, #%a0" : : "i" _FOFF(NThreadBase, iRequestSemaphore));
sl@0: 
sl@0: 	asm("nkfswait1: ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(NThreadWaitState, iTimer.iTriggerTime));
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("bne	0f ");
sl@0: 
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,3);					// count
sl@0: 	asm("mov	r5, r11, lsr #2 ");		// thread>>2
sl@0: 	asm("orr	r5, r5, #0x80000000 ");
sl@0: 	asm("subs	r4, r2, #1 ");
sl@0: 	asm("movlt	r4, r5 ");				// if --count<0, r4=(thread>>2)|0x80000000
sl@0: 	STREX(		12,4,3);
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 
sl@0: 	asm("cmp	r2, #0 ");				// original count zero ?
sl@0: 	asm("beq	2f ");					// if so we must wait
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)(NThreadWaitState::EWtStDead|NThreadWaitState::EWtStWaitActive)));
sl@0: 	asm("bne	0f ");
sl@0: 	__ASM_STI();
sl@0: 	__POPRET("r4,r5,r11,");
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__ASM_CRASH();
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	asm("ldmfd	sp!, {r4-r5} ");
sl@0: 	asm("mov	r2, #1 ");
sl@0: 	asm("str	r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));			// else lock the kernel
sl@0: 	__ASM_STI();
sl@0: 	asm("strb	r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iRescheduleNeededFlag));	// and set the reschedule flag
sl@0: 	asm("stmfd	sp!, {r0,r4-r10} ");
sl@0: 	asm("bl "	CSM_ZN10TScheduler10RescheduleEv );	// reschedule
sl@0: 	asm(".global nkern_wfar_resched_return ");
sl@0: 	asm("nkern_wfar_resched_return: ");
sl@0: 
sl@0: 	// need to send any outstanding reschedule IPIs
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("blne " CSM_CFUNC(send_accumulated_resched_ipis));
sl@0: 	__ASM_STI();
sl@0: 	__POPRET("r0,r4-r11,");
sl@0: 
sl@0: 	asm(".global wait_for_any_request ");
sl@0: 	asm("wait_for_any_request: ");
sl@0: 	asm("add	r3, r9, #%a0" : : "i" _FOFF(NThreadBase,iRequestSemaphore));
sl@0: 	asm("mov	r2, #%a0" : : "i" ((TInt)NThreadBase::EWaitFastSemaphore << 8));
sl@0: 	asm("add	r7, r9, #%a0" : : "i" _FOFF(NThreadBase, iWaitState));
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)NThreadWaitState::EWtStWaitPending));
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,7);
sl@0: 	STREXD(		12,2,7);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r12, [r7, #%a0]" : : "i" _FOFF(NThreadWaitState, iTimer.iTriggerTime));
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("bne	0b ");
sl@0: 
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("1:		");
sl@0: 	LDREX(		0,3);					// count
sl@0: 	asm("mov	r5, r9, lsr #2 ");		// thread>>2
sl@0: 	asm("orr	r5, r5, #0x80000000 ");
sl@0: 	asm("subs	r4, r0, #1 ");
sl@0: 	asm("movlt	r4, r5 ");				// if --count<0, r4=(thread>>2)|0x80000000
sl@0: 	STREX(		12,4,3);
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef __RECORD_STATE__
sl@0: 	asm("str	r0, [r9, #%a0]" : : "i" _FOFF(NThreadBase,iNThreadBaseSpare6));
sl@0: #endif
sl@0: 
sl@0: 	asm("cmp	r0, #0 ");				// original count zero ?
sl@0: 	asm("beq	exec_wfar_wait ");		// yes - must wait
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,7);
sl@0: 	STREXD(		12,2,7);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)(NThreadWaitState::EWtStDead|NThreadWaitState::EWtStWaitActive)));
sl@0: 	asm("ldreq	r4, [r9, #%a0]" : : "i" _FOFF(NThreadBase,iUserModeCallbacks));	// check for callbacks
sl@0: 	asm("beq	exec_wfar_finish ");
sl@0: 	asm("b		0b ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals a fast semaphore.
sl@0: 
sl@0:     Increments the signal count of a fast semaphore by
sl@0: 	one and releases any waiting thread if the semphore becomes signalled.
sl@0: 	
sl@0: 	Note that a reschedule will not occur before this function returns, this will
sl@0: 	only take place when the kernel is unlocked. Generally threads
sl@0: 	would use NKern::FSSignal() which manipulates the kernel lock for you.
sl@0: 	
sl@0: 	@pre Kernel must be locked.
sl@0: 	@pre Call either in a thread or an IDFC context.
sl@0: 	
sl@0: 	@post Kernel is locked.
sl@0: 	
sl@0: 	@see NFastSemaphore::Wait()
sl@0: 	@see NKern::FSSignal()
sl@0: 	@see NKern::Unlock()
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NFastSemaphore::Signal()
sl@0: 	{
sl@0: 	ASM_DEBUG1(FSSignal,r0);
sl@0: 
sl@0: 	asm("mov	r1, #1 ");
sl@0: 	asm("fssignal1: ");
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,0);				// count
sl@0: 	asm("cmp	r2, #0 ");
sl@0: 	asm("sublt	r3, r1, #1 ");		// if count<0, replace with aCount-1
sl@0: 	asm("addges	r3, r2, r1 ");		// if count>=0, add aCount
sl@0: 	asm("bvs	0f ");				// if overflow, leave alone
sl@0: 	STREX(		12,3,0);
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("cmp	r2, #0 ");
sl@0: 	asm("movlt	r1, r2, lsl #2 ");	// if original count<0 r1 = original count<<2 = thread
sl@0: 	asm("blt	fs_signal_wake ");
sl@0: 	asm("0:		");
sl@0: 	__JUMP(,	lr);				// else finished
sl@0: 
sl@0: 	asm("fs_signal_wake: ");
sl@0: 	asm("stmfd	sp!, {r4-r6,lr} ");
sl@0: 	asm("mov	r4, r0 ");
sl@0: 	asm("mov	r5, r1 ");
sl@0: 	asm("mov	r0, r1 ");
sl@0: 	asm("bl		AcqSLock__12NSchedulable ");
sl@0: 	asm("add	r0, r5, #%a0" : : "i" _FOFF(NThreadBase, iWaitState));
sl@0: 	asm("mov	r1, #%a0" : : "i" ((TInt)NThreadBase::EWaitFastSemaphore));
sl@0: 	asm("mov	r2, r4 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("bl		UnBlockT__16NThreadWaitStateUiPvi ");
sl@0: 	asm("mov	r0, r5 ");
sl@0: 	asm("ldmfd	sp!, {r4-r6,lr} ");
sl@0: 	asm("b		RelSLock__12NSchedulable ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals a fast semaphore multiple times.
sl@0: 
sl@0: 	@pre Kernel must be locked.
sl@0: 	@pre Call either in a thread or an IDFC context.
sl@0: 	
sl@0: 	@post Kernel is locked.
sl@0: 
sl@0: 	@internalComponent	
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NFastSemaphore::SignalN(TInt /*aCount*/)
sl@0: 	{
sl@0: 	ASM_DEBUG2(FSSignalN,r0,r1);
sl@0: 
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("bgt	fssignal1 ");
sl@0: 	__JUMP(,	lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals the request semaphore of a nanothread several times.
sl@0: 
sl@0: 	This function is intended to be used by the EPOC layer and personality
sl@0: 	layers.  Device drivers should use Kern::RequestComplete instead.
sl@0: 
sl@0: 	@param aThread Nanothread to signal.  If NULL, the current thread is signaled.
sl@0: 	@param aCount Number of times the request semaphore must be signaled.
sl@0: 	
sl@0: 	@pre aCount >= 0
sl@0: 
sl@0: 	@see Kern::RequestComplete()
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NKern::ThreadRequestSignal(NThread* /*aThread*/, TInt /*aCount*/)
sl@0: 	{
sl@0: 	ASM_DEBUG2(NKThreadRequestSignalN,r0,r1);
sl@0: 
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("ble	0f ");
sl@0: 	asm("cmp	r0, #0 ");
sl@0: 	asm("addne	r0, r0, #%a0" : : "i" _FOFF(NThreadBase,iRequestSemaphore));
sl@0: 	asm("bne	nkfssignal1 ");
sl@0: 	__ASM_CLI();
sl@0: 	GET_RWNO_TID(,r0);
sl@0: 	asm("ldr	r0, [r0, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("add	r0, r0, #%a0" : : "i" _FOFF(NThreadBase,iRequestSemaphore));
sl@0: 	asm("b		nkfssignal2 ");
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__JUMP(eq,	lr);
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals the request semaphore of a nanothread.
sl@0: 
sl@0: 	This function is intended to be used by the EPOC layer and personality
sl@0: 	layers.  Device drivers should use Kern::RequestComplete instead.
sl@0: 
sl@0: 	@param aThread Nanothread to signal. Must be non NULL.
sl@0: 
sl@0: 	@see Kern::RequestComplete()
sl@0: 
sl@0: 	@pre Interrupts must be enabled.
sl@0: 	@pre Do not call from an ISR
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NKern::ThreadRequestSignal(NThread* /*aThread*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKThreadRequestSignal,r0);
sl@0: 	asm("add	r0, r0, #%a0" : : "i" _FOFF(NThreadBase,iRequestSemaphore));
sl@0: 
sl@0: 	/* fall through to FSSignal() ... */
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals a fast semaphore.
sl@0: 
sl@0:     Increments the signal count of a fast semaphore
sl@0: 	by one and releases any	waiting thread if the semaphore becomes signalled.
sl@0: 	
sl@0: 	@param aSem The semaphore to signal.
sl@0: 
sl@0: 	@see NKern::FSWait()
sl@0: 
sl@0: 	@pre Interrupts must be enabled.
sl@0: 	@pre Do not call from an ISR
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NKern::FSSignal(NFastSemaphore* /*aSem*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKFSSignal,r0);
sl@0: 
sl@0: 	asm("mov	r1, #1 ");
sl@0: 	asm("nkfssignal1: ");
sl@0: 	__ASM_CLI();
sl@0: 	asm("nkfssignal2: ");
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,0);				// count
sl@0: 	asm("cmp	r2, #0 ");
sl@0: 	asm("sublt	r3, r1, #1 ");		// if count<0, replace with aCount-1
sl@0: 	asm("addges	r3, r2, r1 ");		// if count>=0, add aCount
sl@0: 	asm("bvs	0f ");				// if overflow, leave alone
sl@0: 	STREX(		12,3,0);
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("cmp	r2, #0 ");
sl@0: 	asm("blt	2f ");
sl@0: 	asm("0:		");
sl@0: 	__ASM_STI();
sl@0: 	__JUMP(,	lr);				// else finished
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	GET_RWNO_TID(,r3);
sl@0: 	asm("mov	r1, r2, lsl #2 ");	// if original count<0 r1 = original count<<2 = thread
sl@0: 	asm("ldr	r12, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));
sl@0: 	asm("stmfd	sp!, {r4,lr} ");
sl@0: 	asm("add	r12, r12, #1 ");			// lock the kernel
sl@0: 	asm("str	r12, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));
sl@0: 	__ASM_STI();
sl@0: 	asm("bl		fs_signal_wake ");			// wake up the thread
sl@0: 	asm("ldmfd	sp!, {r4,lr} ");
sl@0: 	asm("b		Unlock__5NKern ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Signals a fast semaphore multiple times.
sl@0: 
sl@0:     Increments the signal count of a
sl@0: 	fast semaphore by aCount and releases any waiting thread if the semphore
sl@0: 	becomes signalled.
sl@0: 	
sl@0: 	@param aSem The semaphore to signal.
sl@0: 	@param aCount The number of times to signal the semaphore.
sl@0: 
sl@0: 	@see NKern::FSWait()
sl@0: 
sl@0: 	@pre Interrupts must be enabled.
sl@0: 	@pre Do not call from an ISR
sl@0:  */
sl@0: EXPORT_C __NAKED__ void NKern::FSSignalN(NFastSemaphore* /*aSem*/, TInt /*aCount*/)
sl@0: 	{
sl@0: 	ASM_DEBUG2(NKFSSignalN,r0,r1);
sl@0: 
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("bgt	nkfssignal1 ");
sl@0: 	__JUMP(,	lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Cancels a wait on a fast semaphore.
sl@0: 
sl@0: 	@pre Kernel must be locked.
sl@0: 	@pre Call either in a thread or an IDFC context.
sl@0: 	
sl@0: 	@post Kernel is locked.
sl@0: 
sl@0: 	@internalComponent	
sl@0:  */
sl@0: __NAKED__ void NFastSemaphore::WaitCancel()
sl@0: 	{
sl@0: 	asm("mov	r1, #1 ");
sl@0: 	/* Fall through ... */
sl@0: 	}
sl@0: 
sl@0: /* Fall through ... */
sl@0: #endif
sl@0: /* Fall through ... */
sl@0: 
sl@0: /**	Increment a fast semaphore count
sl@0: 
sl@0: 	Do memory barrier
sl@0: 	If iCount >= 0, increment by aCount and return 0
sl@0: 	If iCount < 0, set count equal to aCount-1 and return (original count << 2)
sl@0: 
sl@0: 	Release semantics
sl@0: */
sl@0: __NAKED__ NThreadBase* NFastSemaphore::Inc(TInt /*aCount*/)
sl@0: 	{
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,0);					// count
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("sublt r3, r1, #1 ");	// if count<0, replace with aCount-1
sl@0: 	asm("addges r3, r2, r1 ");	// if count>=0, add aCount
sl@0: 	asm("bvs 0f ");				// if overflow leave alone
sl@0: 	STREX(12,3,0);
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	asm("0: ");
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("movlt r0, r2, lsl #2 ");	// if original count<0, return count<<2
sl@0: 	asm("movge r0, #0 ");			// else return 0
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /**	Decrement a fast semaphore count
sl@0: 
sl@0: 	If count > 0, decrement
sl@0: 	If count = 0, set equal to (thread>>2)|0x80000000
sl@0: 	Return original count
sl@0: 	Full barrier semantics
sl@0: */
sl@0: __NAKED__ TInt NFastSemaphore::Dec(NThreadBase*)
sl@0: 	{
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,0);					// count
sl@0: 	asm("subs r3, r2, #1 ");
sl@0: 	asm("movlt r3, #0x80000000 ");
sl@0: 	asm("orrlt r3, r3, r1, lsr #2 ");	// if --count<0, r3=(thread>>2)|0x80000000
sl@0: 	STREX(12,3,0);
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("mov r0, r2 ");			// return original count
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Reset a fast semaphore count
sl@0: 
sl@0: 	Do memory barrier
sl@0: 	If iCount >= 0, set iCount=0 and return 0
sl@0: 	If iCount < 0, set iCount=0 and return (original count << 2)
sl@0: 
sl@0: 	Release semantics
sl@0: */
sl@0: __NAKED__ NThreadBase* NFastSemaphore::DoReset()
sl@0: 	{
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r3);
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,0);					// count
sl@0: 	STREX(12,3,0);				// zero count
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	asm("cmp r2, #0 ");
sl@0: 	asm("movlt r0, r2, lsl #2 ");	// if original count<0, return count<<2
sl@0: 	asm("movge r0, #0 ");			// else return 0
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: #ifdef __NTHREAD_WAITSTATE_MACHINE_CODED__
sl@0: /******************************************************************************
sl@0:  * Thread wait state
sl@0:  ******************************************************************************/
sl@0: 
sl@0: __NAKED__ void NThreadWaitState::SetUpWait(TUint /*aType*/, TUint /*aFlags*/, TAny* /*aWaitObj*/)
sl@0: 	{
sl@0: 	asm("stmfd	sp!, {r4-r5} ");
sl@0: 	asm("and	r2, r2, #%a0" : : "i" ((TInt)EWtStObstructed));
sl@0: 	asm("and	r1, r1, #0xff ");
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)EWtStWaitPending));
sl@0: 	asm("orr	r2, r2, r1, lsl #8 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("bne	0f ");
sl@0: 	asm("ldmfd	sp!, {r4-r5} ");
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(NThreadWaitState, iTimer.iTriggerTime));
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: __NAKED__ void NThreadWaitState::SetUpWait(TUint /*aType*/, TUint /*aFlags*/, TAny* /*aWaitObj*/, TUint32 /*aTimeout*/)
sl@0: 	{
sl@0: 	asm("stmfd	sp!, {r4-r5} ");
sl@0: 	asm("and	r2, r2, #%a0" : : "i" ((TInt)EWtStObstructed));
sl@0: 	asm("and	r1, r1, #0xff ");
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)EWtStWaitPending));
sl@0: 	asm("orr	r2, r2, r1, lsl #8 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("ldr	r12, [sp, #8] ");
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("bne	0f ");
sl@0: 	asm("ldmfd	sp!, {r4-r5} ");
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(NThreadWaitState, iTimer.iTriggerTime));
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: __NAKED__ void NThreadWaitState::CancelWait()
sl@0: 	{
sl@0: 	asm("mov	r12, r0 ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		0,12);
sl@0: 	STREXD(		1,2,12);
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("tst	r0, #%a0" : : "i" ((TInt)(EWtStDead|EWtStWaitActive)));
sl@0: 	asm("bne	0f ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: __NAKED__ TInt NThreadWaitState::DoWait()
sl@0: 	{
sl@0: 	asm("ldr	r1, [r0, #%a0]" : : "i" _FOFF(NThreadWaitState,iTimer.iTriggerTime));
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		2,0);
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("orrne	r2, r2, #%a0" : : "i" ((TInt)EWtStTimeout));
sl@0: 	asm("tst	r2, #%a0" : : "i" ((TInt)EWtStDead));
sl@0: 	asm("bne	0f ");
sl@0: 	asm("tst	r2, #%a0" : : "i" ((TInt)EWtStWaitPending));
sl@0: 	asm("beq	9f ");
sl@0: 	asm("bic	r2, r2, #%a0" : : "i" ((TInt)EWtStWaitPending));
sl@0: 	asm("orr	r2, r2, #%a0" : : "i" ((TInt)EWtStWaitActive));
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("cmp	r1, #0 ");
sl@0: 	asm("bne	2f ");
sl@0: 	asm("mov	r0, r2, lsr #8 ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	asm("stmfd	sp!, {r2-r4,lr} ");
sl@0: 	asm("mov	r4, r0 ");
sl@0: 	asm("add	r0, r0, #%a0" : : "i" _FOFF(NThreadWaitState,iTimer));
sl@0: 	asm("mov	r2, #1 ");
sl@0: 	asm("bl	"	CSM_ZN6NTimer7OneShotEii );
sl@0: 	asm("ldr	r1, [r4, #%a0]" : : "i" _FOFF(NThreadWaitState,iTimer.iNTimerSpare1));
sl@0: 	asm("cmp	r0, #0 ");
sl@0: 	asm("bne	8f ");
sl@0: 	asm("add	r1, r1, #1 ");
sl@0: 	asm("str	r1, [r4, #%a0]" : : "i" _FOFF(NThreadWaitState,iTimer.iNTimerSpare1));
sl@0: 	asm("ldmfd	sp!, {r2-r4,lr} ");
sl@0: 	asm("mov	r0, r2, lsr #8 ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("0:		");
sl@0: 	asm("mvn	r0, #%a0" : : "i" (~KErrDied));
sl@0: 	__JUMP(,	lr);
sl@0: 	asm("9:		");
sl@0: 	asm("mvn	r0, #%a0" : : "i" (~KErrGeneral));
sl@0: 	__JUMP(,	lr);
sl@0: 	asm("8:		");
sl@0: 	__ASM_CRASH();
sl@0: 	}
sl@0: 
sl@0: __NAKED__ TInt NThreadWaitState::UnBlockT(TUint /*aType*/, TAny* /*aWaitObj*/, TInt /*aReturnValue*/)
sl@0: 	{
sl@0: 	asm("stmfd	sp!, {r4-r6,lr} ");
sl@0: 	asm("mov	r6, r2 ");					// r6 = aWaitObj
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	__DATA_MEMORY_BARRIER__(r2);
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);						// r5:r4 = oldws64
sl@0: 	asm("cmp	r5, r6 ");					// does iWaitObj match?
sl@0: 	asm("bne	2f ");						// no
sl@0: 	asm("eor	r12, r4, r1, lsl #8 ");		// does wait type match?
sl@0: 	asm("cmp	r12, #%a0" : : "i" ((TInt)EWtStDead));
sl@0: 	asm("bhs	2f ");						// no
sl@0: 	STREXD(		12,2,0);					// yes - wait matches - try to write return value
sl@0: 	asm("cmp	r12, #0 ");					// success?
sl@0: 	asm("bne	1b ");						// no - retry
sl@0: 	asm("mov	r6, r0 ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)EWtStTimeout));
sl@0: 	asm("blne	CancelTimerT__16NThreadWaitState ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)EWtStWaitActive));
sl@0: 	asm("beq	0f ");
sl@0: 	asm("ldr	r1, [r6, #%a0]" : : "i" (_FOFF(NThreadBase,iPauseCount)-_FOFF(NThreadBase,iWaitState)));
sl@0: 	asm("sub	r0, r6, #%a0" : : "i" _FOFF(NThreadBase,iWaitState));	// r0 = Thread()
sl@0: 	asm("movs	r1, r1, lsl #16 ");				// check if iPauseCount=iSuspendCount=0
sl@0: 	asm("bleq	ReadyT__12NSchedulableUi ");	// if so, make thread ready
sl@0: 	asm("0:		");
sl@0: 	asm("mov	r0, #0 ");
sl@0: 	__POPRET("	r4-r6,");					// return KErrNone
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	STREXD(		12,4,0);					// no matching wait - write back to check atomicity
sl@0: 	asm("cmp	r12, #0 ");					// success?
sl@0: 	asm("bne	1b ");						// no - retry
sl@0: 	asm("mvn	r0, #%a0" : : "i" (~KErrGeneral));
sl@0: 	__POPRET("	r4-r6,");					// no matching wait - return KErrGeneral
sl@0: 	}
sl@0: 
sl@0: __NAKED__ TUint32 NThreadWaitState::ReleaseT(TAny*& /*aWaitObj*/, TInt /*aReturnValue*/)
sl@0: 	{
sl@0: 	asm("stmfd	sp!, {r4-r5} ");
sl@0: 	asm("mov	r3, r2 ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	__DATA_MEMORY_BARRIER__(r2);
sl@0: 	asm("1:		");
sl@0: 	LDREXD(		4,0);
sl@0: 	asm("and	r2, r4, #%a0" : : "i" ((TInt)EWtStDead));
sl@0: 	STREXD(		12,2,0);
sl@0: 	asm("cmp	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("str	r5, [r1] ");
sl@0: 	asm("tst	r4, #%a0" : : "i" ((TInt)EWtStTimeout));
sl@0: 	asm("bne	2f ");
sl@0: 	asm("mov	r0, r4 ");
sl@0: 	asm("ldmfd	sp!, {r4-r5} ");
sl@0: 	__JUMP(,	lr);
sl@0: 
sl@0: 	asm("2:		");
sl@0: 	asm("mov	r5, lr ");
sl@0: 	asm("bl		CancelTimerT__16NThreadWaitState ");
sl@0: 	asm("mov	r0, r4 ");
sl@0: 	asm("mov	lr, r5 ");
sl@0: 	asm("ldmfd	sp!, {r4-r5} ");
sl@0: 	__JUMP(,	lr);
sl@0: 	}
sl@0: #endif
sl@0: 
sl@0: 
sl@0: #ifdef __FAST_MUTEX_MACHINE_CODED__
sl@0: /******************************************************************************
sl@0:  * Fast mutex
sl@0:  ******************************************************************************/
sl@0: 
sl@0: /** Releases a previously acquired fast mutex.
sl@0: 	
sl@0: 	Generally, threads would use NKern::FMSignal() which manipulates the kernel lock
sl@0: 	for you.
sl@0: 	
sl@0: 	@pre The calling thread holds the mutex.
sl@0: 	@pre Kernel must be locked.
sl@0: 	
sl@0: 	@post Kernel is locked.
sl@0: 	
sl@0: 	@see NFastMutex::Wait()
sl@0: 	@see NKern::FMSignal()
sl@0: */
sl@0: EXPORT_C __NAKED__ void NFastMutex::Signal()
sl@0: 	{
sl@0: 	ASM_DEBUG1(FMSignal,r0);
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: //	BTraceContext4(BTrace::EFastMutex, BTrace::EFastMutexSignal, this);
sl@0: 	asm("stmfd	sp!, {r0,lr} ");
sl@0: 	asm("mov	r1, r0 ");
sl@0: 	asm("ldr	r0, btrace_hdr_fmsignal ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("bl		OutX__6BTraceUlUlUlUl ");
sl@0: 	asm("ldmfd	sp!, {r0,lr} ");
sl@0: #endif
sl@0: 	GET_RWNO_TID(,r3);
sl@0: 	asm("mov	r12, #0 ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("ldr	r1, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	__ASM_CLI();
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,0);				// r2=aMutex->iHoldingThread
sl@0: 	asm("cmp	r2, r1 ");			// anyone else waiting?
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("bne	2f ");				// branch out if someone else waiting
sl@0: 	STREX(		12,2,0);			// else try to clear the holding thread
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r12, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	__ASM_STI();
sl@0: 	__JUMP(,lr);					// mutex released without contention
sl@0: 
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: 	asm("btrace_hdr_fmsignal: ");
sl@0: 	asm(".word %a0" : : "i" (BTRACE_HEADER_C(8,BTrace::EFastMutex,BTrace::EFastMutexSignal)));
sl@0: #endif
sl@0: 
sl@0: 	// there is contention
sl@0: 	asm("2:		");
sl@0: 	asm("orr	r12, r0, #1 ");
sl@0: 	asm("str	r12, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	__ASM_STI();
sl@0: 	asm("b		DoSignalL__10NFastMutex ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Acquires the System Lock.
sl@0: 
sl@0:     This will block until the mutex is available, and causes
sl@0: 	the thread to enter an implicit critical section until the mutex is released.
sl@0: 
sl@0: 	@post System lock is held.
sl@0: 
sl@0: 	@see NKern::UnlockSystem()
sl@0: 	@see NKern::FMWait()
sl@0: 
sl@0: 	@pre No fast mutex can be held.
sl@0: 	@pre Call in a thread context.
sl@0: 	@pre Kernel must be unlocked
sl@0: 	@pre interrupts enabled
sl@0: 
sl@0: */
sl@0: EXPORT_C __NAKED__ void NKern::LockSystem()
sl@0: 	{
sl@0: 	asm("ldr	r0, __SystemLock ");
sl@0: 
sl@0: 	/* fall through to FMWait() ... */
sl@0: 	}
sl@0: 
sl@0: /** Acquires a fast mutex.
sl@0: 
sl@0:     This will block until the mutex is available, and causes
sl@0: 	the thread to enter an implicit critical section until the mutex is released.
sl@0: 
sl@0: 	@param aMutex The fast mutex to acquire.
sl@0: 	
sl@0: 	@post The calling thread holds the mutex.
sl@0: 	
sl@0: 	@see NFastMutex::Wait()
sl@0: 	@see NKern::FMSignal()
sl@0: 
sl@0: 	@pre No fast mutex can be held.
sl@0: 	@pre Call in a thread context.
sl@0: 	@pre Kernel must be unlocked
sl@0: 	@pre interrupts enabled
sl@0: 
sl@0: */
sl@0: EXPORT_C __NAKED__ void NKern::FMWait(NFastMutex* /*aMutex*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKFMWait,r0);
sl@0: 
sl@0: 	__ASM_CLI();
sl@0: 	GET_RWNO_TID(,r3);
sl@0: 	asm("ldr	r1, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("1:		");
sl@0: 	LDREX(		2,0);				// r2=aMutex->iHoldingThread
sl@0: 	asm("cmp	r2, #0 ");			//
sl@0: 	asm("bne	2f ");				// branch out if mutex held
sl@0: 	STREX(		12,1,0);			// else try to set us as holding thread
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r0, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	__ASM_STI();
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: //	BTraceContext4(BTrace::EFastMutex, BTrace::EFastMutexWait, aMutex);
sl@0: 	asm("mov	r1, r0 ");
sl@0: 	asm("ldr	r0, btrace_hdr_fmwait ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("b		OutX__6BTraceUlUlUlUl ");
sl@0: #endif
sl@0: 	__JUMP(,lr);					// mutex acquired without contention
sl@0: 
sl@0: 	// there is contention
sl@0: 	asm("2:		");
sl@0: 	asm("mov	r2, #1 ");
sl@0: 	asm("str	r0, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	asm("str	r2, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));
sl@0: 	__ASM_STI();
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("stmfd	sp!, {r4,lr} ");
sl@0: 	asm("bl		DoWaitL__10NFastMutex ");
sl@0: 	asm("ldmfd	sp!, {r4,lr} ");
sl@0: 	asm("b		Unlock__5NKern ");
sl@0: 
sl@0: 	asm("__SystemLock: ");
sl@0: 	asm(".word	%a0" : : "i" ((TInt)&TheScheduler.iLock));
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: 	asm("btrace_hdr_fmwait: ");
sl@0: 	asm(".word %a0" : : "i" (BTRACE_HEADER_C(8,BTrace::EFastMutex,BTrace::EFastMutexWait)));
sl@0: #endif
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Releases the System Lock.
sl@0: 
sl@0: 	@pre System lock must be held.
sl@0: 
sl@0: 	@see NKern::LockSystem()
sl@0: 	@see NKern::FMSignal()
sl@0: */
sl@0: EXPORT_C __NAKED__ void NKern::UnlockSystem()
sl@0: 	{
sl@0: 	asm("ldr	r0, __SystemLock ");
sl@0: 
sl@0: 	/* fall through to FMSignal() ... */
sl@0: 	}
sl@0: 
sl@0: /** Releases a previously acquired fast mutex.
sl@0: 	
sl@0: 	@param aMutex The fast mutex to release.
sl@0: 	
sl@0: 	@pre The calling thread holds the mutex.
sl@0: 	
sl@0: 	@see NFastMutex::Signal()
sl@0: 	@see NKern::FMWait()
sl@0: */
sl@0: EXPORT_C __NAKED__ void NKern::FMSignal(NFastMutex* /*aMutex*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKFMSignal,r0);
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: //	BTraceContext4(BTrace::EFastMutex, BTrace::EFastMutexSignal, this);
sl@0: 	asm("stmfd	sp!, {r0,lr} ");
sl@0: 	asm("mov	r1, r0 ");
sl@0: 	asm("ldr	r0, btrace_hdr_fmsignal ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("bl		OutX__6BTraceUlUlUlUl ");
sl@0: 	asm("ldmfd	sp!, {r0,lr} ");
sl@0: #endif
sl@0: 	__ASM_CLI();
sl@0: 	GET_RWNO_TID(,r3);
sl@0: 	asm("mov	r12, #0 ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	asm("ldr	r1, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("1:		");
sl@0: 	LDREX(		12,0);				// r12=aMutex->iHoldingThread
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("cmp	r12, r1 ");			// anyone else waiting?
sl@0: 	asm("bne	2f ");				// branch out if someone else waiting
sl@0: 	STREX(		12,2,0);			// else try to clear the holding thread
sl@0: 	asm("teq	r12, #0 ");
sl@0: 	asm("bne	1b ");
sl@0: 	asm("str	r12, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	__ASM_STI();
sl@0: 	__JUMP(,lr);					// mutex released without contention
sl@0: 
sl@0: 	// there is contention
sl@0: 	asm("2:		");
sl@0: 	asm("stmfd	sp!, {r4,lr} ");
sl@0: 	asm("mov	r12, #1 ");
sl@0: 	asm("orr	r4, r0, #1 ");
sl@0: 	asm("str	r12, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));
sl@0: 	asm("str	r4, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	__ASM_STI();
sl@0: 	asm("bl		DoSignalL__10NFastMutex ");
sl@0: 	asm("ldmfd	sp!, {r4,lr} ");
sl@0: 	asm("b		Unlock__5NKern ");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Temporarily releases the System Lock if there is contention.
sl@0: 
sl@0:     If there
sl@0: 	is another thread attempting to acquire the System lock, the calling
sl@0: 	thread releases the mutex and then acquires it again.
sl@0: 	
sl@0: 	This is more efficient than the equivalent code:
sl@0: 	
sl@0: 	@code
sl@0: 	NKern::UnlockSystem();
sl@0: 	NKern::LockSystem();
sl@0: 	@endcode
sl@0: 
sl@0: 	Note that this can only allow higher priority threads to use the System
sl@0: 	lock as lower priority cannot cause contention on a fast mutex.
sl@0: 
sl@0: 	@return	TRUE if the system lock was relinquished, FALSE if not.
sl@0: 
sl@0: 	@pre	System lock must be held.
sl@0: 
sl@0: 	@post	System lock is held.
sl@0: 
sl@0: 	@see NKern::LockSystem()
sl@0: 	@see NKern::UnlockSystem()
sl@0: */
sl@0: EXPORT_C __NAKED__ TBool NKern::FlashSystem()
sl@0: 	{
sl@0: //	CHECK_PRECONDITIONS(MASK_SYSTEM_LOCKED,"NKern::FlashSystem");
sl@0: 	asm("ldr	r0, __SystemLock ");
sl@0: 
sl@0: 	/* fall through to FMFlash() ... */
sl@0: 	}
sl@0: 
sl@0: /** Temporarily releases a fast mutex if there is contention.
sl@0: 
sl@0:     If there is another thread attempting to acquire the mutex, the calling
sl@0: 	thread releases the mutex and then acquires it again.
sl@0: 	
sl@0: 	This is more efficient than the equivalent code:
sl@0: 	
sl@0: 	@code
sl@0: 	NKern::FMSignal();
sl@0: 	NKern::FMWait();
sl@0: 	@endcode
sl@0: 
sl@0: 	@return	TRUE if the mutex was relinquished, FALSE if not.
sl@0: 
sl@0: 	@pre	The mutex must be held.
sl@0: 
sl@0: 	@post	The mutex is held.
sl@0: */
sl@0: EXPORT_C __NAKED__ TBool NKern::FMFlash(NFastMutex* /*aM*/)
sl@0: 	{
sl@0: 	ASM_DEBUG1(NKFMFlash,r0);
sl@0: 	__ASM_CLI();
sl@0: 	GET_RWNO_TID(,r3);
sl@0: 	asm("ldr	r1, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
sl@0: 	asm("ldrb	r2, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iMutexPri));
sl@0: 	asm("ldrb	r12, [r1, #%a0]" : : "i" _FOFF(NThreadBase,iBasePri));
sl@0: 	asm("cmp	r2, r12 ");
sl@0: 	asm("bhs	1f ");							// a thread of greater or equal priority is waiting
sl@0: 	__ASM_STI();
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: //	BTraceContext4(BTrace::EFastMutex, BTrace::EFastMutexFlash, aM);
sl@0: 	asm("mov	r1, r0 ");
sl@0: 	asm("ldr	r0, btrace_hdr_fmsignal ");
sl@0: 	asm("stmfd	sp!, {r4,lr} ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("bl		OutX__6BTraceUlUlUlUl ");
sl@0: 	asm("ldmfd	sp!, {r4,lr} ");
sl@0: #endif
sl@0: 	asm("mov	r0, #0 ");
sl@0: 	__JUMP(,lr);								// return FALSE
sl@0: 
sl@0: #ifdef BTRACE_FAST_MUTEX
sl@0: 	asm("btrace_hdr_fmflash: ");
sl@0: 	asm(".word %a0" : : "i" (BTRACE_HEADER_C(8,BTrace::EFastMutex,BTrace::EFastMutexFlash)));
sl@0: #endif
sl@0: 
sl@0: 	asm("1:		");
sl@0: 	asm("mov	r12, #1 ");
sl@0: 	asm("str	r12, [r3, #%a0]" : : "i" _FOFF(TSubScheduler,iKernLockCount));
sl@0: 	__ASM_STI();
sl@0: 	asm("stmfd	sp!, {r4,lr} ");
sl@0: 	asm("mov	r4, r0 ");
sl@0: 	asm("bl		Signal__10NFastMutex ");
sl@0: 	asm("bl		PreemptionPoint__5NKern ");
sl@0: 	asm("mov	r0, r4 ");
sl@0: 	asm("bl		Wait__10NFastMutex ");
sl@0: 	asm("bl		Unlock__5NKern ");
sl@0: 	asm("ldmfd	sp!, {r4,lr} ");
sl@0: 	asm("mov	r0, #1 ");
sl@0: 	__JUMP(,lr);								// return TRUE
sl@0: 	}
sl@0: #endif
sl@0: 
sl@0: 
sl@0: 
sl@0: /** Check whether a thread holds a fast mutex.
sl@0: 	If so set the mutex contention flag and return TRUE, else return FALSE.
sl@0: 
sl@0: 	Called with kernel lock held
sl@0: 
sl@0: 	@internalComponent
sl@0:  */
sl@0: __NAKED__ TBool NThreadBase::CheckFastMutexDefer()
sl@0: 	{
sl@0: 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	asm("bics r2, r1, #3 ");		// r2 = pointer to mutex if any, r1 bit 0 = flag
sl@0: 	asm("bne 1f ");
sl@0: 	asm("mov r0, #0 ");				// no mutex - return FALSE
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	// iHeldFastMutex points to a mutex
sl@0: 	asm("1: ");
sl@0: 	asm("tst r1, #1 ");				// test flag
sl@0: 	asm("beq 2f ");					// branch if not being released
sl@0: 
sl@0: 	// mutex being released
sl@0: 	asm("3: ");
sl@0: 	LDREX(3,2);						// r3 = m->iHoldingThread
sl@0: 	asm("sub r3, r3, r0 ");			// m->iHoldingThread - this
sl@0: 	asm("cmp r3, #1 ");
sl@0: 	asm("bhi 4f ");					// if m->iHoldingThread != this or this+1, skip
sl@0: 	asm("orr r3, r0, #1 ");			// if m->iHoldingThread = this or this+1, set m->iHoldingThread = this+1
sl@0: 	STREX(12,3,2);
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 3b ");
sl@0: 	asm("mov r0, #1 ");				// return TRUE
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("4: ");
sl@0: 	asm("mov r3, #0 ");				// already released, so set iHeldFastMutex=0
sl@0: 	asm("str r3, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	asm("0: ");
sl@0: 	asm("mov r0, #0 ");				// no mutex - return FALSE
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	// mutex being acquired or has been acquired
sl@0: 	// if it has been acquired set the contention flag and return TRUE, else return FALSE
sl@0: 	asm("2: ");
sl@0: 	LDREX(3,2);						// r3 = m->iHoldingThread
sl@0: 	asm("sub r3, r3, r0 ");			// m->iHoldingThread - this
sl@0: 	asm("cmp r3, #1 ");
sl@0: 	asm("bhi 0b ");					// if m->iHoldingThread != this or this+1, finish and return FALSE
sl@0: 	asm("orr r3, r0, #1 ");			// if m->iHoldingThread = this or this+1, set m->iHoldingThread = this+1
sl@0: 	STREX(12,3,2);
sl@0: 	asm("teq r12, #0 ");
sl@0: 	asm("bne 2b ");
sl@0: 	asm("mov r0, #1 ");				// return TRUE
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("4: ");
sl@0: 	asm("mov r3, #0 ");				// already released, so set iHeldFastMutex=0
sl@0: 	asm("str r3, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iHeldFastMutex));
sl@0: 	asm("mov r0, #0 ");				// no mutex - return FALSE
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /******************************************************************************
sl@0:  * IDFC/DFC
sl@0:  ******************************************************************************/
sl@0: 
sl@0: /**	Transition the state of an IDFC or DFC when Add() is called
sl@0: 
sl@0: 	0000->008n, 00Cn->00En, all other states unchanged
sl@0: 	Return original state.
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::AddStateChange()
sl@0: 	{
sl@0: 	GET_RWNO_TID(, r1);				// r1->SubScheduler
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	asm("ldr r1, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r1 = current CPU number
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("cmp r0, #0 ");				// original state 0000 ?
sl@0: 	asm("orreq r2, r1, #0x0080 ");	// yes -> 008n
sl@0: 	asm("movne r2, r0 ");			// no -> R2=original state ...
sl@0: 	asm("eorne r12, r0, #0x00C0 ");	// ... and R12=original state^00C0 ...
sl@0: 	asm("cmpne r12, #0x0020 ");		// ... and check if result < 0020 (i.e. original==00C0..00DF)
sl@0: 	asm("addlo r2, r2, #0x0020 ");	// 00Cn->00En otherwise leave R2 alone
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC just before running it.
sl@0: 
sl@0: 	002g->00Cn, 008n->00Cn, 00An->00Cn, XXYY->XX00, XX00->0000
sl@0: 	other initial states invalid
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::RunIDFCStateChange()
sl@0: 	{
sl@0: 	GET_RWNO_TID(, r1);				// r1->SubScheduler
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	asm("ldr r1, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r1 = current CPU number
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("str r4, [sp, #-4]! ");
sl@0: 	asm("ldr r4, __IdleGeneration ");
sl@0: 	asm("ldrb r4, [r4] ");			// r4 = TheScheduler.iIdleGeneration
sl@0: 	asm("eor r4, r4, #0x0021 ");	// r4 = expected state of idle IDFCs
sl@0: #endif
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("eor r2, r0, #0x0080 ");
sl@0: 	asm("cmp r2, #0x0040 ");
sl@0: 	asm("bhs 2f ");					// branch out unless 008n or 00An
sl@0: #ifdef _DEBUG
sl@0: 	asm("and r2, r0, #0x001F ");
sl@0: 	asm("cmp r2, r1 ");
sl@0: 	asm("bne 0f ");					// if n!=current CPU number, die
sl@0: #endif
sl@0: 	asm("orr r2, r1, #0x00C0 ");	// 008n->00Cn, 00An->00Cn
sl@0: 	asm("3: ");
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("ldr r4, [sp], #4 ");
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("2: ");
sl@0: 	asm("bic r2, r0, #1 ");
sl@0: 	asm("cmp r2, #0x0020 ");
sl@0: 	asm("orreq r2, r1, #0x00C0 ");	// 002g->00Cn
sl@0: #ifdef _DEBUG
sl@0: 	asm("bne 4f ");
sl@0: 	asm("cmp r0, r4 ");
sl@0: 	asm("bne 0f ");					// wrong idle state
sl@0: 	asm("4: ");
sl@0: #endif
sl@0: 	asm("beq 3b ");
sl@0: 	asm("cmp r0, #0x0100 ");		// C=1 if XXYY or XX00, C=0 if bad state
sl@0: 	asm("bic r2, r0, #0x00FF ");	// XXYY->XX00, C unchanged
sl@0: 	asm("tst r0, #0x00FF ");		// C unchanged
sl@0: 	asm("moveq r2, #0 ");			// XX00->0000, C unchanged
sl@0: 	asm("bcs 3b ");					// branch to STREX if valid state
sl@0: 
sl@0: 	asm("0: ");
sl@0: 	__ASM_CRASH();					// bad state
sl@0: 
sl@0: 	asm("__IdleGeneration: ");
sl@0: 	asm(".word %a0 " : : "i" ((TInt)&TheScheduler.iIdleGeneration));
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC just after running it.
sl@0: 
sl@0: 	First swap aS->iCurrentIDFC with 0
sl@0: 	If original value != this, return 0xFFFFFFFF and don't touch *this
sl@0: 	Else 00Cn->0000, 00En->008n, 006n->006n, XXCn->XX00, XXEn->XX00, XX6n->XX00, XX00->0000
sl@0: 	other initial states invalid
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::EndIDFCStateChange(TSubScheduler* /*aS*/)
sl@0: 	{
sl@0: 	asm("add r1, r1, #%a0" : : "i" _FOFF(TSubScheduler,iCurrentIDFC));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1: ");
sl@0: 	LDREX(2,1);
sl@0: 	asm("subs r2, r2, r0 ");		// aS->iCurrentIDFC == this?
sl@0: 	asm("bne 9f ");					// no - bail out immediately
sl@0: 	STREX(12,2,1);					// yes - set aS->iCurrentIDFC=0
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("str r4, [sp, #-4]! ");
sl@0: 	GET_RWNO_TID(, r4);				// r4->SubScheduler
sl@0: 	asm("ldr r4, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r4 = current CPU number
sl@0: #endif
sl@0: 	asm("2: ");
sl@0: 	LDREXH(0,3);					// r0 = original DFC state
sl@0: 	asm("mov r2, #0 ");				// r2 = 0 to begin with
sl@0: #ifdef _DEBUG
sl@0: 	asm("tst r0, #0x00FF ");
sl@0: 	asm("beq 5f ");
sl@0: 	asm("eor r12, r0, r4 ");		// original state ^ CPU number, should be xxC0, xxE0 or xx60
sl@0: 	asm("and r12, r12, #0x00E0 ");
sl@0: 	asm("cmp r12, #0x00E0 ");
sl@0: 	asm("cmpne r12, #0x00C0 ");
sl@0: 	asm("cmpne r12, #0x0060 ");
sl@0: 	asm("beq 5f ");
sl@0: 	__ASM_CRASH();					// bad state
sl@0: 	asm("5: ");
sl@0: #endif
sl@0: 	asm("bic r12, r0, #0x001F ");
sl@0: 	asm("cmp r12, #0x00E0 ");
sl@0: 	asm("bhi 4f ");					// branch out if XXYY or XX00
sl@0: 	asm("subeq r2, r0, #0x0060 ");	// 00En->008n
sl@0: 	asm("cmp r12, #0x0060 ");
sl@0: 	asm("moveq r2, r0 ");			// 006n->006n, else R2=0
sl@0: 	asm("3: ");
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 2b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("ldr r4, [sp], #4 ");
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 
sl@0: 	asm("4: ");
sl@0: 	asm("tst r0, #0x00FF ");
sl@0: 	asm("bicne r2, r0, #0x00FF ");	// XXYY->XX00, XX00->0000
sl@0: 	asm("b 3b ");
sl@0: 
sl@0: 	asm("9: ");
sl@0: 	asm("mvn r0, #0 ");				// return 0xFFFFFFFF
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC just after running it.
sl@0: 
sl@0: 	006n->002g where g = TheScheduler.iIdleGeneration
sl@0: 	XX6n->XX00
sl@0: 	other initial states invalid
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::EndIDFCStateChange2()
sl@0: 	{
sl@0: 	asm("ldr r12, __IdleGeneration ");
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: #ifdef _DEBUG
sl@0: 	asm("str r4, [sp, #-4]! ");
sl@0: 	GET_RWNO_TID(, r4);				// r4->SubScheduler
sl@0: 	asm("ldr r4, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r4 = current CPU number
sl@0: #endif
sl@0: 	asm("ldrb r1, [r12] ");			// r1 = TheScheduler.iIdleGeneration
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: #ifdef _DEBUG
sl@0: 	asm("eor r12, r0, r4 ");
sl@0: 	asm("and r12, r12, #0x00FF ");
sl@0: 	asm("cmp r12, #0x0060 ");		// should be 006n or XX6n
sl@0: 	asm("beq 2f ");
sl@0: 	__ASM_CRASH();					// if not, die
sl@0: 	asm("2: ");
sl@0: #endif
sl@0: 	asm("tst r0, #0xFF00 ");		// XX6n or 006n ?
sl@0: 	asm("orreq r2, r1, #0x0020 ");	// 006n->002g
sl@0: 	asm("bicne r2, r0, #0x00FF ");	// XX6n->XX00
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("ldr r4, [sp], #4 ");
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of a DFC just before moving it from the IDFC queue to
sl@0: 	its final queue.
sl@0: 
sl@0: 	002g->0001, 008n->0001, XX2g->XX00, XX8n->XX00, XX00->0000
sl@0: 	other initial states invalid
sl@0: 	Return original state
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::MoveToFinalQStateChange()
sl@0: 	{
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("str r4, [sp, #-4]! ");
sl@0: 	asm("ldr r4, __IdleGeneration ");
sl@0: 	GET_RWNO_TID(, r1);				// r1->SubScheduler
sl@0: 	asm("ldrb r4, [r4] ");			// r4 = TheScheduler.iIdleGeneration
sl@0: 	asm("ldr r1, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r1 = current CPU number
sl@0: 	asm("eor r4, r4, #0x0021 ");	// r4 = expected state of idle IDFCs
sl@0: 	asm("orr r1, r1, #0x0080 ");
sl@0: #endif
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: #ifdef _DEBUG
sl@0: 	asm("cmp r0, #0 ");
sl@0: 	asm("beq 0f ");					// 0000 -> die
sl@0: 	asm("ands r2, r0, #0x00FF ");
sl@0: 	asm("beq 3f ");					// XX00 -> OK
sl@0: 	asm("cmp r2, r4 ");				// 002g ?
sl@0: 	asm("beq 3f ");					// yes -> OK
sl@0: 	asm("cmp r2, r1 ");				// 008n ?
sl@0: 	asm("beq 3f ");					// yes -> OK
sl@0: 	asm("0: ");
sl@0: 	__ASM_CRASH();					// otherwise die
sl@0: 	asm("3: ");
sl@0: #endif
sl@0: 	asm("bics r2, r0, #0x00FF ");	// XXYY->XX00
sl@0: 	asm("moveq r2, #0x0001 ");		// 002g,008n->0001
sl@0: 	asm("beq 2f ");
sl@0: 	asm("tst r0, #0x00FF ");
sl@0: 	asm("moveq r2, #0 ");			// XX00->0000
sl@0: 	asm("2: ");
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("ldr r4, [sp], #4 ");
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC when transferring it to another CPU
sl@0: 
sl@0: 	002g->00Am, 008n->00Am, XXYY->XX00, XX00->0000
sl@0: 	other initial states invalid
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled and target CPU's ExIDfcLock held.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::TransferIDFCStateChange(TInt /*aCpu*/)
sl@0: 	{
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("stmfd sp!, {r4-r5} ");
sl@0: 	asm("ldr r4, __IdleGeneration ");
sl@0: 	GET_RWNO_TID(, r5);				// r5->SubScheduler
sl@0: 	asm("ldrb r4, [r4] ");			// r4 = TheScheduler.iIdleGeneration
sl@0: 	asm("ldr r5, [r5, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));	// r5 = current CPU number
sl@0: 	asm("eor r4, r4, #0x0021 ");	// r4 = expected state of idle IDFCs
sl@0: 	asm("orr r5, r5, #0x0080 ");
sl@0: #endif
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: #ifdef _DEBUG
sl@0: 	asm("cmp r0, #0 ");
sl@0: 	asm("beq 0f ");					// 0000 -> die
sl@0: 	asm("ands r2, r0, #0x00FF ");
sl@0: 	asm("beq 3f ");					// XX00 -> OK
sl@0: 	asm("cmp r2, r4 ");				// 002g ?
sl@0: 	asm("beq 3f ");					// yes -> OK
sl@0: 	asm("cmp r2, r5 ");				// 008n ?
sl@0: 	asm("beq 3f ");					// yes -> OK
sl@0: 	asm("0: ");
sl@0: 	__ASM_CRASH();					// otherwise die
sl@0: 	asm("3: ");
sl@0: #endif
sl@0: 	asm("bics r2, r0, #0x00FF ");	// XXYY->XX00
sl@0: 	asm("orreq r2, r1, #0x00A0 ");	// 002g,008n->00Am
sl@0: 	asm("beq 2f ");
sl@0: 	asm("tst r0, #0x00FF ");
sl@0: 	asm("moveq r2, #0 ");			// XX00->0000
sl@0: 	asm("2: ");
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: #ifdef _DEBUG
sl@0: 	asm("ldmfd sp!, {r4-r5} ");
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC/DFC just before cancelling it.
sl@0: 
sl@0: 	0000->0000, XX00->ZZ00, xxYY->zzYY
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::CancelInitialStateChange()
sl@0: 	{
sl@0: 	GET_RWNO_TID(,r1);
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("ldr r1, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuMask));	// r1 = mask of current CPU number
sl@0: 
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("cmp r0, #0 ");
sl@0: 	asm("beq 2f ");				// if original state 0000 leave alone
sl@0: 	asm("orr r2, r0, r1, lsl #8 ");	// else set bit 8-15 corresponding to CPU number
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	asm("2: ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC/DFC at the end of a cancel operation
sl@0: 
sl@0: 	XXYY->XX00, XX00->0000
sl@0: 	Return original state
sl@0: 
sl@0: 	Enter and return with interrupts disabled.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::CancelFinalStateChange()
sl@0: 	{
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("tst r0, #0x00FF ");
sl@0: 	asm("bicne r2, r0, #0x00FF ");	// XXYY->XX00
sl@0: 	asm("moveq r2, #0 ");			// xx00->0000
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /**	Transition the state of an IDFC or DFC when QueueOnIdle() is called
sl@0: 
sl@0: 	0000->002g where g = TheScheduler.iIdleGeneration,
sl@0: 	00Cn->006n, all other states unchanged
sl@0: 	Return original state.
sl@0: 
sl@0: 	Enter and return with interrupts disabled and IdleSpinLock held.
sl@0: */
sl@0: __NAKED__ TUint32 TDfc::QueueOnIdleStateChange()
sl@0: 	{
sl@0: 	asm("ldr r12, __IdleGeneration ");
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	asm("ldrb r1, [r12] ");			// r1 = TheScheduler.iIdleGeneration
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r12);
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("cmp r0, #0 ");				// original state 0000 ?
sl@0: 	asm("orreq r2, r1, #0x0020 ");	// yes -> 002g
sl@0: 	asm("movne r2, r0 ");			// no -> R2=original state ...
sl@0: 	asm("eorne r12, r0, #0x00C0 ");	// ... and R12=original state^00C0 ...
sl@0: 	asm("cmpne r12, #0x0020 ");		// ... and check if result < 0020 (i.e. original==00C0..00DF)
sl@0: 	asm("sublo r2, r2, #0x0060 ");	// 00Cn->006n otherwise leave R2 alone
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: 	__DATA_MEMORY_BARRIER__(r12);
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: __NAKED__ void TDfc::ResetState()
sl@0: 	{
sl@0: 	asm("add r3, r0, #%a0" : : "i" _FOFF(TDfc,iDfcState));
sl@0: 	__DATA_MEMORY_BARRIER_Z__(r2);
sl@0: #ifdef _DEBUG
sl@0: 	asm("1: ");
sl@0: 	LDREXH(0,3);
sl@0: 	asm("cmp r0, #0 ");
sl@0: 	asm("beq 0f ");				// if state already zero, die
sl@0: 	STREXH(12,2,3);
sl@0: 	asm("cmp r12, #0 ");
sl@0: 	asm("bne 1b ");
sl@0: #else
sl@0: 	asm("strh r2, [r3] ");		// __e32_atomic_store_rel16(&iDfcState, 0)
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: #ifdef _DEBUG
sl@0: 	asm("0: ");
sl@0: 	__ASM_CRASH();
sl@0: #endif
sl@0: 	}
sl@0: 
sl@0: 
sl@0: