sl@0: // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\nkern\arm\ncutils.cia
sl@0: // 
sl@0: //
sl@0: 
sl@0: #include <e32cia.h>
sl@0: #include <arm.h>
sl@0: 
sl@0: //#define __DBG_MON_FAULT__
sl@0: //#define __RAM_LOADED_CODE__
sl@0: //#define __EARLY_DEBUG__
sl@0: 
sl@0: #ifdef _DEBUG
sl@0: #define ASM_KILL_LINK(rp,rs)	asm("mov "#rs", #0xdf ");\
sl@0: 								asm("orr "#rs", "#rs", "#rs", lsl #8 ");\
sl@0: 								asm("orr "#rs", "#rs", "#rs", lsl #16 ");\
sl@0: 								asm("str "#rs", ["#rp"] ");\
sl@0: 								asm("str "#rs", ["#rp", #4] ");
sl@0: #else
sl@0: #define ASM_KILL_LINK(rp,rs)
sl@0: #endif
sl@0: 
sl@0: 
sl@0: #ifdef __PRI_LIST_MACHINE_CODED__
sl@0: /** Return the priority of the highest priority item present on a priority list.
sl@0: 
sl@0: 	@return	The highest priority present or -1 if the list is empty.
sl@0:  */
sl@0: EXPORT_C __NAKED__ TInt TPriListBase::HighestPriority()
sl@0: 	{
sl@0: #ifdef __CPU_ARM_HAS_CLZ
sl@0: 	asm("ldr r2, [r0, #4] ");				// r2=iPresent MSW
sl@0: 	asm("ldr r1, [r0, #0] ");				// r1=iPresent LSW
sl@0: 	CLZ(0,2);								// r0=31-MSB(r2)
sl@0: 	asm("subs r0, r0, #32 ");				// r0=-1-MSB(r2), 0 if r2=0
sl@0: 	CLZcc(CC_EQ,0,1);						// if r2=0, r0=31-MSB(r1)
sl@0: 	asm("rsb r0, r0, #31 ");				// r0=highest priority
sl@0: #else
sl@0: 	asm("ldmia r0, {r1,r2} ");				// r2:r1=iPresent
sl@0: 	asm("mov r0, #31 ");					// start at 31
sl@0: 	asm("cmp r2, #0 ");						// high word non-zero?
sl@0: 	asm("movne r0, #63 ");					// if so, start at 63
sl@0: 	asm("movne r1, r2 ");					// and set r1=high word
sl@0: 	asm("cmp r1, #0 ");
sl@0: 	asm("beq highest_pri_0 ");
sl@0: 	asm("cmp r1, #0x00010000 ");
sl@0: 	asm("movcc r1, r1, lsl #16 ");
sl@0: 	asm("subcc r0, r0, #16 ");
sl@0: 	asm("cmp r1, #0x01000000 ");
sl@0: 	asm("movcc r1, r1, lsl #8 ");
sl@0: 	asm("subcc r0, r0, #8 ");
sl@0: 	asm("cmp r1, #0x10000000 ");
sl@0: 	asm("movcc r1, r1, lsl #4 ");
sl@0: 	asm("subcc r0, r0, #4 ");
sl@0: 	asm("cmp r1, #0x40000000 ");
sl@0: 	asm("movcc r1, r1, lsl #2 ");
sl@0: 	asm("subcc r0, r0, #2 ");
sl@0: 	asm("cmp r1, #0x80000000 ");
sl@0: 	asm("subcc r0, r0, #1 ");
sl@0: 	__JUMP(,lr);
sl@0: 	asm("highest_pri_0: ");
sl@0: 	asm("mvn r0, #0 ");						// if list empty, return -1
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /** Find the highest priority item present on a priority list.
sl@0: 	If multiple items at the same priority are present, return the first to be
sl@0: 	added in chronological order.
sl@0: 
sl@0: 	@return	a pointer to the item or NULL if the list is empty.
sl@0:  */
sl@0: EXPORT_C __NAKED__ TPriListLink* TPriListBase::First()
sl@0: 	{
sl@0: #ifdef __CPU_ARM_HAS_CLZ
sl@0: 	asm("ldr r2, [r0, #4] ");				// r2=iPresent MSW
sl@0: 	asm("ldr r1, [r0], #8 ");				// r1=iPresent LSW, r0=&iQueue[0]
sl@0: 	CLZ(3,2);								// r3=31-MSB(r2)
sl@0: 	asm("subs r3, r3, #32 ");				// r3=-1-MSB(r2), 0 if r2=0
sl@0: 	CLZcc(CC_EQ,3,1);						// if r2=0, r3=31-MSB(r1)
sl@0: 	asm("rsbs r3, r3, #31 ");				// r3=highest priority
sl@0: 	asm("ldrpl r0, [r0, r3, lsl #2] ");		// if r3>=0 list is nonempty, r0->first entry
sl@0: 	asm("movmi r0, #0 ");					// if r3<0 list empty, return NULL
sl@0: #else
sl@0: 	asm("ldmia r0!, {r1,r2} ");				// r2:r1=iPresent, r0=&iQueue[0]
sl@0: 	asm("cmp r2, #0 ");						// high word non-zero?
sl@0: 	asm("addne r0, r0, #128 ");				// if so, r0=&iQueue[32]
sl@0: 	asm("movne r1, r2 ");					// and set r1=high word
sl@0: 	asm("cmp r1, #0x00010000 ");
sl@0: 	asm("movcc r1, r1, lsl #16 ");
sl@0: 	asm("addcs r0, r0, #0x40 ");			// if iPresent>=0x00010000, step r0 on by 16 words
sl@0: 	asm("cmp r1, #0x01000000 ");
sl@0: 	asm("movcc r1, r1, lsl #8 ");
sl@0: 	asm("addcs r0, r0, #0x20 ");			// if iPresent>=0x01000000, step r0 on by 8 words
sl@0: 	asm("cmp r1, #0x10000000 ");
sl@0: 	asm("movcc r1, r1, lsl #4 ");
sl@0: 	asm("addcs r0, r0, #0x10 ");			// if iPresent>=0x10000000, step r0 on by 4 words
sl@0: 	asm("cmp r1, #0x40000000 ");
sl@0: 	asm("movcc r1, r1, lsl #2 ");
sl@0: 	asm("addcs r0, r0, #0x08 ");			// if iPresent>=0x40000000, step r0 on by 2 words
sl@0: 	asm("cmp r1, #0 ");
sl@0: 	asm("addmi r0, r0, #4 ");				// if iPresent>=0x80000000, step r0 on by 1 word
sl@0: 	asm("ldrne r0, [r0] ");					// if iPresent was not zero, r0 points to first entry
sl@0: 	asm("moveq r0, #0 ");					// else r0=NULL
sl@0: #endif
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /** Add an item to a priority list.
sl@0: 
sl@0: 	@param aLink = a pointer to the item - must not be NULL
sl@0:  */
sl@0: EXPORT_C __NAKED__ void TPriListBase::Add(TPriListLink* /*aLink*/)
sl@0: 	{
sl@0: 	asm("ldrb r2, [r1, #8]" );				// r2=priority of aLink
sl@0: 	asm("add ip, r0, #8 ");					// ip=&iQueue[0]
sl@0: 	asm("ldr r3, [ip, r2, lsl #2]! ");		// r3->first entry at this priority
sl@0: 	asm("cmp r3, #0 ");						// is this first entry at this priority?
sl@0: 	asm("bne pri_list_add_1 ");				// branch if not
sl@0: 	asm("str r1, [ip] ");					// if queue originally empty, iQueue[pri]=aThread
sl@0: 	asm("ldrb ip, [r0, r2, lsr #3]! ");		// ip=relevant byte of present mask, r0->same
sl@0: 	asm("and r2, r2, #7 ");
sl@0: 	asm("mov r3, #1 ");
sl@0: 	asm("str r1, [r1, #0] ");				// aThread->next=aThread
sl@0: 	asm("orr ip, ip, r3, lsl r2 ");			// ip |= 1<<(pri&7)
sl@0: 	asm("str r1, [r1, #4] ");				// aThread->iPrev=aThread
sl@0: 	asm("strb ip, [r0] ");					// update relevant byte of present mask
sl@0: 	__JUMP(,lr);
sl@0: 	asm("pri_list_add_1: ");
sl@0: 	asm("ldr ip, [r3, #4] ");				// if nonempty, ip=last
sl@0: 	asm("str r1, [r3, #4] ");				// first->prev=aThread
sl@0: 	asm("stmia r1, {r3,ip} ");				// aThread->next=r3=first, aThread->prev=ip=last
sl@0: 	asm("str r1, [ip, #0] ");				// last->next=aThread
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: /** Change the priority of an item on a priority list
sl@0: 
sl@0: 	@param	aLink = pointer to the item to act on - must not be NULL
sl@0: 	@param	aNewPriority = new priority for the item
sl@0:  */
sl@0: EXPORT_C __NAKED__ void TPriListBase::ChangePriority(TPriListLink* /*aLink*/, TInt /*aNewPriority*/)
sl@0: 	{
sl@0: 	asm("ldrb r3, [r1, #8] ");				// r3=old priority
sl@0: 	asm("stmfd sp!, {r4-r6,lr} ");
sl@0: 	asm("cmp r3, r2 ");
sl@0: 	asm("ldmeqfd sp!, {r4-r6,pc} ");		// if old priority=new, finished
sl@0: 	asm("ldmia r1, {r4,r12} ");				// r4=next, r12=prev
sl@0: 	asm("ldmia r0!, {r6,lr} ");				// lr:r6=present mask, r0=&iQueue[0]
sl@0: 	asm("subs r5, r4, r1 ");				// check if aLink is only one at that priority, r5=0 if it is
sl@0: 	asm("beq change_pri_1 ");				// branch if it is
sl@0: 	asm("ldr r5, [r0, r3, lsl #2] ");		// r5=iQueue[old priority]
sl@0: 	asm("str r4, [r12, #0] ");				// prev->next=next
sl@0: 	asm("str r12, [r4, #4] ");				// next->prev=prev
sl@0: 	asm("cmp r5, r1 ");						// was aLink first?
sl@0: 	asm("streq r4, [r0, r3, lsl #2] ");		// if it was, iQueue[old priority]=aLink->next
sl@0: 	asm("b change_pri_2 ");
sl@0: 	asm("change_pri_1: ");
sl@0: 	asm("str r5, [r0, r3, lsl #2] ");		// if empty, set iQueue[old priority]=NULL
sl@0: 	asm("mov r12, #0x80000000 ");
sl@0: 	asm("rsbs r3, r3, #31 ");				// r3=31-priority
sl@0: 	asm("bicmi lr, lr, r12, ror r3 ");		// if pri>31, clear bit is MS word
sl@0: 	asm("bicpl r6, r6, r12, ror r3 ");		// if pri<=31, clear bit in LS word
sl@0: 	asm("change_pri_2: ");
sl@0: 	asm("ldr r4, [r0, r2, lsl #2] ");		// r4=iQueue[new priority]
sl@0: 	asm("strb r2, [r1, #8] ");				// store new priority
sl@0: 	asm("cmp r4, #0 ");						// new priority queue empty?
sl@0: 	asm("bne change_pri_3 ");				// branch if not
sl@0: 	asm("str r1, [r0, r2, lsl #2] ");		// if new priority queue was empty, iQueue[new p]=aLink
sl@0: 	asm("mov r12, #0x80000000 ");
sl@0: 	asm("str r1, [r1, #0] ");				// aLink->next=aLink
sl@0: 	asm("rsbs r2, r2, #31 ");				// r2=31-priority
sl@0: 	asm("str r1, [r1, #4] ");				// aLink->prev=aLink
sl@0: 	asm("orrmi lr, lr, r12, ror r2 ");		// if pri>31, set bit is MS word
sl@0: 	asm("orrpl r6, r6, r12, ror r2 ");		// if pri<=31, set bit in LS word
sl@0: 	asm("stmdb r0!, {r6,lr} ");				// store present mask and restore r0
sl@0: 	asm("ldmfd sp!, {r4-r6,pc} ");
sl@0: 	asm("change_pri_3: ");
sl@0: 	asm("ldr r12, [r4, #4] ");				// r12->last link at this priority
sl@0: 	asm("str r1, [r4, #4] ");				// first->prev=aLink
sl@0: 	asm("str r1, [r12, #0] ");				// old last->next=aLink
sl@0: 	asm("stmia r1, {r4,r12} ");				// aLink->next=r3=first, aLink->prev=r12=old last
sl@0: 	asm("stmdb r0!, {r6,lr} ");				// store present mask and restore r0
sl@0: 	asm("ldmfd sp!, {r4-r6,pc} ");
sl@0: 	}
sl@0: #endif
sl@0: 
sl@0: __NAKED__ void initialiseState()
sl@0: 	{
sl@0: 	// entry in mode_svc with irqs and fiqs off	
sl@0: 	asm("mrs r0, cpsr ");
sl@0: 	asm("bic r1, r0, #0x1f ");
sl@0: 	asm("orr r1, r1, #0xd3 ");				// mode_svc
sl@0: 	asm("msr cpsr, r1 ");
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: // Called by a thread when it first runs
sl@0: __NAKED__ void __StartThread()
sl@0: 	{
sl@0: 	// On entry r4->current thread, r5->entry point, r6->parameter block
sl@0: 	asm("mov r0, r6 ");
sl@0: 	USER_MEMORY_GUARD_OFF_IF_MODE_USR(r6);
sl@0: 	ERRATUM_353494_MODE_CHANGE(,r6);
sl@0: 	asm("mov lr, pc ");
sl@0: 	asm("movs pc, r5 ");
sl@0: 	asm("b  " CSM_ZN5NKern4ExitEv);
sl@0: 	}
sl@0: 
sl@0: // Called by a thread which has been forced to exit
sl@0: // Interrupts off here, kernel unlocked
sl@0: __NAKED__ void __DoForcedExit()
sl@0: 	{
sl@0: 	asm("mov r0, #0x13 ");
sl@0: 	asm("msr cpsr, r0 ");		// interrupts back on
sl@0: 	asm("bic sp, sp, #4 ");		// align stack since it may be misaligned on return from scheduler
sl@0: 	asm("bl  " CSM_ZN5NKern4LockEv);	// lock the kernel (must do this before setting iCsCount=0)
sl@0: 	asm("ldr r0, __TheScheduler ");			// r0 points to scheduler data
sl@0: 	asm("mov r1, #0 ");
sl@0: 	asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));	// r0=iCurrentThread
sl@0: 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount));	// set iCsCount=0
sl@0: 	asm("b  " CSM_ZN11NThreadBase4ExitEv);	// exit
sl@0: 
sl@0: 	asm("__TheScheduler: ");
sl@0: 	asm(".word TheScheduler ");
sl@0: 	asm("__BTraceData: ");
sl@0: 	asm(".word BTraceData ");
sl@0: 	asm("__DBTraceFilter2_iCleanupHead:");
sl@0: #ifdef __EABI__
sl@0: 	asm(".word _ZN14DBTraceFilter212iCleanupHeadE");
sl@0: #else
sl@0: 	asm(".word _14DBTraceFilter2.iCleanupHead");
sl@0: #endif
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** @internalTechnology
sl@0: 
sl@0: 	Called to indicate that the system has crashed and all CPUs should be
sl@0: 	halted and should dump their registers.
sl@0: 
sl@0: */
sl@0: __NAKED__ void NKern::NotifyCrash(const TAny* /*a0*/, TInt /*a1*/)
sl@0: 	{
sl@0: 	asm("stmfd	sp!, {r0-r1} ");			// save parameters
sl@0: 	asm("ldr	r0, __CrashState ");
sl@0: 	asm("mov	r1, #1 ");
sl@0: 	asm("str	r1, [r0] ");				// CrashState = ETrue
sl@0: 	asm("ldr	r0, __TheScheduler ");
sl@0: 	asm("ldr	r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,i_Regs));
sl@0: 	asm("ldr	r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode));
sl@0: 	asm("cmp	r1, #0 ");					// context already saved?
sl@0: 	asm("bge	state_already_saved ");		// skip if so
sl@0: 	asm("mov	r1, lr ");
sl@0: 	asm("bl "	CSM_ZN3Arm9SaveStateER14SFullArmRegSet );
sl@0: 	asm("str	r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iN.iR15));
sl@0: 	asm("ldmia	sp!, {r2-r3} ");			// original R0,R1
sl@0: 	asm("stmia	r0, {r2-r3} ");				// save original R0,R1
sl@0: 	asm("add	r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
sl@0: 	asm("stmib	r1, {r2-r3} ");				// save a0, a1 in iCrashArgs
sl@0: 	asm("mov	r1, #13 ");					// r1 = regnum
sl@0: 	asm("mrs	r2, cpsr ");				// r2 = mode
sl@0: 	asm("bl "	CSM_ZN3Arm3RegER14SFullArmRegSetim );	// r0 = pointer to exception mode R13
sl@0: 	asm("str	sp, [r0] ");				// save correct original value for exception mode R13
sl@0: 	asm("b		state_save_complete ");
sl@0: 
sl@0: 	asm("state_already_saved: ");
sl@0: 	asm("ldmia	sp!, {r2-r3} ");			// original R0,R1
sl@0: 	asm("add	r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
sl@0: 	asm("ldr	r4, [r1, #4]! ");
sl@0: 	asm("cmp	r4, #0 ");
sl@0: 	asm("stmeqia	r1, {r2-r3} ");			// save a0, a1 in iCrashArgs, provided iCrashArgs not already set
sl@0: 	asm("state_save_complete: ");
sl@0: 
sl@0: 	asm("mov	r2, #0xd1 ");
sl@0: 	asm("msr	cpsr, r2 ");				// mode_fiq, interrupts off
sl@0: 	asm("mov	r4, r0 ");
sl@0: 	asm("bic	sp, sp, #4 ");				// align stack to multiple of 8
sl@0: 
sl@0: 	asm("mov	r0, #0 ");
sl@0: 	asm("mov	r1, #0 ");
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("bl		NKCrashHandler ");
sl@0: 
sl@0: 	asm("mov	r0, #1 ");
sl@0: 	asm("ldr	r1, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR0));	// original R0 = a0 parameter
sl@0: 	asm("ldr	r2, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR1));	// original R1 = a1 parameter
sl@0: 	asm("bl		NKCrashHandler ");
sl@0: 
sl@0: 	// shouldn't get back here
sl@0: 	__ASM_CRASH();
sl@0: 
sl@0: 	asm("__CrashState: ");
sl@0: 	asm(".word %a0" : : "i" ((TInt)&CrashState));
sl@0: 	}
sl@0: 
sl@0: 
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::Out(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("adr	lr, 9f");
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	asm("ldrne	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	asm("9:");
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("ldr	r4, [sp, #16]");	// r2 = aDataSize
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("cmp	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0: 	asm("movhi	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0:  	asm("orrhi	r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
sl@0: 	asm("add	r0, r0, r4");
sl@0: 	asm("subs	r4, r4, #1");
sl@0: 	asm("ldrhs	r2, [r3]");			// get first word of aData is aDataSize!=0
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("cmp	r4, #4");
sl@0: 	asm("strlo	r2, [sp, #4]");		// replace aData with first word if aDataSize is 1-4
sl@0: 
sl@0: 	asm("mov	lr, pc");
sl@0: 	asm("ldr	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("ldr	lr, __TheScheduler");
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	// set r2 = context id
sl@0: 	asm("ldrb	r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
sl@0: 	asm("mrs	r2, cpsr");
sl@0: 	asm("and	r2, r2, #0x0f");
sl@0: 	asm("cmp	r2, #3");
sl@0: 	asm("movhi	r2, #2");		// r2 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
sl@0: 	asm("cmpeq	r4, #0");
sl@0: 	asm("ldreq	r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
sl@0: 
sl@0: 	asm("mov	lr, pc");
sl@0: 	asm("ldr	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("ldr	r4, [sp, #16]");	// r2 = aDataSize
sl@0: 	asm("ldr	lr, __TheScheduler");
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("cmp	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0: 	asm("movhi	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0:  	asm("orrhi	r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
sl@0: 	asm("add	r0, r0, r4");
sl@0: 	asm("subs	r4, r4, #1");
sl@0: 	asm("ldrhs	r2, [r3]");			// get first word of aData is aDataSize!=0
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("cmp	r4, #4");
sl@0: 	asm("strlo	r2, [sp, #4]");		// replace aData with first word if aDataSize is 1-4
sl@0: 
sl@0: 	// set r2 = context id
sl@0: 	asm("ldrb	r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
sl@0: 	asm("mrs	r2, cpsr");
sl@0: 	asm("and	r2, r2, #0x0f");
sl@0: 	asm("cmp	r2, #3");
sl@0: 	asm("movhi	r2, #2");		// r2 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
sl@0: 	asm("cmpeq	r4, #0");
sl@0: 	asm("ldreq	r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
sl@0: 
sl@0: 	asm("mov	lr, pc");
sl@0: 	asm("ldr	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r4,lr}");
sl@0: 	asm("and	r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("cmp	r4, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r4,");
sl@0: 
sl@0: 	asm("ldr	r12, __TheScheduler");
sl@0: 	asm("stmdb	sp!, {lr}");
sl@0: 	asm("ldrb	lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
sl@0: 	asm("mrs	r4, cpsr");
sl@0: 	asm("and	r4, r4, #0x0f");
sl@0: 	asm("cmp	r4, #3");
sl@0: 	asm("movhi	r4, #2");		// r4 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
sl@0: 	asm("cmpeq	lr, #0");
sl@0: 	asm("ldreq	r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
sl@0: 	asm("stmdb	sp!, {r4}");
sl@0: 	asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
sl@0: 	asm("add	sp, sp, #8");
sl@0: 	__POPRET("r4,");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: __NAKED__ TBool DBTraceFilter2::Check(TUint32 aUid)
sl@0: 	{
sl@0: 	asm("stmdb	sp!, {lr}");
sl@0: 	asm("ldr	r3, [r0,#%a0]" : : "i" _FOFF(DBTraceFilter2,iNumUids));
sl@0: 	asm("add	r0, r0, #%a0" : : "i" _FOFF(DBTraceFilter2,iUids));
sl@0: 	asm("mov	r2, #0");
sl@0: 	asm("0:");
sl@0: 	asm("cmp	r3, r2");
sl@0: 	asm("bls	9f");
sl@0: 	asm("add	r12, r2, r3");
sl@0: 	asm("mov	r12, r12, asr #1");
sl@0: 	asm("ldr	lr, [r0, r12, lsl #2]");
sl@0: 	asm("cmp	r1, lr");
sl@0: 	asm("addhi	r2, r12, #1");
sl@0: 	asm("movlo	r3, r12");
sl@0: 	asm("bne	0b");
sl@0: 	asm("movs	r0, #1");
sl@0: 	__POPRET("");
sl@0: 	asm("9:");
sl@0: 	asm("movs	r0, #0");
sl@0: 	__POPRET("");
sl@0: 	}
sl@0: 
sl@0: 
sl@0: __NAKED__ TBool SBTraceData::CheckFilter2(TUint32 aUid)
sl@0: 	{
sl@0: 	asm("btrace_check_filter2:");
sl@0: 	// returns r0 = 0 or 1 indicating if trace passed the filter check
sl@0: 	// returns r2 = trace context id
sl@0: 
sl@0: 	asm("ldr	r12, __TheScheduler");
sl@0: 	asm("stmdb	sp!, {r4-r6,lr}");
sl@0: 	asm("mrs	r2, cpsr");
sl@0: 	// r2 = cpsr
sl@0: 	asm("ldrb	lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
sl@0: 	asm("and	r4, r2, #0x0f");
sl@0: 	asm("cmp	r4, #3");
sl@0: 	asm("movhi	r4, #2");		// r4 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
sl@0: 	asm("cmpeq	lr, #0");
sl@0: 	asm("ldreq	lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iKernCSLocked));
sl@0: 	asm("ldreq	r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
sl@0: 	asm("cmpeq	lr, #0");
sl@0: 	// r4 = context value for trace
sl@0: 	// zero flag set if we need to enter a critical section
sl@0: 
sl@0: 	// NKern::ThreadEnterCS()
sl@0: 	asm("ldreq	r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount));
sl@0: 	asm("movne	r5, #0");
sl@0: 	asm("addeq	r5, r5, #1");
sl@0: 	asm("streq	r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount));
sl@0: 	// r5 = true if we entered a critical section
sl@0: 
sl@0: 	// DBTraceFilter2::Open()
sl@0: 	INTS_OFF(r12, r2, INTS_ALL_OFF);
sl@0: 	asm("ldr	r0, [r0, #%a0]" : : "i" (_FOFF(SBTraceData,iFilter2)));
sl@0: 	asm("cmp	r0, #1");
sl@0: 	asm("ldrhi	r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
sl@0: 	asm("addhi	r12, r12, #1");
sl@0: 	asm("strhi	r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
sl@0: 	asm("msr	cpsr_c, r2");
sl@0: 	asm("bls	8f");
sl@0: 
sl@0: 
sl@0: 	asm("mov	r6, r0");
sl@0: 	asm("bl		Check__14DBTraceFilter2Ul");
sl@0: 	// r0 = result
sl@0: 
sl@0: 
sl@0: 	// DBTraceFilter2::Close()
sl@0: 	asm("mrs	r2, cpsr");
sl@0: 	INTS_OFF(r12, r2, INTS_ALL_OFF);
sl@0: 	asm("ldr	r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
sl@0: 	asm("ldr	r1, __DBTraceFilter2_iCleanupHead");
sl@0: 	asm("subs	r12, r12, #1");
sl@0: 	asm("str	r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
sl@0: 	asm("ldreq	r12, [r1]");
sl@0: 	asm("streq	r6, [r1]");
sl@0: 	asm("streq	r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iCleanupLink));
sl@0: 	asm("msr	cpsr_c, r2");
sl@0: 
sl@0: 	// NKern::ThreadLeaveCS()	
sl@0: 	asm("8:");
sl@0: 	asm("cmp	r5, #0");
sl@0: 	asm("beq	9f");
sl@0: 	asm("mov	r5, r0");
sl@0: 	asm("bl " CSM_ZN5NKern13ThreadLeaveCSEv);
sl@0: 	asm("mov	r0, r5");
sl@0: 	asm("9:");
sl@0: 	asm("mov	r2, r4"); // r2 = context id
sl@0: 	__POPRET("r4-r6,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFiltered(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
sl@0: 	{
sl@0: 	// fall through to OutFilteredX...
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFilteredX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("stmdb	sp!, {r0,r3,r12}");
sl@0: 	asm("mov	r0, r12");
sl@0: 	asm("bl		btrace_check_filter2");
sl@0: 	asm("cmp	r0, #0");
sl@0: 	asm("ldmia	sp!, {r0,r3,r12}");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("adr	lr, 9f");
sl@0: 	asm("ldr	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	asm("9:");
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFilteredN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	// fall through to OutFilteredNX...
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFilteredNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r2,r3,r4,lr}");
sl@0: 	asm("and	r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("cmp	r2, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("stmdb	sp!, {r0,r1,r3,r12}");
sl@0: 	asm("mov	r0, r12");
sl@0: 	asm("bl		btrace_check_filter2");
sl@0: 	asm("cmp	r0, #0");
sl@0: 	asm("ldmia	sp!, {r0,r1,r3,r12}");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r2,r3,r4,");
sl@0: 
sl@0: 	asm("ldr	r4, [sp, #16]");	// r4 = aDataSize
sl@0: 	asm("cmp	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0: 	asm("movhi	r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
sl@0:  	asm("orrhi	r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
sl@0: 	asm("add	r0, r0, r4");
sl@0: 	asm("subs	r4, r4, #1");
sl@0: 	asm("ldrhs	lr, [r3]");			// get first word of aData is aDataSize!=0
sl@0: 	asm("mov	r3, r1");			// r3 = a1 (ready for call to handler)
sl@0: 	asm("cmp	r4, #4");
sl@0: 	asm("strlo	lr, [sp, #4]");		// replace aData with first word if aDataSize is 1-4
sl@0: 
sl@0: 	asm("mov	lr, pc");
sl@0: 	asm("ldr	pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
sl@0: 	__POPRET("r2,r3,r4,");
sl@0: 	}
sl@0: 
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFilteredBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("ldr	r12, __BTraceData");
sl@0: 	asm("stmdb	sp!, {r4,lr}");
sl@0: 	asm("and	r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
sl@0: 	asm("ldrb	r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
sl@0: 	asm("cmp	r4, #0");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r4,");
sl@0: 
sl@0: 	asm("stmdb	sp!, {r0-r3,r4,lr}");
sl@0: 	asm("mov	r0, r12");
sl@0: 	asm("bl		btrace_check_filter2");
sl@0: 	asm("cmp	r0, #0");
sl@0: 	asm("mov	r12, r2");
sl@0: 	asm("ldmia	sp!, {r0-r3,r4,lr}");
sl@0: 	asm("moveq	r0, #0");
sl@0: 	__CPOPRET(eq,"r4,");
sl@0: 
sl@0: 	asm("stmdb	sp!, {r12,lr}");
sl@0: 	asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
sl@0: 	asm("add	sp, sp, #8");
sl@0: 	__POPRET("r4,");
sl@0: 	}
sl@0: 
sl@0: 	
sl@0: __NAKED__ EXPORT_C TBool BTrace::OutFilteredPcFormatBig(TUint32 a0, TUint32 aModuleUid, TUint32 aPc, TUint16 aFormatId, const TAny* aData, TInt aDataSize)
sl@0: 	{
sl@0: 	asm("mov	r0, #0"); //kernel side not implemented yet
sl@0: 	}
sl@0: 
sl@0: /******************************************************************************/
sl@0: 
sl@0: /** Save all the ARM registers
sl@0: 
sl@0: @internalTechnology
sl@0: */
sl@0: __NAKED__ void Arm::SaveState(SFullArmRegSet&)
sl@0: 	{
sl@0: 	asm("stmia	r0, {r0-r14}^ ");	// save R0-R7, R8_usr-R14_usr
sl@0: 	asm("str	lr, [r0, #60]! ");	// save R15
sl@0: 	asm("mrs	r1, cpsr ");
sl@0: 	asm("str	r1, [r0, #4]! ");	// save CPSR
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xd3 ");	// mode_svc, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 	asm("stmib	r0!, {r13,r14} ");	// save R13_svc, R14_svc
sl@0: 	asm("mrs	r3, spsr ");
sl@0: 	asm("str	r3, [r0, #4]! ");	// save SPSR_svc
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xd7 ");	// mode_abt, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 	asm("stmib	r0!, {r13,r14} ");	// save R13_abt, R14_abt
sl@0: 	asm("mrs	r3, spsr ");
sl@0: 	asm("str	r3, [r0, #4]! ");	// save SPSR_abt
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xdb ");	// mode_und, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 	asm("stmib	r0!, {r13,r14} ");	// save R13_und, R14_und
sl@0: 	asm("mrs	r3, spsr ");
sl@0: 	asm("str	r3, [r0, #4]! ");	// save SPSR_und
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xd2 ");	// mode_irq, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 	asm("stmib	r0!, {r13,r14} ");	// save R13_irq, R14_irq
sl@0: 	asm("mrs	r3, spsr ");
sl@0: 	asm("str	r3, [r0, #4]! ");	// save SPSR_irq
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xd1 ");	// mode_fiq, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 	asm("stmib	r0!, {r8-r14} ");	// save R8_fiq ... R14_fiq
sl@0: 	asm("mrs	r3, spsr ");
sl@0: 	asm("str	r3, [r0, #4]! ");	// save SPSR_fiq
sl@0: 	asm("bic	r2, r1, #0x1f ");
sl@0: 	asm("orr	r2, r2, #0xd3 ");	// mode_svc, all interrupts off
sl@0: 	asm("msr	cpsr, r2 ");
sl@0: 
sl@0: 	asm("mov	r4, #0 ");
sl@0: 	asm("mov	r5, #0 ");
sl@0: 	asm("mov	r6, #0 ");
sl@0: 	asm("mov	r7, #0 ");
sl@0: 	asm("mov	r8, #0 ");
sl@0: 	asm("mov	r9, #0 ");
sl@0: 	asm("mov	r10, #0 ");
sl@0: 	asm("mov	r11, #0 ");
sl@0: 
sl@0: 	// monitor mode - skip for now
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("stmib	r0!, {r4-r6} ");	// R13_mon, R14_mon, SPSR_mon
sl@0: 
sl@0: 	// zero spare words
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("stmib	r0!, {r4-r11} ");
sl@0: 	asm("add	r0, r0, #4 ");		// r0 = &a.iA
sl@0: 
sl@0: #ifdef __CPU_ARMV7
sl@0: 	asm("mrc	p14, 6, r3, c1, c0, 0 ");
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// TEEHBR
sl@0: #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
sl@0: 	GET_CAR(,r3);
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// CPACR
sl@0: 
sl@0: 	// skip SCR, SDER, NSACR, PMCR, MVBAR for now
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("stmia	r0!, {r4-r8} ");	// SCR, SDER, NSACR, PMCR, MVBAR
sl@0: 
sl@0: 	// zero spare words
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("stmia	r0!, {r3-r11} ");	// r0 = &a.iB[0]
sl@0: 
sl@0: 	// just fill in iB[0]
sl@0: #ifdef __CPU_HAS_MMU
sl@0: 	asm("mrc	p15, 0, r3, c1, c0, 0 ");
sl@0: 	asm("str	r3, [r0], #4 ");	// SCTLR
sl@0: #ifdef __CPU_HAS_ACTLR
sl@0: 	asm("mrc	p15, 0, r3, c1, c0, 1 ");
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// ACTLR
sl@0: 	asm("mrc	p15, 0, r3, c2, c0, 0 ");
sl@0: 	asm("str	r3, [r0], #4 ");	// TTBR0
sl@0: #ifdef __CPU_HAS_TTBR1
sl@0: 	asm("mrc	p15, 0, r2, c2, c0, 1 ");
sl@0: 	asm("mrc	p15, 0, r3, c2, c0, 2 ");
sl@0: #else
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3} ");	// TTBR1, TTBCR
sl@0: 	asm("mrc	p15, 0, r3, c3, c0, 0 ");
sl@0: 	asm("str	r3, [r0], #4 ");	// DACR
sl@0: #ifdef __CPU_MEMORY_TYPE_REMAPPING
sl@0: 	asm("mrc	p15, 0, r2, c10, c2, 0 ");
sl@0: 	asm("mrc	p15, 0, r3, c10, c2, 1 ");
sl@0: #else
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3} ");	// PRRR, NMRR
sl@0: #ifdef __CPU_ARMV7
sl@0: 	asm("mrc	p15, 0, r3, c12, c0, 0 ");
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// VBAR
sl@0: #if defined(__CPU_SA1) || defined(__CPU_ARM920T) || defined(__CPU_ARM925T) || defined(__CPU_ARMV5T) || defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
sl@0: 	asm("mrc	p15, 0, r3, c13, c0, 0 ");
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// FCSEIDR
sl@0: #if defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
sl@0: 	asm("mrc	p15, 0, r3, c13, c0, 1 ");
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("str	r3, [r0], #4 ");	// CONTEXTIDR
sl@0: #ifdef __CPU_HAS_CP15_THREAD_ID_REG
sl@0: 	GET_RWRW_TID(,r2);
sl@0: 	GET_RWRO_TID(,r3);
sl@0: 	GET_RWNO_TID(,r12);
sl@0: #else
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: 	asm("mov	r12, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3,r12} ");	// RWRWTID, RWROTID, RWNOTID
sl@0: 	asm("mrc	p15, 0, r2, c5, c0, 0 ");	// DFSR
sl@0: #ifdef __CPU_ARM_HAS_SPLIT_FSR
sl@0: 	asm("mrc	p15, 0, r3, c5, c0, 1 ");	// IFSR
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3} ");	// DFSR, IFSR
sl@0: #ifdef __CPU_ARMV7
sl@0: 	asm("mrc	p15, 0, r2, c5, c1, 0 ");	// ADFSR
sl@0: 	asm("mrc	p15, 0, r3, c5, c1, 1 ");	// AIFSR
sl@0: #else
sl@0: 	asm("mov	r2, #0 ");
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3} ");	// ADFSR, AIFSR
sl@0: 	asm("mrc	p15, 0, r2, c6, c0, 0 ");	// DFAR
sl@0: #ifdef __CPU_ARM_HAS_CP15_IFAR
sl@0: 	asm("mrc	p15, 0, r3, c6, c0, 2 ");	// IFAR
sl@0: #else
sl@0: 	asm("mov	r3, #0 ");
sl@0: #endif
sl@0: 	asm("stmia	r0!, {r2,r3} ");	// DFAR, IFAR
sl@0: 
sl@0: 	// zero spare words
sl@0: 	asm("stmia	r0!, {r4-r7} ");
sl@0: 	asm("stmia	r0!, {r4-r11} ");
sl@0: #else	// __CPU_HAS_MMU
sl@0: 	asm("stmia	r0!, {r4-r11} ");	// no MMU so zero fill
sl@0: 	asm("stmia	r0!, {r4-r11} ");	// no MMU so zero fill
sl@0: 	asm("stmia	r0!, {r4-r11} ");	// no MMU so zero fill
sl@0: 	asm("stmia	r0!, {r4-r11} ");	// no MMU so zero fill
sl@0: #endif	// __CPU_HAS_MMU
sl@0: 
sl@0: 	// zero iB[1]
sl@0: 	asm("stmia	r0!, {r4-r11} ");
sl@0: 	asm("stmia	r0!, {r4-r11} ");
sl@0: 	asm("stmia	r0!, {r4-r11} ");
sl@0: 	asm("stmia	r0!, {r4-r11} ");	// r0 = &a.iMore[0]
sl@0: 	asm("add	r1, r0, #62*8 ");	// r1 = &a.iExcCode
sl@0: 
sl@0: 	// Save VFP state
sl@0: 	// Save order:
sl@0: 	//				FPEXC	FPSCR
sl@0: 	// VFPv2 ONLY:	FPINST	FPINST2
sl@0: 	//				D0-D3	D4-D7	D8-D11	D12-D15 
sl@0: 	// VFPv3 ONLY:	D16-D19	D20-D23	D24-D27	D28-D31
sl@0: #ifdef __CPU_HAS_VFP
sl@0: 	GET_CAR(,r2);
sl@0: 	asm("bic	r2, r2, #0x00f00000 ");
sl@0: #ifdef __VFP_V3
sl@0: 	asm("bic	r2, r2, #0xc0000000 ");	// mask off ASEDIS, D32DIS
sl@0: #endif
sl@0: 	asm("orr	r2, r2, #0x00500000 ");	// enable privileged access to CP10, CP11
sl@0: 	SET_CAR(,r2);
sl@0: 	VFP_FMRX(,2,VFP_XREG_FPEXC);		// r2=FPEXC
sl@0: 	asm("orr	r3, r2, #%a0" : : "i" ((TInt)VFP_FPEXC_EN));
sl@0: 	VFP_FMXR(,VFP_XREG_FPEXC,3);		// enable VFP
sl@0: 	__DATA_SYNC_BARRIER__(r4);
sl@0: 	__INST_SYNC_BARRIER__(r4);
sl@0: 	VFP_FMRX(,3,VFP_XREG_FPSCR);		// r3=FPSCR
sl@0: 	asm("stmia	r0!, {r2,r3} ");		//
sl@0: #ifdef __VFP_V3
sl@0: 	VFP_FSTMIADW(CC_AL,0,0,16);			// save D0 - D15
sl@0: 	VFP_FMRX(,3,VFP_XREG_MVFR0);
sl@0: 	asm("tst r3, #%a0" : : "i" ((TInt)VFP_MVFR0_ASIMD32)); // Check to see if all 32 Advanced SIMD registers are present
sl@0: 	VFP_FSTMIADW(CC_NE,0,16,16);		// if so then save D16 - D31 (don't need to check CPACR.D32DIS as it is cleared above)
sl@0: #else
sl@0: 	VFP_FMRX(,2,VFP_XREG_FPINST);
sl@0: 	VFP_FMRX(,3,VFP_XREG_FPINST2);
sl@0: 	asm("stmia	r0!, {r2,r3} ");		// FPINST, FPINST2
sl@0: 	VFP_FSTMIADW(CC_AL,0,0,16);			// save D0 - D15
sl@0: #endif
sl@0: #endif	// __CPU_HAS_VFP
sl@0: 	asm("1:		");
sl@0: 	asm("cmp	r0, r1 ");
sl@0: 	asm("strlo	r4, [r0], #4 ");		// clear up to end of iMore[61]
sl@0: 	asm("blo	1b ");
sl@0: 	asm("mov	r1, #%a0" : : "i" ((TInt)KMaxTInt));
sl@0: 	asm("stmia	r0!, {r1,r5-r7} ");		// iExcCode=KMaxTInt, iCrashArgs[0...2]=0
sl@0: 	asm("sub	r0, r0, #1024 ");		// r0 = &a
sl@0: #ifdef __CPU_HAS_VFP
sl@0: 	asm("ldr	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iMore[0]));
sl@0: 	VFP_FMXR(,VFP_XREG_FPEXC,2);		// restore FPEXC
sl@0: 	__DATA_SYNC_BARRIER__(r4);
sl@0: 	__INST_SYNC_BARRIER__(r4);
sl@0: 	asm("ldr	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iA.iCPACR));
sl@0: 	SET_CAR(,r2);						// restore CPACR
sl@0: #endif
sl@0: 	asm("ldr	r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
sl@0: 	asm("orr	r1, r1, #0xC0 ");		// interrupts off
sl@0: 	asm("msr	cpsr, r1 ");			// restore CPSR with interrupts off
sl@0: 	asm("ldmia	r0, {r0-r11} ");		// restore R4-R11
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Update the saved ARM registers with information from an exception
sl@0: 
sl@0: @internalTechnology
sl@0: */
sl@0: __NAKED__ void Arm::UpdateState(SFullArmRegSet&, TArmExcInfo&)
sl@0: 	{
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13Svc));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR4));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR5));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR6));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR7));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR8));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR9));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR10));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR11));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14Svc));
sl@0: 	asm("ldr	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode));
sl@0: 	asm("ldmia	r1!, {r2,r3} ");	// r2=iFaultAddress, r3=iFaultStatus
sl@0: 	asm("cmp	r12, #%a0 " : : "i" ((TInt)EArmExceptionPrefetchAbort));
sl@0: 	asm("streq	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFAR));
sl@0: 	asm("strne	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFAR));
sl@0: 	asm("streq	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFSR));
sl@0: 	asm("strne	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFSR));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iSpsrSvc));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR0));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR1));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR2));
sl@0: 	asm("ldmia	r1!, {r2,r3,r12} ");
sl@0: 	asm("str	r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR3));
sl@0: 	asm("str	r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR12));
sl@0: 	asm("str	r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR15));
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Get a pointer to a stored integer register, accounting for registers which
sl@0: 	are banked across modes.
sl@0: 
sl@0: @param	a		Pointer to saved register block
sl@0: @param	aRegNum	Number of register required, 0-15 or -1 (indicates SPSR)
sl@0: @param	aMode	Bottom 5 bits indicate which processor mode
sl@0: 				Other bits of aMode are ignored
sl@0: @return			Pointer to the required saved register value
sl@0: 
sl@0: @internalTechnology
sl@0: */
sl@0: __NAKED__ TArmReg* Arm::Reg(SFullArmRegSet& /*a*/, TInt /*aRegNum*/, TArmReg /*aMode*/)
sl@0: 	{
sl@0: 	asm("cmp	r1, #8 ");				// register number < 8 ?
sl@0: 	asm("addlo	r0, r0, r1, lsl #2 ");	// register R0-R7 are not banked
sl@0: 	asm("blo	0f ");
sl@0: 	asm("cmp	r1, #15 ");				// register number = 15 ?
sl@0: 	asm("addeq	r0, r0, r1, lsl #2 ");	// register R15 not banked
sl@0: 	asm("movgt	r0, #0 ");				// no registers > 15
sl@0: 	asm("bge	0f ");
sl@0: 	asm("cmn	r1, #1 ");
sl@0: 	asm("movlt	r0, #0 ");				// no registers < -1
sl@0: 	asm("blt	0f ");
sl@0: 	asm("and	r12, r2, #0x1F ");
sl@0: 	asm("cmp	r12, #0x11 ");			// mode_fiq?
sl@0: 	asm("beq	1f ");					// skip if it is
sl@0: 	asm("cmp	r1, #13 ");
sl@0: 	asm("addlo	r0, r0, r1, lsl #2 ");	// register R8-R12 are only banked in mode_fiq
sl@0: 	asm("blo	0f ");
sl@0: 	asm("cmp	r12, #0x10 ");			// mode_usr ?
sl@0: 	asm("cmpne	r12, #0x1F ");			// if not, mode_sys ?
sl@0: 	asm("bne	2f ");					// skip if neither
sl@0: 	asm("cmp	r1, #16 ");
sl@0: 	asm("addlo	r0, r0, r1, lsl #2 ");	// handle R13_usr, R14_usr
sl@0: 	asm("movhs	r0, #0 ");				// no SPSR in mode_usr or mode_sys
sl@0: 	asm("blo	0f ");
sl@0: 	asm("1: ");							// mode_fiq, regnum = 8-12
sl@0: 	asm("2: ");							// exception mode, regnum not 0-12 or 15
sl@0: 	asm("cmn	r1, #1 ");				// regnum = -1 ?
sl@0: 	asm("moveq	r1, #15 ");				// if so, change to 15
sl@0: 	asm("sub	r1, r1, #13 ");
sl@0: 	asm("add	r0, r0, r1, lsl #2 ");	// add 0 for R13, 4 for R14, 8 for SPSR
sl@0: 	asm("cmp	r12, #0x16 ");
sl@0: 	asm("addeq	r0, r0, #12 ");			// if mon, add offset from R13Fiq to R13Mon
sl@0: 	asm("cmpne	r12, #0x11 ");
sl@0: 	asm("addeq	r0, r0, #32 ");			// if valid but not svc/abt/und/irq, add offset from R13Irq to R13Fiq
sl@0: 	asm("cmpne	r12, #0x12 ");
sl@0: 	asm("addeq	r0, r0, #12 ");			// if valid but not svc/abt/und, add offset from R13Und to R13Irq
sl@0: 	asm("cmpne	r12, #0x1b ");
sl@0: 	asm("addeq	r0, r0, #12 ");			// if valid but not svc/abt, add offset from R13Abt to R13Und
sl@0: 	asm("cmpne	r12, #0x17 ");
sl@0: 	asm("addeq	r0, r0, #12 ");			// if valid but not svc, add offset from R13Svc to R13Abt
sl@0: 	asm("cmpne	r12, #0x13 ");
sl@0: 	asm("addeq	r0, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iN.iR13Svc));	// if valid mode add offset to R13Svc
sl@0: 	asm("movne	r0, #0 ");
sl@0: 	asm("0: ");
sl@0: 	__JUMP(,lr);
sl@0: 	}
sl@0: 
sl@0: 
sl@0: /** Restore all the ARM registers
sl@0: 
sl@0: @internalTechnology
sl@0: */
sl@0: __NAKED__ void Arm::RestoreState(SFullArmRegSet&)
sl@0: 	{
sl@0: 	}
sl@0: 
sl@0: 
sl@0: 
sl@0: 
sl@0: