sl@0: // Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // e32\include\nkernsmp\x86\nk_plat.h sl@0: // sl@0: // WARNING: This file contains some APIs which are internal and are subject sl@0: // to change without notice. Such APIs should therefore not be used sl@0: // outside the Kernel and Hardware Services package. sl@0: // sl@0: sl@0: /** sl@0: @file sl@0: @internalComponent sl@0: */ sl@0: sl@0: #ifndef __NK_X86_H__ sl@0: #define __NK_X86_H__ sl@0: #include sl@0: sl@0: // TSubScheduler member data sl@0: #define i_IrqCount iExtras[9] // count of interrupts handled sl@0: #define i_ExcInfo iExtras[10] // pointer to exception info for crash debugger sl@0: #define i_CrashState iExtras[11] // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted sl@0: #define i_APICID iExtras[12] // Local APIC ID for this CPU (starts at -1) sl@0: #define i_IrqNestCount iExtras[13] // IRQ nest count for this CPU (starts at -1) sl@0: #define i_IrqStackTop iExtras[14] // Top of IRQ stack for this CPU sl@0: #define i_Tss iExtras[15] // Address of TSS for this CPU sl@0: #define i_TimerMultF iExtras[16] // Timer frequency / Max Timer frequency * 2^32 sl@0: #define i_TimerMultI iExtras[17] // Max Timer frequency / Timer frequency * 2^24 sl@0: #define i_CpuMult iExtras[18] // CPU frequency / Max CPU frequency * 2^32 sl@0: #define i_TimestampOffset iExtras[20] // 64 bit value to add to CPU TSC to give NKern::Timestamp() sl@0: #define i_TimestampOffsetL iExtras[20] // sl@0: #define i_TimestampOffsetH iExtras[21] // sl@0: sl@0: // TScheduler member data sl@0: #define i_TimerMax iExtras[16] // Maximum per-CPU timer frequency (after prescaling) sl@0: sl@0: #define CRASH_IPI_VECTOR 0x27 sl@0: #define RESCHED_IPI_VECTOR 0x28 sl@0: #define TIMESLICE_VECTOR 0x29 sl@0: #define GENERIC_IPI_VECTOR 0x2A sl@0: #define TRANSFERRED_IRQ_VECTOR 0x2E sl@0: #define SPURIOUS_INTERRUPT_VECTOR 0x2F sl@0: sl@0: extern "C" TSubScheduler* SubSchedulerLookupTable[256]; // look up subscheduler from APIC ID sl@0: sl@0: #define IRQ_STACK_SIZE 1024 sl@0: sl@0: //#define __SCHEDULER_MACHINE_CODED__ sl@0: //#define __DFC_MACHINE_CODED__ sl@0: //#define __MSTIM_MACHINE_CODED__ sl@0: //#define __PRI_LIST_MACHINE_CODED__ sl@0: //#define __FAST_SEM_MACHINE_CODED__ sl@0: //#define __FAST_MUTEX_MACHINE_CODED__ sl@0: sl@0: class TX86RegSet; sl@0: class NThread : public NThreadBase sl@0: { sl@0: public: sl@0: TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial); sl@0: inline void Stillborn() sl@0: {} sl@0: void GetUserContext(TX86RegSet& aContext, TUint32& aAvailRegMask); sl@0: void SetUserContext(const TX86RegSet& aContext, TUint32& aRegMask); sl@0: void GetSystemContext(TX86RegSet& aContext, TUint32& aAvailRegMask); sl@0: void CompleteContextSave(); sl@0: public: sl@0: TUint64 iCoprocessorState[64]; // state of FPU, SSE, SSE2 sl@0: }; sl@0: sl@0: __ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7)); sl@0: sl@0: sl@0: // Positions of registers on stack, relative to saved SP sl@0: struct SThreadReschedStack sl@0: { sl@0: TUint32 iCR0; sl@0: TUint32 iReschedFlag; sl@0: TUint32 iEip; sl@0: TUint32 iReason; sl@0: }; sl@0: sl@0: // Registers pushed on stack for all exceptions other than slow exec sl@0: struct SThreadExcStack sl@0: { sl@0: TUint32 iEcx; sl@0: TUint32 iEdx; sl@0: TUint32 iEbx; sl@0: TUint32 iEsi; sl@0: TUint32 iEdi; sl@0: TUint32 iEbp; sl@0: TUint32 iEax; sl@0: TUint32 iDs; sl@0: TUint32 iEs; sl@0: TUint32 iFs; sl@0: TUint32 iGs; sl@0: TUint32 iVector; sl@0: TUint32 iError; sl@0: TUint32 iEip; sl@0: TUint32 iCs; sl@0: TUint32 iEflags; sl@0: TUint32 iEsp3; // only if iCs does not indicate CPL=0 sl@0: TUint32 iSs3; // only if iCs does not indicate CPL=0 sl@0: }; sl@0: sl@0: // Registers pushed on stack for slow exec sl@0: struct SThreadSlowExecStack sl@0: { sl@0: TUint32 iEcx; sl@0: TUint32 iEdx; sl@0: TUint32 iEbx; sl@0: TUint32 iEsi; sl@0: TUint32 iEdi; sl@0: TUint32 iEbp; sl@0: TUint32 iEax; sl@0: TUint32 iDs; sl@0: TUint32 iEs; sl@0: TUint32 iFs; sl@0: TUint32 iGs; sl@0: TUint32 iArgs[8]; // space for extra arguments copied from user side sl@0: TUint32 iVector; sl@0: TUint32 iError; sl@0: TUint32 iEip; sl@0: TUint32 iCs; sl@0: TUint32 iEflags; sl@0: TUint32 iEsp3; // only if iCs does not indicate CPL=0 sl@0: TUint32 iSs3; // only if iCs does not indicate CPL=0 sl@0: }; sl@0: sl@0: // Top of stack after thread creation for threads with parameter block passed sl@0: // by value. sl@0: struct SThreadStackStub sl@0: { sl@0: enum {EVector=0xffffffffu}; sl@0: TLinAddr iPBlock; // pointer to parameter block sl@0: TUint32 iVector; sl@0: TUint32 iError; sl@0: TUint32 iEip; sl@0: TUint32 iCs; sl@0: TUint32 iEflags; sl@0: }; sl@0: sl@0: // Stack structure at thread creation either at top of stack (if parameter block sl@0: // passed by reference) or below parameter block if passed by value. sl@0: struct SThreadInitStack sl@0: { sl@0: enum {EVector=0xfffffffeu}; sl@0: SThreadReschedStack iR; sl@0: SThreadExcStack iX; sl@0: }; sl@0: sl@0: sl@0: extern "C" { sl@0: GLREF_D TLinAddr X86_IrqHandler; sl@0: GLREF_D SCpuIdleHandler CpuIdleHandler; sl@0: GLREF_D TUint32 X86_CPUID; sl@0: GLREF_D TBool X86_UseGlobalPTEs; sl@0: GLREF_D TUint64 DefaultCoprocessorState[64]; sl@0: } sl@0: sl@0: /** Ensure the ordering of explicit memory writes sl@0: sl@0: On x86 this is a no-op sl@0: */ sl@0: #define wmb() sl@0: #define smp_wmb() wmb() sl@0: sl@0: /** Ensure the ordering of explicit memory accesses sl@0: sl@0: On x86 any instruction with the LOCK prefix does this sl@0: */ sl@0: #ifdef __GCC32__ sl@0: #define mb() __asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory") sl@0: #else sl@0: #define mb() do { _asm lock add dword ptr [esp], 0 } while (0) sl@0: #endif sl@0: #define smp_mb() mb() sl@0: sl@0: sl@0: sl@0: // End of file sl@0: #endif