sl@0: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // e32\include\nkernsmp\arm\arm_scu.h sl@0: // Register definitions for ARM Snoop Control Unit sl@0: // sl@0: // WARNING: This file contains some APIs which are internal and are subject sl@0: // to change without notice. Such APIs should therefore not be used sl@0: // outside the Kernel and Hardware Services package. sl@0: // sl@0: sl@0: #ifndef __ARM_SCU_H__ sl@0: #define __ARM_SCU_H__ sl@0: #include sl@0: sl@0: #ifdef __STANDALONE_NANOKERNEL__ sl@0: #undef __IN_KERNEL__ sl@0: #define __IN_KERNEL__ sl@0: #endif sl@0: sl@0: #if defined(__CPU_ARM11MP__) sl@0: struct ArmScu sl@0: { sl@0: volatile TUint32 iCtrl; // 00 Control register sl@0: volatile TUint32 iConfig; // 04 Configuration register (RO) sl@0: volatile TUint32 iCpuStatus; // 08 SCU CPU Status register sl@0: volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO) sl@0: volatile TUint32 iPMCtrl; // 10 Performance Monitor Control register sl@0: volatile TUint32 iMonitorEvents0; // 14 Monitor Counter Events 0 sl@0: volatile TUint32 iMonitorEvents1; // 18 Monitor Counter Events 1 sl@0: volatile TUint32 iMonitorCount0; // 1C Monitor Counter 0 sl@0: volatile TUint32 iMonitorCount1; // 20 Monitor Counter 1 sl@0: volatile TUint32 iMonitorCount2; // 24 Monitor Counter 2 sl@0: volatile TUint32 iMonitorCount3; // 28 Monitor Counter 3 sl@0: volatile TUint32 iMonitorCount4; // 2C Monitor Counter 4 sl@0: volatile TUint32 iMonitorCount5; // 30 Monitor Counter 5 sl@0: volatile TUint32 iMonitorCount6; // 34 Monitor Counter 6 sl@0: volatile TUint32 iMonitorCount7; // 38 Monitor Counter 7 sl@0: volatile TUint32 i_Skip_1[49]; // 3C unused sl@0: }; sl@0: sl@0: __ASSERT_COMPILE(sizeof(ArmScu)==0x100); sl@0: sl@0: enum TArmScuCtrl sl@0: { sl@0: E_ArmScuCtrl_Enable =1u, // SCU Enable sl@0: E_ArmScuCtrl_AccessShift =1u, sl@0: E_ArmScuCtrl_AccessMask =0x1eu, // bits 1-4 = SCU access control for CPU0-3 sl@0: E_ArmScuCtrl_IIAliasShift =5u, sl@0: E_ArmScuCtrl_IIAliasMask =0x1e0u, // bits 5-8 = Interrupt Interface Alias enable for CPU0-3 sl@0: E_ArmScuCtrl_PIAliasShift =9u, sl@0: E_ArmScuCtrl_PIAliasMask =0x1e00u, // bits 9-12 = Peripheral Interface Alias enable for CPU0-3 sl@0: }; sl@0: sl@0: enum TArmScuPMCR sl@0: { sl@0: E_ArmScuPMCR_Enable =1u, // 0=all counters disabled sl@0: E_ArmScuPMCR_ResetAll =2u, // write 1 resets all counters sl@0: E_ArmScuPMCR_IntEn0 =0x100u, // Interrupt Enable for MN0 sl@0: E_ArmScuPMCR_IntEn1 =0x200u, // Interrupt Enable for MN1 sl@0: E_ArmScuPMCR_IntEn2 =0x400u, // Interrupt Enable for MN2 sl@0: E_ArmScuPMCR_IntEn3 =0x800u, // Interrupt Enable for MN3 sl@0: E_ArmScuPMCR_IntEn4 =0x1000u, // Interrupt Enable for MN4 sl@0: E_ArmScuPMCR_IntEn5 =0x2000u, // Interrupt Enable for MN5 sl@0: E_ArmScuPMCR_IntEn6 =0x4000u, // Interrupt Enable for MN6 sl@0: E_ArmScuPMCR_IntEn7 =0x8000u, // Interrupt Enable for MN7 sl@0: E_ArmScuPMCR_Ovfw0 =0x10000u, // Overflow Flag for MN0 (write 1 to clear) sl@0: E_ArmScuPMCR_Ovfw1 =0x20000u, // Overflow Flag for MN1 sl@0: E_ArmScuPMCR_Ovfw2 =0x40000u, // Overflow Flag for MN2 sl@0: E_ArmScuPMCR_Ovfw3 =0x80000u, // Overflow Flag for MN3 sl@0: E_ArmScuPMCR_Ovfw4 =0x100000u, // Overflow Flag for MN4 sl@0: E_ArmScuPMCR_Ovfw5 =0x200000u, // Overflow Flag for MN5 sl@0: E_ArmScuPMCR_Ovfw6 =0x400000u, // Overflow Flag for MN6 sl@0: E_ArmScuPMCR_Ovfw7 =0x800000u, // Overflow Flag for MN7 sl@0: }; sl@0: sl@0: sl@0: #elif defined(__CPU_CORTEX_A9__) sl@0: struct ArmScu sl@0: { sl@0: volatile TUint32 iCtrl; // 00 Control register sl@0: volatile TUint32 iConfig; // 04 Configuration register (RO) sl@0: volatile TUint32 iCpuStatus; // 08 SCU CPU Power Status register sl@0: volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO) sl@0: volatile TUint32 i_Skip_1[12]; // 10-3F unused sl@0: volatile TUint32 i_FSAR; // 40 Filtering Start Address Register sl@0: volatile TUint32 i_FEAR; // 44 Filtering End Address Register sl@0: volatile TUint32 i_Skip_2[2]; // 48-4F unused sl@0: volatile TUint32 i_SAC; // 50 SCU Access Control Register sl@0: volatile TUint32 i_SSAC; // 54 SCU Secure Access Control Register sl@0: volatile TUint32 i_Skip_3[42]; // 58-FF unused sl@0: }; sl@0: sl@0: __ASSERT_COMPILE(sizeof(ArmScu)==0x100); sl@0: sl@0: enum TArmScuCtrl sl@0: { sl@0: E_ArmScuCtrl_Enable =1u, // SCU Enable sl@0: E_ArmScuCtrl_AFEnable =2u, // SCU Address Filtering Enable sl@0: E_ArmScuCtrl_ParityEnable =4u, // SCU Parity Enable sl@0: }; sl@0: sl@0: enum TArmScuSAC sl@0: { sl@0: E_ArmScuSAC_CPU0 =1u, // If set, CPU0 can access SCU registers sl@0: E_ArmScuSAC_CPU1 =2u, // If set, CPU1 can access SCU registers sl@0: E_ArmScuSAC_CPU2 =4u, // If set, CPU2 can access SCU registers sl@0: E_ArmScuSAC_CPU3 =8u, // If set, CPU3 can access SCU registers sl@0: }; sl@0: sl@0: enum TArmScuSSAC sl@0: { sl@0: E_ArmScuSSAC_CPU0 =1u, // If set, CPU0 can access SCU registers in nonsecure state sl@0: E_ArmScuSSAC_CPU1 =2u, // If set, CPU1 can access SCU registers in nonsecure state sl@0: E_ArmScuSSAC_CPU2 =4u, // If set, CPU2 can access SCU registers in nonsecure state sl@0: E_ArmScuSSAC_CPU3 =8u, // If set, CPU3 can access SCU registers in nonsecure state sl@0: E_ArmScuSSAC_Timer0 =16u, // If set, CPU0 private timer is accessible in nonsecure state sl@0: E_ArmScuSSAC_Timer1 =32u, // If set, CPU1 private timer is accessible in nonsecure state sl@0: E_ArmScuSSAC_Timer2 =64u, // If set, CPU2 private timer is accessible in nonsecure state sl@0: E_ArmScuSSAC_Timer3 =128u, // If set, CPU3 private timer is accessible in nonsecure state sl@0: }; sl@0: sl@0: #else sl@0: #error Unknown SCU sl@0: #endif sl@0: sl@0: enum TArmScuConfig sl@0: { sl@0: E_ArmScuCfg_NCpusMask =3u, // bits0,1 = number of CPUs - 1 sl@0: E_ArmScuCfg_CpuSMPShift =4u, sl@0: E_ArmScuCfg_CpuSMPMask =0xf0u, // bits4-7 = CPU0-3 SMP mode indicator sl@0: E_ArmScuCfg_TagShift =8u, sl@0: E_ArmScuCfg_TagMask =0xff00u, // two bits per CPU, tag RAM size = 16KB<