sl@0: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // e32\include\nkernsmp\arm\arm_gic.h sl@0: // Register definitions for ARM Generic Interrupt Controller sl@0: // sl@0: // WARNING: This file contains some APIs which are internal and are subject sl@0: // to change without notice. Such APIs should therefore not be used sl@0: // outside the Kernel and Hardware Services package. sl@0: // sl@0: sl@0: #ifndef __ARM_GIC_H__ sl@0: #define __ARM_GIC_H__ sl@0: #include sl@0: sl@0: #ifdef __STANDALONE_NANOKERNEL__ sl@0: #undef __IN_KERNEL__ sl@0: #define __IN_KERNEL__ sl@0: #endif sl@0: sl@0: enum TGicIntId sl@0: { sl@0: E_GicIntId_Soft0 =0, // IDs 0-15 are for software triggered IPIs sl@0: E_GicIntId_Soft1 =1, sl@0: E_GicIntId_Soft2 =2, sl@0: E_GicIntId_Soft3 =3, sl@0: E_GicIntId_Soft4 =4, sl@0: E_GicIntId_Soft5 =5, sl@0: E_GicIntId_Soft6 =6, sl@0: E_GicIntId_Soft7 =7, sl@0: E_GicIntId_Soft8 =8, sl@0: E_GicIntId_Soft9 =9, sl@0: E_GicIntId_Soft10 =10, sl@0: E_GicIntId_Soft11 =11, sl@0: E_GicIntId_Soft12 =12, sl@0: E_GicIntId_Soft13 =13, sl@0: E_GicIntId_Soft14 =14, sl@0: E_GicIntId_Soft15 =15, sl@0: sl@0: E_GicIntId_Private0 =16, // IDs 16-31 are for private peripherals sl@0: E_GicIntId_Private1 =17, sl@0: E_GicIntId_Private2 =18, sl@0: E_GicIntId_Private3 =19, sl@0: E_GicIntId_Private4 =20, sl@0: E_GicIntId_Private5 =21, sl@0: E_GicIntId_Private6 =22, sl@0: E_GicIntId_Private7 =23, sl@0: E_GicIntId_Private8 =24, sl@0: E_GicIntId_Private9 =25, sl@0: E_GicIntId_Private10 =26, sl@0: E_GicIntId_Private11 =27, sl@0: E_GicIntId_Private12 =28, sl@0: E_GicIntId_Private13 =29, sl@0: E_GicIntId_Private14 =30, sl@0: E_GicIntId_Private15 =31, sl@0: sl@0: E_GicIntId_Normal0 =32, // first normal interrupt ID sl@0: sl@0: E_GicIntId_NormalLast =1019, // last possible normal interrupt ID sl@0: E_GicIntId_Reserved0 =1020, // reserved interrupt ID sl@0: E_GicIntId_Reserved1 =1021, // reserved interrupt ID sl@0: E_GicIntId_NS =1022, // only nonsecure interrupts are serviceable sl@0: E_GicIntId_Spurious =1023 // no interrupts are serviceable sl@0: }; sl@0: sl@0: struct GicDistributor sl@0: { sl@0: volatile TUint32 iCtrl; // 000 Control register sl@0: volatile TUint32 iType; // 004 Type register sl@0: volatile TUint32 iImpId; // 008 Implementor Identification register (not on MPCore) sl@0: volatile TUint32 i_Skip_1[29]; // 00C unused sl@0: volatile TUint32 iIntSec[32]; // 080 Interrupt Security register (not on MPCore) (1 bit per interrupt) sl@0: volatile TUint32 iEnableSet[32]; // 100 Enable set register (1 bit per interrupt) sl@0: volatile TUint32 iEnableClear[32]; // 180 Enable clear register (1 bit per interrupt) sl@0: volatile TUint32 iPendingSet[32]; // 200 Pending set register (1 bit per interrupt) sl@0: volatile TUint32 iPendingClear[32]; // 280 Pending clear register (1 bit per interrupt) sl@0: volatile TUint32 iActive[32]; // 300 Active status register (1 bit per interrupt) sl@0: volatile TUint32 i_Skip_2[32]; // 380 unused sl@0: volatile TUint32 iPriority[256]; // 400 Interrupt priority register (8 bits per interrupt) sl@0: volatile TUint32 iTarget[256]; // 800 Interrupt target CPUs register (8 bits per interrupt) sl@0: volatile TUint32 iConfig[64]; // C00 Interrupt configuration register (2 bits per interrupt) sl@0: volatile TUint32 iImpDef[64]; // D00 Implementation defined registers sl@0: // = Interrupt line level on MPCore sl@0: volatile TUint32 i_Skip_3[64]; // E00 unused sl@0: volatile TUint32 iSoftIrq; // F00 Software triggered interrupt register sl@0: volatile TUint32 i_Skip_4[51]; // F04 unused sl@0: volatile TUint32 iIdent[12]; // FD0 Identification registers sl@0: }; sl@0: sl@0: __ASSERT_COMPILE(sizeof(GicDistributor)==0x1000); sl@0: sl@0: struct GicCpuIfc sl@0: { sl@0: volatile TUint32 iCtrl; // 00 Control register sl@0: volatile TUint32 iPriMask; // 04 Priority mask register sl@0: volatile TUint32 iBinaryPoint; // 08 Binary point register sl@0: volatile TUint32 iAck; // 0C Interrupt acknowledge register sl@0: volatile TUint32 iEoi; // 10 End of interrupt register sl@0: volatile TUint32 iRunningPri; // 14 Running priority register sl@0: volatile TUint32 iHighestPending; // 18 Highest pending interrupt register sl@0: volatile TUint32 iNSBinaryPoint; // 1C Aliased nonsecure binary point register (not on MPCore) sl@0: volatile TUint32 i_Skip_1[8]; // 20 unused sl@0: volatile TUint32 iImpDef[36]; // 40 Implementation defined (not present on MPCore) sl@0: volatile TUint32 i_Skip_2[11]; // D0 unused sl@0: volatile TUint32 iImpId; // FC Implementor Identification register (not on MPCore) sl@0: }; sl@0: sl@0: __ASSERT_COMPILE(sizeof(GicCpuIfc)==0x100); sl@0: sl@0: enum TGicDistCtrl sl@0: { sl@0: E_GicDistCtrl_Enable =1, // Enable interrupt distributor sl@0: }; sl@0: sl@0: enum TGicDistType sl@0: { sl@0: E_GicDistType_ITShift =0u, // bits 0-4 = number of sets of 32 interrupts supported sl@0: E_GicDistType_ITMask =0x1fu, sl@0: E_GicDistType_CPUNShift =5u, // bits 5-7 = number of CPUs supported - 1 sl@0: E_GicDistType_CPUNMask =0xe0u, sl@0: E_GicDistType_Domains =0x400u, // set if two security domains supported sl@0: E_GicDistType_LSPIShift =11u, // bits 11-15 = number of lockable shared peripheral interrupts sl@0: E_GicDistType_LSPIMask =0xf800u, sl@0: }; sl@0: sl@0: enum TGicDistIntConfig sl@0: { sl@0: E_GicDistICfg1N =1u, // if set use 1-N model else use N-N model sl@0: // peripheral interrupts support only 1-N model, s/w interrupts N-N sl@0: // 1-N means the interrupt is cleared by the first CPU to accept it sl@0: E_GicDistICfgEdge =2u, // if set, rising edge triggered, else active high level triggered sl@0: }; sl@0: sl@0: enum TGicDistSoftIrqDestType sl@0: { sl@0: E_GicDestTypeList =0u, // send to all CPUs in list (bit mask) sl@0: E_GicDestTypeOthers =1u, // send to all CPUs other than self sl@0: E_GicDestTypeSelf =2u, // send to self only sl@0: E_GicDestTypeRsvd =3u sl@0: }; sl@0: sl@0: // Compile word to generate IPI sl@0: // dt = destination type, dl = bit mask of destination CPUs, id = interrupt ID (0-15) sl@0: #define GIC_SOFT_IRQ_WORD(dt,dl,id) ((TUint32(dt)<<24)|(TUint32(dl)<<16)|(TUint32(id))) sl@0: sl@0: #define GIC_IPI_SELF(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeSelf, 0, id) sl@0: #define GIC_IPI_OTHERS(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeOthers, 0, id) sl@0: #define GIC_IPI(dl,id) GIC_SOFT_IRQ_WORD(E_GicDestTypeList, dl, id) sl@0: sl@0: sl@0: #endif // __ARM_GIC_H__