sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\include\nkern\arm\nk_plat.h
sl@0: // 
sl@0: // WARNING: This file contains some APIs which are internal and are subject
sl@0: //          to change without notice. Such APIs should therefore not be used
sl@0: //          outside the Kernel and Hardware Services package.
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @internalComponent
sl@0: */
sl@0: 
sl@0: #ifndef __NK_ARM_H__
sl@0: #define __NK_ARM_H__
sl@0: #include <nk_cpu.h>
sl@0: 
sl@0: // These macros are intended for Symbian use only.
sl@0: // It may not be possible to build the kernel if any of these macros are undefined
sl@0: #define __SCHEDULER_MACHINE_CODED__
sl@0: #define __DFC_MACHINE_CODED__
sl@0: #define __MSTIM_MACHINE_CODED__
sl@0: #define __PRI_LIST_MACHINE_CODED__
sl@0: #define __FAST_SEM_MACHINE_CODED__
sl@0: #define __FAST_MUTEX_MACHINE_CODED__
sl@0: #define __USER_CONTEXT_TYPE_MACHINE_CODED__
sl@0: #define __CLIENT_REQUEST_MACHINE_CODED__
sl@0: 
sl@0: // TScheduler member data
sl@0: #define	i_Regs				iExtras[14]
sl@0: #define	i_ExcInfo			iExtras[15]		// pointer to exception info for crash debugger
sl@0: 
sl@0: const TUint32 KNThreadContextFlagThumbBit0=1;
sl@0: 
sl@0: #ifdef __CPU_ARM_USE_DOMAINS
sl@0: #define DOMAIN_STACK_SPACE	4
sl@0: #else
sl@0: #define DOMAIN_STACK_SPACE	0
sl@0: #endif
sl@0: #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
sl@0: #define CAR_STACK_SPACE	4
sl@0: #else
sl@0: #define CAR_STACK_SPACE	0
sl@0: #endif
sl@0: #ifdef __CPU_HAS_VFP
sl@0: #define VFP_STACK_SPACE	4
sl@0: #else
sl@0: #define VFP_STACK_SPACE	0
sl@0: #endif
sl@0: #ifdef __CPU_HAS_CP15_THREAD_ID_REG
sl@0: #define TID_STACK_SPACE	4
sl@0: #else 
sl@0: #define TID_STACK_SPACE	0
sl@0: #endif 
sl@0: #ifdef __CPU_SUPPORT_THUMB2EE
sl@0: #define THUMB2EE_STACK_SPACE 4
sl@0: #else
sl@0: #define THUMB2EE_STACK_SPACE 0
sl@0: #endif
sl@0: 
sl@0: #define EXTRA_STACK_SPACE	(DOMAIN_STACK_SPACE+CAR_STACK_SPACE+VFP_STACK_SPACE+TID_STACK_SPACE+THUMB2EE_STACK_SPACE)
sl@0: 
sl@0: #ifdef __INCLUDE_REG_OFFSETS__
sl@0: // Positions of registers on stack, relative to saved SP
sl@0: #define EXTRA_WORDS	(EXTRA_STACK_SPACE/4)
sl@0: 
sl@0: #ifdef __CPU_HAS_VFP
sl@0: #define SP_FPEXC	((THUMB2EE_STACK_SPACE+TID_STACK_SPACE)/4)
sl@0: #endif
sl@0: #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
sl@0: #define	SP_CAR		((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE)/4)
sl@0: #endif
sl@0: #ifdef __CPU_ARM_USE_DOMAINS
sl@0: #define SP_DACR		((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE+CAR_STACK_SPACE)/4)
sl@0: #endif
sl@0: 
sl@0: #define	SP_R13U		EXTRA_WORDS
sl@0: #define	SP_R14U		(SP_R13U+1)
sl@0: #define	SP_SPSR		(SP_R13U+2)
sl@0: #define	SP_R4		(SP_R13U+3)
sl@0: #define	SP_R5		(SP_R13U+4)
sl@0: #define	SP_R6		(SP_R13U+5)
sl@0: #define	SP_R7		(SP_R13U+6)
sl@0: #define	SP_R8		(SP_R13U+7)
sl@0: #define	SP_R9		(SP_R13U+8)
sl@0: #define	SP_R10		(SP_R13U+9)
sl@0: #define	SP_R11		(SP_R13U+10)
sl@0: #define	SP_PC		(SP_R13U+11)
sl@0: 
sl@0: #define SP_NEXT		(SP_PC+1)		// first word on stack before reschedule
sl@0: #endif	// __INCLUDE_REG_OFFSETS__
sl@0: 
sl@0: class TArmContextElement;
sl@0: class TArmRegSet;
sl@0: 
sl@0: /** ARM-specific part of the nano-thread abstraction.
sl@0: 	@internalComponent
sl@0:  */
sl@0: class NThread : public NThreadBase
sl@0: 	{
sl@0: public:
sl@0: 	TInt Create(SNThreadCreateInfo& aInfo, TBool aInitial);
sl@0: 	inline void Stillborn()
sl@0: 		{}
sl@0: 
sl@0: 	/** Value indicating what event caused thread to enter privileged mode.
sl@0: 		@publishedPartner
sl@0: 		@released
sl@0: 	 */
sl@0: 	enum TUserContextType
sl@0: 		{
sl@0: 		EContextNone=0,             /**< Thread has no user context */
sl@0: 		EContextException=1,		/**< Hardware exception while in user mode */
sl@0: 		EContextUndefined,			
sl@0: 		EContextUserInterrupt,		/**< Preempted by interrupt taken in user mode */
sl@0: 		EContextUserInterruptDied,  /**< Killed while preempted by interrupt taken in user mode */
sl@0: 		EContextSvsrInterrupt1,     /**< Preempted by interrupt taken in executive call handler */
sl@0: 		EContextSvsrInterrupt1Died, /**< Killed while preempted by interrupt taken in executive call handler */
sl@0: 		EContextSvsrInterrupt2,     /**< Preempted by interrupt taken in executive call handler */
sl@0: 		EContextSvsrInterrupt2Died, /**< Killed while preempted by interrupt taken in executive call handler */
sl@0: 		EContextWFAR,               /**< Blocked on User::WaitForAnyRequest() */
sl@0: 		EContextWFARDied,           /**< Killed while blocked on User::WaitForAnyRequest() */
sl@0: 		EContextExec,				/**< Slow executive call */
sl@0: 		EContextKernel,				/**< Kernel side context (for kernel threads) */
sl@0: 		EContextUserIntrCallback,	/**< Blocked/preempted in a user callback on the way back from interrupt */
sl@0: 		EContextWFARCallback,		/**< Blocked/preempted in a user callback on the way back from User::WFAR */
sl@0: 		};
sl@0: 
sl@0: 	IMPORT_C static const TArmContextElement* const* UserContextTables();
sl@0: 	IMPORT_C TUserContextType UserContextType();
sl@0: 	inline TInt SetUserContextType()
sl@0: 		{ return iSpare3=UserContextType(); }
sl@0: 	inline void ResetUserContextType()
sl@0: 		{ if(iSpare3>EContextUndefined && iSpare3<EContextUserIntrCallback) iSpare3=EContextUndefined; }
sl@0: 	void GetContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask, const TArmContextElement* aContextTable);
sl@0: 	void GetUserContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask);
sl@0: 	void SetUserContext(const TArmRegSet& aContext);
sl@0: 	void GetSystemContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask);
sl@0: 
sl@0: 	void ModifyUsp(TLinAddr aUsp);
sl@0: 
sl@0: #ifdef __CPU_ARM_USE_DOMAINS
sl@0: 	TUint32 Dacr();
sl@0: 	void SetDacr(TUint32 aDacr);
sl@0: 	TUint32 ModifyDacr(TUint32 aClearMask, TUint32 aSetMask);
sl@0: #endif
sl@0: 
sl@0: #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
sl@0: 	void SetCar(TUint32 aDacr);
sl@0: #endif
sl@0: 	IMPORT_C TUint32 Car();
sl@0: 	IMPORT_C TUint32 ModifyCar(TUint32 aClearMask, TUint32 aSetMask);
sl@0: 
sl@0: #ifdef __CPU_HAS_VFP
sl@0: 	void SetFpExc(TUint32 aDacr);
sl@0: #endif
sl@0: 	IMPORT_C TUint32 FpExc();
sl@0: 	IMPORT_C TUint32 ModifyFpExc(TUint32 aClearMask, TUint32 aSetMask);
sl@0: 	};
sl@0: 
sl@0: 
sl@0: struct SArmInterruptInfo
sl@0: 	{
sl@0: 	TLinAddr iIrqHandler;
sl@0: 	TLinAddr iFiqHandler;
sl@0: 	TUint8	 iCpuUsageFilter;
sl@0: 	BTrace::THandler iBTraceHandler;
sl@0: 	SCpuIdleHandler iCpuIdleHandler;
sl@0: 	};
sl@0: 
sl@0: extern "C" SArmInterruptInfo ArmInterruptInfo;
sl@0: 
sl@0: #endif