sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // e32\include\memmodel\epoc\plat_priv.h sl@0: // sl@0: // WARNING: This file contains some APIs which are internal and are subject sl@0: // to change without notice. Such APIs should therefore not be used sl@0: // outside the Kernel and Hardware Services package. sl@0: // sl@0: sl@0: #ifndef __M32KERN_H__ sl@0: #define __M32KERN_H__ sl@0: #include sl@0: #include sl@0: #include sl@0: sl@0: /** Hardware Variant Discriminator sl@0: sl@0: @internalTechnology sl@0: */ sl@0: class THardwareVariant sl@0: { sl@0: public: sl@0: inline THardwareVariant(); sl@0: inline THardwareVariant(TUint aVariant); sl@0: inline operator TUint(); sl@0: inline TBool IsIndependent(); sl@0: inline TBool IsCpu(); sl@0: inline TBool IsCompatibleWith(TUint aCpu, TUint aAsic, TUint aVMask); sl@0: private: sl@0: inline TUint Layer(); sl@0: inline TUint Parent(); sl@0: inline TUint VMask(); sl@0: private: sl@0: TUint iVariant; sl@0: }; sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline THardwareVariant::THardwareVariant() sl@0: {iVariant=0x01000000;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline THardwareVariant::THardwareVariant(TUint aVariant) sl@0: {iVariant=aVariant;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline THardwareVariant::operator TUint() sl@0: {return iVariant;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TUint THardwareVariant::Layer() sl@0: {return iVariant>>24;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TUint THardwareVariant::Parent() sl@0: {return (iVariant>>16)&0xff;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TUint THardwareVariant::VMask() sl@0: {return iVariant&0xffff;} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TBool THardwareVariant::IsIndependent() sl@0: {return (Layer()<=3);} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TBool THardwareVariant::IsCpu() sl@0: {return (Parent()==3);} sl@0: sl@0: /** sl@0: @internalTechnology sl@0: */ sl@0: inline TBool THardwareVariant::IsCompatibleWith(TUint aCpu, TUint aAsic, TUint aVMask) sl@0: { return(Layer()<=3 || (Parent()==3 && Layer()==aCpu) || sl@0: (Layer()==aAsic && (VMask() & aVMask)!=0) );} sl@0: sl@0: sl@0: /** Functions/Data defined in layer 2 or below of the kernel and not available to layer 1. sl@0: sl@0: @internalComponent sl@0: */ sl@0: class PP sl@0: { sl@0: public: sl@0: enum TPlatPanic sl@0: { sl@0: EInitialSystemTimeInvalid=0, sl@0: EInvalidStartupReason=1, sl@0: EIncorrectDllDataAddress=2, sl@0: ENoDllDataChunk=3, sl@0: EUnsupportedOldBinary=4, sl@0: }; sl@0: sl@0: static void Panic(TPlatPanic aPanic); sl@0: static void InitSuperPageFromRom(TLinAddr aRomHeader, TLinAddr aSuperPage); sl@0: public: sl@0: static TInt RamDriveMaxSize; sl@0: static TInt RamDriveRange; sl@0: static TUint32 NanoWaitCal; sl@0: static DChunk* TheRamDriveChunk; sl@0: static TLinAddr RamDriveStartAddress; sl@0: static TInt MaxUserThreadStack; sl@0: static TInt UserThreadStackGuard; sl@0: static TInt MaxStackSpacePerProcess; sl@0: static TInt SupervisorThreadStackGuard; sl@0: static TUint32 MonitorEntryPoint[3]; sl@0: static TLinAddr RomRootDirAddress; sl@0: public: sl@0: }; sl@0: sl@0: extern "C" { sl@0: extern TLinAddr RomHeaderAddress; sl@0: } sl@0: sl@0: /******************************************** sl@0: * Code segment sl@0: ********************************************/ sl@0: sl@0: /** sl@0: @internalComponent sl@0: */ sl@0: struct SRamCodeInfo sl@0: { sl@0: TInt iCodeSize; sl@0: TInt iTextSize; sl@0: TLinAddr iCodeRunAddr; sl@0: TLinAddr iCodeLoadAddr; sl@0: TInt iDataSize; sl@0: TInt iBssSize; sl@0: TLinAddr iDataRunAddr; sl@0: TLinAddr iDataLoadAddr; sl@0: TInt iConstOffset; // not used sl@0: TLinAddr iExportDir; sl@0: TInt iExportDirCount; sl@0: TLinAddr iExceptionDescriptor; sl@0: }; sl@0: sl@0: sl@0: class DEpocCodeSeg; sl@0: sl@0: /** sl@0: @internalComponent sl@0: */ sl@0: class DEpocCodeSegMemory : public DBase sl@0: { sl@0: public: sl@0: static DEpocCodeSegMemory* New(DEpocCodeSeg* aCodeSeg); sl@0: TInt Open(); sl@0: TInt Close(); sl@0: protected: sl@0: DEpocCodeSegMemory(DEpocCodeSeg* aCodeSeg); sl@0: public: sl@0: TInt iAccessCount; sl@0: SRamCodeInfo iRamInfo; sl@0: DEpocCodeSeg* iCodeSeg; sl@0: }; sl@0: sl@0: sl@0: /** sl@0: @internalComponent sl@0: */ sl@0: class DEpocCodeSeg : public DCodeSeg sl@0: { sl@0: public: sl@0: virtual ~DEpocCodeSeg(); sl@0: void Destruct(); sl@0: public: sl@0: virtual void Info(TCodeSegCreateInfo& aInfo); sl@0: virtual TLibraryFunction Lookup(TInt aOrdinal); sl@0: virtual TInt GetMemoryInfo(TModuleMemoryInfo& aInfo, DProcess* aProcess); sl@0: virtual TInt DoCreate(TCodeSegCreateInfo& aInfo, DProcess* aProcess); sl@0: virtual void InitData(); sl@0: virtual TInt Loaded(TCodeSegCreateInfo& aInfo); sl@0: virtual TInt DoCreateRam(TCodeSegCreateInfo& aInfo, DProcess* aProcess)=0; sl@0: virtual TInt DoCreateXIP(DProcess* aProcess)=0; sl@0: public: sl@0: inline SRamCodeInfo& RamInfo() sl@0: {return *(SRamCodeInfo*)iInfo;} sl@0: inline const TRomImageHeader& RomInfo() sl@0: {return *(const TRomImageHeader*)iInfo;} sl@0: void GetDataSizeAndBase(TInt& aTotalDataSizeOut, TLinAddr& aDataBaseOut); sl@0: public: sl@0: TUint8 iXIP; // TRUE for XIP ROM code sl@0: const TAny* iInfo; // pointer to TRomImageHeader or SRamCodeInfo sl@0: DEpocCodeSegMemory* iMemory; sl@0: TCodeSegLoaderCookieList* iLoaderCookie; sl@0: }; sl@0: sl@0: /******************************************** sl@0: * Process control block sl@0: ********************************************/ sl@0: sl@0: /** sl@0: @internalComponent sl@0: */ sl@0: class DEpocProcess : public DProcess sl@0: { sl@0: public: sl@0: virtual TInt AttachExistingCodeSeg(TProcessCreateInfo& aInfo); sl@0: }; sl@0: sl@0: /** sl@0: @internalComponent sl@0: */ sl@0: inline const TRomHeader& TheRomHeader() sl@0: {return *((const TRomHeader *)RomHeaderAddress);} sl@0: sl@0: #endif