sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: // e32\include\memmodel\epoc\moving\arm\mmboot.h
sl@0: // 
sl@0: // WARNING: This file contains some APIs which are internal and are subject
sl@0: //          to change without notice. Such APIs should therefore not be used
sl@0: //          outside the Kernel and Hardware Services package.
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @publishedPartner
sl@0:  @released
sl@0: */
sl@0: 
sl@0: #ifndef __MMBOOT_H__
sl@0: #define __MMBOOT_H__
sl@0: #include <arm.h>
sl@0: #include <memmodel.h>
sl@0: #include <kernel/cache.h>
sl@0: 
sl@0: //
sl@0: // Linear address map:
sl@0: // 00000000-003FFFFF	Unmapped
sl@0: // 00400000-2FFFFFFF	Moving process data
sl@0: // 30000000-3FFFFFFF	DLL static data (=phys ram size/2 up to 128M, always ends at 40000000)
sl@0: // 40000000-5FFFFFFF	RAM drive
sl@0: // 60000000-60001FFF	Super page/CPU page
sl@0: // 60030000-600303FF	KPageInfoMap
sl@0: // 60038000-6003FFFF	IRQ, FIQ, UND, ABT stacks (4*4K for stacks + 4*4K for guard pages) 
sl@0: // 61000000-61003FFF	Page directory (16K)
sl@0: // 61020000-6103FFFF	Page table info (4096 * 8bytes = 32K)
sl@0: // 61100000-611FFFFF	Cache flush area
sl@0: // 61200000-612FFFFF	Alternate cache flush area
sl@0: // 62000000-623FFFFF	Page tables (up to 4096 * 1K)
sl@0: // 63000000-63FFFFFF	Primary I/O mappings
sl@0: // 64000000-64FFFFFF	Kernel .data/.bss, initial stack, kernel heap
sl@0: // 65000000-655FFFFF	fixed processes - usually 2 or 3Mb each.
sl@0: // 65600000-F1FFFFFF	Kernel section (includes extra I/O mappings)
sl@0: // F0000000-F1FFFFFF	Kernel code (RAM size/2)
sl@0: // F2000000-F5FFFFFF	User code (RAM size)
sl@0: // F6000000-F7FFFFFF	Page Info array
sl@0: // F8000000-FFEFFFFF	ROM
sl@0: // FFF00000-FFFFFFFF	Exception vectors
sl@0: //
sl@0: 
sl@0: // Linear addresses
sl@0: const TLinAddr	KDataSectionBase		=0x00400000u;
sl@0: const TLinAddr	KDataSectionEnd			=0x40000000u;
sl@0: const TLinAddr	KRamDriveStartAddress	=0x40000000u;
sl@0: const TInt		KRamDriveMaxSize		=0x20000000;
sl@0: const TLinAddr	KRamDriveEndAddress		=0x60000000u;
sl@0: 
sl@0: const TLinAddr	KPageInfoLinearBase		=0xF6000000u;
sl@0: 
sl@0: const TLinAddr	KRomLinearBase			=0xF8000000u;
sl@0: const TLinAddr	KRomLinearEnd			=0xFFF00000u;
sl@0: const TLinAddr	KSuperPageLinAddr		=0x60000000u;
sl@0: const TLinAddr  KExcptStacksLinearBase	=0x60038000u;
sl@0: const TLinAddr	KPageDirectoryBase		=0x61000000u;
sl@0: const TLinAddr	KPageTableInfoBase		=0x61020000u;
sl@0: const TLinAddr	KPageTableBase			=0x62000000u;
sl@0: const TLinAddr	KPrimaryIOBase			=0x63000000u;
sl@0: const TLinAddr  KKernelDataBase			=0x64000000u;
sl@0: const TLinAddr  KKernelDataEnd			=0x65000000u;
sl@0: const TLinAddr	KKernelSectionEnd		=0xFFF00000u;	// we always use HIVECS
sl@0: 
sl@0: const TLinAddr	KMachineConfigLinAddr	=0x60000800u;
sl@0: const TLinAddr	KDummyUncachedAddr		=0x6000F000u;
sl@0: const TLinAddr	KTempAddr				=0x60010000u;
sl@0: const TLinAddr	KSecondTempAddr			=0x60014000u;
sl@0: const TLinAddr	KDefragAltStackAddr		=0x6001F000u;
sl@0: const TLinAddr	KPageInfoMap			=0x60030000u;
sl@0: 
sl@0: const TLinAddr	KDCacheFlushArea		=0x61100000u;
sl@0: const TInt		KDCacheFlushAreaLimit	=0x00080000;	// 512k
sl@0: const TLinAddr	KAltDCacheFlushArea		=0x61200000u;
sl@0: const TInt		KAltDCacheFlushAreaLimit=0x00080000;	// 512k
sl@0: 
sl@0: // Constants for ARM MMU
sl@0: const TInt KPageShift=12;
sl@0: const TInt KPageSize=1<<KPageShift;
sl@0: const TInt KPageMask=KPageSize-1;
sl@0: const TInt KChunkShift=20;
sl@0: const TInt KChunkSize=1<<KChunkShift;
sl@0: const TInt KChunkMask=KChunkSize-1;
sl@0: const TInt KPageTableShift=KChunkShift-KPageShift+2;	// PTE is 4 bytes
sl@0: const TInt KPageTableSize=1<<KPageTableShift;
sl@0: const TInt KPageTableMask=KPageTableSize-1;
sl@0: const TInt KPtClusterShift=KPageShift-KPageTableShift;
sl@0: const TInt KPtClusterSize=1<<KPtClusterShift;
sl@0: const TInt KPtClusterMask=KPtClusterSize-1;
sl@0: const TInt KPtBlockShift=KPageShift-3;					/**< @internalTechnology */	// sizeof(SPageTableInfo)=8
sl@0: const TInt KPtBlockSize=1<<KPtBlockShift;				/**< @internalTechnology */
sl@0: const TInt KPtBlockMask=KPtBlockSize-1;					/**< @internalTechnology */
sl@0: const TInt KPagesInPDEShift=KChunkShift-KPageShift;
sl@0: const TInt KPagesInPDE=1<<KPagesInPDEShift;
sl@0: const TInt KPagesInPDEMask=KPagesInPDE-1;
sl@0: const TInt KLargePageShift=16;
sl@0: const TInt KLargePageSize=1<<KLargePageShift;
sl@0: const TInt KLargePageMask=KLargePageSize-1;
sl@0: 
sl@0: const TInt KPageDirectoryShift=32-KChunkShift+2;		// PDE is 4 bytes
sl@0: const TInt KPageDirectorySize=1<<KPageDirectoryShift;
sl@0: const TInt KPageDirectoryMask=KPageDirectorySize-1;
sl@0: 
sl@0: const TPde KPdePresentMask=3;
sl@0: const TPde KPdeTypeMask=0x3;
sl@0: const TPde KPdeSectionAddrMask=0xfff00000;
sl@0: const TPde KPdePageTableAddrMask=0xfffffc00;
sl@0: const TPte KPteLargePageAddrMask=0xffff0000;
sl@0: const TPte KPteSmallPageAddrMask=0xfffff000;
sl@0: const TInt KLargeSmallPageRatio=KLargePageSize/KPageSize;
sl@0: const TPde KPdeNotPresentEntry=0;
sl@0: const TPte KPteNotPresentEntry=0;
sl@0: const TPte KPtePresentMask=0x3;
sl@0: const TPte KPteTypeMask=0x3;
sl@0: 
sl@0: 
sl@0: // Domain usage
sl@0: //
sl@0: /** @internalComponent */
sl@0: enum TArmDomain
sl@0: 	{
sl@0: 	EDomainVarUserRun=0,
sl@0: 	EDomainClient=1,
sl@0: 	EDomainPageTable=2,
sl@0: 	EDomainRamDrive=3,
sl@0: 
sl@0: 	ENumDomains=16
sl@0: 	};
sl@0: 
sl@0: // default domain access is 0=manager, 1=client, 2,3=no access, 4-15=client
sl@0: const TUint32 KDefaultDomainAccess			 = 0x55555507u;	/**< @internalComponent */
sl@0: const TUint32 KSupervisorInitialDomainAccess = 0x55555557u;	/**< @internalTechnology */
sl@0: 
sl@0: const TUint32 KManzanoTTBRExtraBits		=0x00000018;	/**< @internalTechnology On Manzano, page table walk is L2 cachable*/
sl@0: 
sl@0: const TInt KPageInfoShift = 5;
sl@0: 
sl@0: const TInt KAbtStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KUndStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KIrqStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KFiqStackSize=KPageSize;		/**< @internalComponent */
sl@0: 
sl@0: #endif	// __MMBOOT_H__