sl@0: // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
sl@0: // All rights reserved.
sl@0: // This component and the accompanying materials are made available
sl@0: // under the terms of the License "Eclipse Public License v1.0"
sl@0: // which accompanies this distribution, and is available
sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html".
sl@0: //
sl@0: // Initial Contributors:
sl@0: // Nokia Corporation - initial contribution.
sl@0: //
sl@0: // Contributors:
sl@0: //
sl@0: // Description:
sl@0: //
sl@0: 
sl@0: /**
sl@0:  @file
sl@0:  @publishedPartner
sl@0:  @prototype
sl@0: */
sl@0: 
sl@0: #ifndef __MMBOOT_H__
sl@0: #define __MMBOOT_H__
sl@0: 
sl@0: #include <nk_cpu.h>
sl@0: 
sl@0: // Linear address map
sl@0: // 00000000-003FFFFF	Unmapped
sl@0: // 00400000-7EFFFFFF	Local data
sl@0: // 7F000000-7FFFFFFF	IPC Alias region
sl@0: // 80000000-			ROM
sl@0: //         -8FFFFFFF	Global user area
sl@0: // 90000000-EFFFFFFF	Kernel memory
sl@0: // F0000000-FFF00000	Fixed kernel mappings
sl@0: // FFF00000-FFFFFFFF	Exception vectors
sl@0: //
sl@0: 
sl@0: // Linear addresses
sl@0: 
sl@0: const TLinAddr KUserLocalDataBase		=0x00400000u;
sl@0: 
sl@0: const TLinAddr KUserLocalDataEnd		=0x7f000000u;
sl@0: 
sl@0: const TLinAddr KIPCAlias				=0x7f000000u;
sl@0: const TLinAddr KIPCAliasAreaSize		=0x01000000u;
sl@0: 
sl@0: /** Everything above here is global (visible to all processes).*/
sl@0: const TLinAddr KGlobalMemoryBase		=0x80000000u;
sl@0: 
sl@0: const TLinAddr KRomLinearBase			=0x80000000u;
sl@0: 
sl@0: /** Everything below here has user access permissions, everything above is supervisor only. */
sl@0: const TLinAddr KUserMemoryLimit			=0x90000000u;
sl@0: 
sl@0: const TLinAddr KKernelSectionBase		=0x90000000u;
sl@0: 
sl@0: const TLinAddr KPrimaryIOBase			=0xC6000000u; // XXX This magic constant is hard coded into baseports!
sl@0: const TLinAddr KPrimaryIOEnd			=0xC8000000u;
sl@0: 
sl@0: const TLinAddr KKernelDataBase			=0xC8000000u;
sl@0: 
sl@0: const TLinAddr KKernelSectionEnd		=0xF0000000u;
sl@0: 
sl@0: const TLinAddr KSuperPageLinAddr		=0xF0000000u;
sl@0: const TLinAddr KMachineConfigLinAddr	=0xF0000800u;
sl@0: #ifdef __SMP__
sl@0: const TLinAddr KAPBootPageDirLin		=0xF0004000u;
sl@0: const TLinAddr KAPBootPageTableLin		=0xF0008000u;
sl@0: const TLinAddr KAPBootPageLin			=0xF0009000u;
sl@0: #endif
sl@0: const TLinAddr KDummyUncachedAddr		=0xF000F000u;
sl@0: const TLinAddr KPageInfoMap				=0xF0010000u;
sl@0: const TLinAddr KExcptStacksLinearBase	=0xF0040000u;
sl@0: const TLinAddr KExcptStacksLinearEnd	=0xF0080000u;
sl@0: const TLinAddr KTempAddr				=0xF0080000u;
sl@0: const TLinAddr KTempAddrEnd				=0xF0100000u;
sl@0: 
sl@0: const TLinAddr KPageTableInfoBase		=0xF0C00000u;
sl@0: const TLinAddr KPageTableInfoEnd		=0xF1000000u;
sl@0: 
sl@0: const TLinAddr KPageArraySegmentBase	=0xF1000000u;
sl@0: const TLinAddr KPageArraySegmentEnd		=0xF2000000u;
sl@0: 
sl@0: const TLinAddr KPageInfoLinearBase		=0xF2000000u;
sl@0: const TLinAddr KPageInfoLinearEnd		=0xF4000000u;
sl@0: 
sl@0: const TLinAddr KPageDirectoryBase		=0xF4000000u;
sl@0: const TLinAddr KPageDirectoryEnd		=0xF8000000u;
sl@0: 
sl@0: const TLinAddr KPageTableBase			=0xF8000000u;
sl@0: const TLinAddr KPageTableEnd			=0xFFF00000u;
sl@0: 
sl@0: 
sl@0: // Domain usage
sl@0: //
sl@0: // 0 All, except...
sl@0: // 2 IPC Alias chunk
sl@0: // 15 User memory when __USER_MEMORY_GUARDS_ENABLED__ defined
sl@0: const TInt KIPCAliasDomain = 2;
sl@0: const TInt KNumArmDomains = 16;								/**< @internalTechnology */
sl@0: 
sl@0: // default domain access is client of domain 0, no access to rest
sl@0: const TUint32 KDefaultDomainAccess			 = 0x00000001u;	/**< @internalTechnology */
sl@0: const TUint32 KSupervisorInitialDomainAccess = 0x00000001u;	/**< @internalTechnology */
sl@0: 
sl@0: #define	PDE_IN_DOMAIN(aPde, aDomain)	(((aPde) & ~(15 << 5)) | ((aDomain) << 5))
sl@0: 
sl@0: // Constants for ARM V6 MMU
sl@0: const TInt KPageShift=12;
sl@0: const TInt KPageSize=1<<KPageShift;
sl@0: const TInt KPageMask=KPageSize-1;
sl@0: const TInt KChunkShift=20;
sl@0: const TInt KChunkSize=1<<KChunkShift;
sl@0: const TInt KChunkMask=KChunkSize-1;
sl@0: const TInt KPageTableShift=KChunkShift-KPageShift+2;	// PTE is 4 bytes
sl@0: const TInt KPageTableSize=1<<KPageTableShift;
sl@0: const TInt KPageTableMask=KPageTableSize-1;
sl@0: const TInt KPtClusterShift=KPageShift-KPageTableShift;
sl@0: const TInt KPtClusterSize=1<<KPtClusterShift;
sl@0: const TInt KPtClusterMask=KPtClusterSize-1;
sl@0: const TInt KPtBlockShift=KPageShift-4;					/**< @internalTechnology */	// sizeof(SPageTableInfo)=16
sl@0: const TInt KPtBlockSize=1<<KPtBlockShift;				/**< @internalTechnology */
sl@0: const TInt KPtBlockMask=KPtBlockSize-1;					/**< @internalTechnology */
sl@0: const TInt KPagesInPDEShift=KChunkShift-KPageShift;
sl@0: const TInt KPagesInPDE=1<<KPagesInPDEShift;
sl@0: const TInt KPagesInPDEMask=KPagesInPDE-1;
sl@0: const TInt KLargePageShift=16;
sl@0: const TInt KLargePageSize=1<<KLargePageShift;
sl@0: const TInt KLargePageMask=KLargePageSize-1;
sl@0: 
sl@0: const TInt KPageDirectoryShift=32-KChunkShift+2;		// PDE is 4 bytes
sl@0: const TInt KPageDirectorySize=1<<KPageDirectoryShift;
sl@0: const TInt KPageDirectoryMask=KPageDirectorySize-1;
sl@0: 
sl@0: const TInt KMmuAsidCount=256;
sl@0: const TInt KMmuAsidMask=KMmuAsidCount-1;
sl@0: 
sl@0: const TUint KNumOsAsids=KMmuAsidCount;
sl@0: const TUint KKernelOsAsid=0;
sl@0: 
sl@0: // Permissions - 3 bit field, APX most significant. When __CPU_MEMORY_TYPE_REMAPPING defined, LSB must be 1
sl@0: #if defined(__CPU_MEMORY_TYPE_REMAPPING)
sl@0: const TInt KArmV6PermRORO=7;		/**< @internalTechnology */ // sup RO user RO
sl@0: #else
sl@0: const TInt KArmV6PermRORO=6;		/**< @internalTechnology */ // sup RO user RO
sl@0: #endif
sl@0: const TInt KArmV6PermRWNO=1;		/**< @internalTechnology */ // sup RW user no access
sl@0: const TInt KArmV6PermRWRW=3;		/**< @internalTechnology */ // sup RW user RW
sl@0: const TInt KArmV6PermRONO=5;		/**< @internalTechnology */ // sup RO user no access
sl@0: 
sl@0: #if defined(__CPU_MEMORY_TYPE_REMAPPING)
sl@0: // ARM1176, ARM11MPCORE, ARMv7
sl@0: // TMemoryType is used to describe cache attributes
sl@0: // 3 bits are reserved in page table: TEX[0]:C:B
sl@0: #else
sl@0: // Attributes - 5 bit field, TEX in 2-4, CB in 1,0
sl@0: const TInt KArmV6MemAttSO			=0x00;	/**< @internalTechnology */ // strongly ordered
sl@0: const TInt KArmV6MemAttSD			=0x01;	/**< @internalTechnology */ // shared device
sl@0: const TInt KArmV6MemAttNSD			=0x08;	/**< @internalTechnology */ // non-shared device
sl@0: const TInt KArmV6MemAttNCNC			=0x04;	/**< @internalTechnology */ // normal, outer uncached, inner uncached
sl@0: const TInt KArmV6MemAttWTRAWTRA		=0x02;	/**< @internalTechnology */ // normal, outer WTRA cached, inner WTRA cached
sl@0: const TInt KArmV6MemAttWBRAWBRA		=0x03;	/**< @internalTechnology */	// normal, outer WBRA cached, inner WBRA cached
sl@0: const TInt KArmV6MemAttWBWAWBWA		=0x15;	/**< @internalTechnology */	// normal, outer WBWA cached, inner WBWA cached
sl@0: const TInt KArmV6MemAttNCWTRA		=0x12;	/**< @internalTechnology */	// normal, outer uncached, inner WTRA cached
sl@0: const TInt KArmV6MemAttNCWBRA		=0x13;	/**< @internalTechnology */	// normal, outer uncached, inner WBRA cached
sl@0: const TInt KArmV6MemAttNCWBWA		=0x11;	/**< @internalTechnology */	// normal, outer uncached, inner WBWA cached
sl@0: const TInt KArmV6MemAttWTRANC		=0x18;	/**< @internalTechnology */	// normal, outer WTRA cached, inner uncached
sl@0: const TInt KArmV6MemAttWTRAWBRA		=0x1B;	/**< @internalTechnology */	// normal, outer WTRA cached, inner WBRA cached
sl@0: const TInt KArmV6MemAttWTRAWBWA		=0x19;	/**< @internalTechnology */	// normal, outer WTRA cached, inner WBWA cached
sl@0: const TInt KArmV6MemAttWBRANC		=0x1C;	/**< @internalTechnology */	// normal, outer WBRA cached, inner uncached
sl@0: const TInt KArmV6MemAttWBRAWTRA		=0x1E;	/**< @internalTechnology */	// normal, outer WBRA cached, inner WTRA cached
sl@0: const TInt KArmV6MemAttWBRAWBWA		=0x1D;	/**< @internalTechnology */	// normal, outer WBRA cached, inner WBWA cached
sl@0: const TInt KArmV6MemAttWBWANC		=0x14;	/**< @internalTechnology */	// normal, outer WBWA cached, inner uncached
sl@0: const TInt KArmV6MemAttWBWAWTRA		=0x16;	/**< @internalTechnology */	// normal, outer WBWA cached, inner WTRA cached
sl@0: const TInt KArmV6MemAttWBWAWBRA		=0x17;	/**< @internalTechnology */	// normal, outer WBWA cached, inner WBRA cached
sl@0: #endif
sl@0: 
sl@0: const TUint32 KArmV6PdePageTable	=0x00000001;/**< @internalTechnology */	// L1 descriptor is page table
sl@0: const TUint32 KArmV6PdeSection		=0x00000002;/**< @internalTechnology */	// L1 descriptor is section
sl@0: const TUint32 KArmV6PdeTypeMask		=0x00000003;/**< @internalTechnology */
sl@0: const TUint32 KArmV6PdeECCEnable	=0x00000200;/**< @internalTechnology */	// ECC enable (all L1 descriptors)
sl@0: const TUint32 KArmV6PdeSectionXN	=0x00000010;/**< @internalTechnology */	// Section not executable
sl@0: const TUint32 KArmV6PdeSectionS		=0x00010000;/**< @internalTechnology */	// Section shared
sl@0: const TUint32 KArmV6PdeSectionNG	=0x00020000;/**< @internalTechnology */	// Section not global
sl@0: const TUint32 KArmV6PdePermMask		=0x00008c00;/**< @internalTechnology */	// Section permission bits
sl@0: const TUint32 KArmV6PdeAttMask		=0x0000700c;/**< @internalTechnology */	// Section memory attribute bits
sl@0: const TUint32 KArmV6PteLargePage	=0x00000001;/**< @internalTechnology */	// L2 descriptor is large page
sl@0: const TUint32 KArmV6PteSmallPage	=0x00000002;/**< @internalTechnology */	// L2 descriptor is small page
sl@0: const TUint32 KArmV6PteTypeMask		=0x00000003;/**< @internalTechnology */
sl@0: const TUint32 KArmV6PteLargeXN		=0x00008000;/**< @internalTechnology */	// Large page not executable
sl@0: const TUint32 KArmV6PteSmallXN		=0x00000001;/**< @internalTechnology */	// Small page not executable
sl@0: const TUint32 KArmV6PteS			=0x00000400;/**< @internalTechnology */	// Large or small page shared
sl@0: const TUint32 KArmV6PteNG			=0x00000800;/**< @internalTechnology */	// Large or small page not global
sl@0: const TUint32 KArmV6PtePermMask		=0x00000230;/**< @internalTechnology */	// Large or small page permission bits
sl@0: const TUint32 KArmV6PteLargeAttMask	=0x0000700c;/**< @internalTechnology */	// Large page memory attribute bits
sl@0: const TUint32 KArmV6PteSmallAttMask	=0x000001cc;/**< @internalTechnology */	// Small page memory attribute bits
sl@0: // Remapped Access Permission coding:
sl@0: const TUint32 KArmV6PteAP2			=0x00000200;/**< @internalTechnology */	// RO / !RW
sl@0: const TUint32 KArmV6PteSmallTEX2	=0x00000100;/**< @internalTechnology */
sl@0: const TUint32 KArmV6PteSmallTEX1	=0x00000080;/**< @internalTechnology */
sl@0: const TUint32 KArmV6PteSmallTEX0	=0x00000040;/**< @internalTechnology */
sl@0: const TUint32 KArmV6PteAP1			=0x00000020;/**< @internalTechnology */	// AllAccess / !KernelOnly
sl@0: const TUint32 KArmV6PteAP0			=0x00000010;/**< @internalTechnology */	// Must be set
sl@0: 
sl@0: const TUint32  KPdePresentMask=KArmV6PdeTypeMask;				/**< @internalTechnology */
sl@0: const TUint32  KPdeTypeMask=KArmV6PdeTypeMask;					/**< @internalTechnology */
sl@0: const TUint32  KPdeSectionAddrMask=0xfff00000;					/**< @internalTechnology */
sl@0: const TUint32  KPdePageTableAddrMask=0xfffffc00;				/**< @internalTechnology */
sl@0: const TUint32  KPteLargePageAddrMask=0xffff0000;				/**< @internalTechnology */
sl@0: const TUint32  KPteSmallPageAddrMask=0xfffff000;				/**< @internalTechnology */
sl@0: const TInt KLargeSmallPageRatio=KLargePageSize/KPageSize;	/**< @internalTechnology */
sl@0: const TUint32  KPdeUnallocatedEntry=0;							/**< @internalTechnology */
sl@0: const TUint32  KPteUnallocatedEntry=0;							/**< @internalTechnology */
sl@0: const TUint32  KPdeMatchMask=0;									/**< @internalTechnology */
sl@0: const TUint32  KPteMatchMask=0;									/**< @internalTechnology */
sl@0: const TUint32  KPtePresentMask=KArmV6PteTypeMask;				/**< @internalTechnology */
sl@0: const TUint32  KPteTypeMask=KArmV6PteTypeMask;					/**< @internalTechnology */
sl@0: 
sl@0: const TUint32 KTTBRExtraBitsMask	=0x0000007f;	/**< @internalTechnology */	// Extra bits in TTBR in addition to physical address
sl@0: 
sl@0: const TInt KPageInfoShift = 5;
sl@0: 
sl@0: #ifdef __CPU_CACHE_HAS_COLOUR
sl@0: const TInt KPageColourShift=2;
sl@0: #else
sl@0: const TInt KPageColourShift=0;
sl@0: #endif
sl@0: const TInt KPageColourCount=(1<<KPageColourShift);
sl@0: const TInt KPageColourMask=KPageColourCount-1;	
sl@0: 	
sl@0: const TInt KAbtStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KUndStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KIrqStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KFiqStackSize=KPageSize;		/**< @internalComponent */
sl@0: const TInt KExcStackAddressSpace = KIrqStackSize + KFiqStackSize + KUndStackSize + KAbtStackSize + 4*KPageSize;	/**< @internalComponent */
sl@0: 
sl@0: const TInt KMaxCPUs = 8;
sl@0: __ASSERT_COMPILE(KExcptStacksLinearEnd-KExcptStacksLinearBase >= (TLinAddr)KExcStackAddressSpace * (TUint)KMaxCPUs);
sl@0: 
sl@0: #endif	// __MMBOOT_H__