sl@0: // Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // include/drivers/dmadefs.h sl@0: // DMA Framework - General class, enum, constant and type definitions. sl@0: // sl@0: // sl@0: sl@0: #ifndef __DMADEFS_H__ sl@0: #define __DMADEFS_H__ sl@0: sl@0: sl@0: #include sl@0: sl@0: sl@0: /** The client request callback type */ sl@0: enum TDmaCallbackType sl@0: { sl@0: /** Transfer request completion callback */ sl@0: EDmaCallbackRequestCompletion = 0x01, sl@0: /** Transfer request completion callback - source side */ sl@0: EDmaCallbackRequestCompletion_Src = 0x02, sl@0: /** Transfer request completion callback - destination side */ sl@0: EDmaCallbackRequestCompletion_Dst = 0x04, sl@0: sl@0: /** Descriptor completion callback */ sl@0: EDmaCallbackDescriptorCompletion = 0x08, sl@0: /** Descriptor completion callback - source side */ sl@0: EDmaCallbackDescriptorCompletion_Src = 0x10, sl@0: /** Descriptor completion callback - destination side */ sl@0: EDmaCallbackDescriptorCompletion_Dst = 0x20, sl@0: sl@0: /** Frame completion callback */ sl@0: EDmaCallbackFrameCompletion = 0x40, sl@0: /** Frame completion callback - source side */ sl@0: EDmaCallbackFrameCompletion_Src = 0x80, sl@0: /** Frame completion callback - destination side */ sl@0: EDmaCallbackFrameCompletion_Dst = 0x100, sl@0: sl@0: /** H/W descriptor pause event callback */ sl@0: EDmaCallbackLinkedListPaused = 0x200, sl@0: /** H/W descriptor pause event callback - source side */ sl@0: EDmaCallbackLinkedListPaused_Src = 0x400, sl@0: /** H/W descriptor pause event callback - destination side */ sl@0: EDmaCallbackLinkedListPaused_Dst = 0x800 sl@0: }; sl@0: sl@0: sl@0: /** The outcome of the transfer request */ sl@0: enum TDmaResult sl@0: { sl@0: /** Completed without error */ sl@0: EDmaResultOK = 0, sl@0: /** There was an error */ sl@0: EDmaResultError sl@0: }; sl@0: sl@0: sl@0: sl@0: /** To be used with address mode field of the DMA transfer config struct. sl@0: sl@0: @see TDmaTransferConfig::iAddrMode sl@0: */ sl@0: enum TDmaAddrMode sl@0: { sl@0: /** Constant addressing. The address remains the same for consecutive sl@0: accesses. sl@0: */ sl@0: KDmaAddrModeConstant, sl@0: /** Post-increment addressing. The address increases by the element size sl@0: after each access. sl@0: */ sl@0: KDmaAddrModePostIncrement, sl@0: /** Post-decrement addressing. The address decreases by the element size sl@0: after each access. sl@0: */ sl@0: KDmaAddrModePostDecrement, sl@0: /** 1D-index addressing. The address always increases by the element size sl@0: plus the element skip value after each access. sl@0: */ sl@0: KDmaAddrMode1DIndex, sl@0: /** 2D-index addressing. The address increases by the element size plus the sl@0: element skip value - but only within a frame. Once a full frame has been sl@0: transferred, the address increases by the element size plus the element sl@0: skip value plus the frame skip value. sl@0: */ sl@0: KDmaAddrMode2DIndex sl@0: }; sl@0: sl@0: sl@0: /** To be used with the burst size field of the DMA transfer config struct. sl@0: sl@0: @see SDmacCaps::iBurstTransactions sl@0: @see TDmaTransferConfig::iBurstSize sl@0: */ sl@0: enum TDmaBurstSize sl@0: { sl@0: /** Don't use burst transactions */ sl@0: KDmaNoBursts = -1, sl@0: /** Don't care (the default) */ sl@0: KDmaBurstSizeAny = 0x00, sl@0: /** 4 bytes */ sl@0: KDmaBurstSize4 = 0x04, sl@0: /** 8 bytes */ sl@0: KDmaBurstSize8 = 0x08, sl@0: /** 16 bytes */ sl@0: KDmaBurstSize16 = 0x10, sl@0: /** 32 bytes */ sl@0: KDmaBurstSize32 = 0x20, sl@0: /** 64 bytes */ sl@0: KDmaBurstSize64 = 0x40, sl@0: /** 128 bytes */ sl@0: KDmaBurstSize128 = 0x80 sl@0: }; sl@0: sl@0: sl@0: /** To be used with the flags field of the DMA transfer config struct. sl@0: sl@0: @see TDmaTransferConfig::iFlags sl@0: */ sl@0: enum TDmaTransferFlags sl@0: { sl@0: /** Location is address of a memory buffer (as opposed to a peripheral or a sl@0: register). sl@0: */ sl@0: KDmaMemAddr = 0x01, sl@0: /** Address is a physical address (as opposed to a linear one). sl@0: If it is a memory address then KDmaMemIsContiguous will need to be set sl@0: as well. sl@0: */ sl@0: KDmaPhysAddr = 0x02, sl@0: /** Target memory is known to be physically contiguous, hence there is sl@0: no need for the framework to check for memory fragmentation. sl@0: */ sl@0: KDmaMemIsContiguous = 0x04, sl@0: /** Don't use packed access (if possible) */ sl@0: KDmaDontUsePacked = 0x08, sl@0: /** Location is big endian (little endian if not set). sl@0: sl@0: To have any effect, this flag requires the DMAC to support endianness sl@0: conversion. sl@0: sl@0: @see SDmacCaps::iEndiannessConversion sl@0: */ sl@0: KDmaBigEndian = 0x10, sl@0: /** Don't do endianness conversion even if applicable. sl@0: sl@0: To have any effect, this flag requires the DMAC to support endianness sl@0: conversion. sl@0: sl@0: @see SDmacCaps::iEndiannessConversion sl@0: */ sl@0: KDmaLockEndian = 0x20, sl@0: /** Execute client request callback after each subtransfer (streaming / sl@0: loop case). sl@0: sl@0: This option is only taken into account if the respective sl@0: TDmaTransferConfig::iRepeatCount is non-zero. sl@0: sl@0: The callback will complete with a TDmaCallbackType of sl@0: EDmaCallbackRequestCompletion (even if the repeat counts for source and sl@0: destination are different), unless the flag sl@0: TDmaPILFlags::KDmaAsymCompletionCallback is set too, in which case what sl@0: is described there applies. sl@0: */ sl@0: KDmaCallbackAfterEveryTransfer = 0x40, sl@0: /** Execute client request callback after each completed hardware sl@0: descriptor. sl@0: sl@0: Requires the DMAC to support this feature. Unless the DMAC supports sl@0: asymmetric descriptor interrupts as well, this flag should not be set sl@0: on only one (source or destination) side. sl@0: sl@0: @see SDmacCaps::iDescriptorInterrupt sl@0: @see SDmacCaps::iAsymDescriptorInterrupt sl@0: */ sl@0: KDmaCallbackAfterEveryDescriptor = 0x80, sl@0: /** Execute client request callback after each completed frame. sl@0: sl@0: Requires the DMAC to support this feature. Unless the DMAC supports sl@0: asymmetric frame interrupts as well, this flag should not be set on sl@0: only one (source or destination) side. sl@0: sl@0: @see SDmacCaps::iFrameInterrupt sl@0: @see SDmacCaps::iAsymFrameInterrupt sl@0: */ sl@0: KDmaCallbackAfterEveryFrame = 0x100 sl@0: }; sl@0: sl@0: sl@0: /** To be used with the synchronization flags field of a DMA transfer sl@0: config struct. sl@0: sl@0: @see SDmacCaps::iSynchronizationTypes sl@0: @see TDmaTransferConfig::iSyncFlags sl@0: */ sl@0: enum TDmaTransferSyncFlags sl@0: { sl@0: /** Leave the decision on whether the transfer is hardware synchronized at sl@0: this end (either source or destination) to the Framework. This is the sl@0: default. sl@0: */ sl@0: KDmaSyncAuto = 0x00, sl@0: /** Transfer is not hardware synchronized at this end (either source or sl@0: destination). sl@0: */ sl@0: KDmaSyncNone = 0x01, sl@0: /** Transfer is hardware synchronized at this end (either source or sl@0: destination). This option can also be used on its own, without any sl@0: of the following sync sizes. sl@0: */ sl@0: KDmaSyncHere = 0x02, sl@0: /** H/W synchronized at this end: transfer one ELEMENT (a number of sl@0: bytes, depending on the configured element size) per sync event. sl@0: */ sl@0: KDmaSyncSizeElement = 0x04, sl@0: /** H/W synchronized at this end: transfer one FRAME (a number of sl@0: elements, depending on the configured frame size) per sync event. sl@0: */ sl@0: KDmaSyncSizeFrame = 0x08, sl@0: /** H/W synchronized at this end: transfer one BLOCK (a number of sl@0: frames, depending on the configured transfer size) per sync sl@0: event. This is the most common use case. sl@0: */ sl@0: KDmaSyncSizeBlock = 0x10, sl@0: /** H/W synchronized at this end: transfer one PACKET (a number of sl@0: elements, depending on the configured packet size) per sync event. sl@0: In cases where the transfer block size is not a multiple of the sl@0: packet size the last packet will consist of the remaining elements. sl@0: */ sl@0: KDmaSyncSizePacket = 0x20 sl@0: }; sl@0: sl@0: sl@0: /** To be used with the Graphics operation field of a DMA transfer request. sl@0: sl@0: @see TDmaTransferArgs::iGraphicsOps sl@0: */ sl@0: enum TDmaGraphicsOps sl@0: { sl@0: /** Don't use any graphics acceleration feature (the default) */ sl@0: KDmaGraphicsOpNone = 0x00, sl@0: /** Enable graphics acceleration feature 'Constant Fill' */ sl@0: KDmaGraphicsOpConstantFill = 0x01, sl@0: /** Enable graphics acceleration feature 'TransparentCopy' */ sl@0: KDmaGraphicsOpTransparentCopy = 0x02 sl@0: }; sl@0: sl@0: sl@0: /** To be used with the PIL flags field of a DMA transfer request. sl@0: sl@0: @see TDmaTransferArgs::iFlags sl@0: */ sl@0: enum TDmaPILFlags sl@0: { sl@0: /** Request a different max transfer size (for instance for test sl@0: purposes). sl@0: */ sl@0: KDmaAltTransferLength = 0x01, sl@0: /** Execute client request callback in ISR context instead of from a sl@0: DFC. sl@0: */ sl@0: KDmaRequestCallbackFromIsr = 0x02, sl@0: /** Execute descriptor completion callback in ISR context instead of sl@0: from a DFC. This option is to be used in conjunction with the sl@0: TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag. sl@0: */ sl@0: KDmaDescriptorCallbackFromIsr = 0x04, sl@0: /** Execute frame completion callback in ISR context instead of sl@0: from a DFC. This option is to be used in conjunction with the sl@0: TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. sl@0: */ sl@0: KDmaFrameCallbackFromIsr = 0x08, sl@0: /** Execute the client request callback separately for source and sl@0: destination subtransfers. sl@0: sl@0: This flag also determines the TDmaCallbackType value returned. If set, sl@0: the callback will complete with EDmaCallbackRequestCompletion_Src or sl@0: EDmaCallbackRequestCompletion_Dst, respectively, instead of with sl@0: EDmaCallbackRequestCompletion. sl@0: sl@0: Requires the DMAC to support this feature. sl@0: sl@0: @see SDmacCaps::iAsymCompletionInterrupt sl@0: */ sl@0: KDmaAsymCompletionCallback = 0x10, sl@0: /** Execute the descriptor completion callback separately for source sl@0: and destination subtransfers. sl@0: sl@0: This flag modifies the behaviour of the sl@0: TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag and also sl@0: determines the TDmaCallbackType value returned. If set, the callback sl@0: will complete with EDmaCallbackDescriptorCompletion_Src or sl@0: EDmaCallbackDescriptorCompletion_Dst, respectively, instead of with sl@0: EDmaCallbackDescriptorCompletion. sl@0: sl@0: Requires the DMAC to support this feature. sl@0: sl@0: @see SDmacCaps::iAsymDescriptorInterrupt sl@0: */ sl@0: KDmaAsymDescriptorCallback = 0x20, sl@0: /** Execute the frame completion callback separately for source and sl@0: destination subtransfers. sl@0: sl@0: This flag modifies the behaviour of the sl@0: TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. If set, the sl@0: callback will complete with EDmaCallbackFrameCompletion_Src or sl@0: EDmaCallbackFrameCompletion_Dst, respectively, instead of with sl@0: EDmaCallbackFrameCompletion. sl@0: sl@0: Requires the DMAC to support this feature. sl@0: sl@0: @see SDmacCaps::iAsymFrameInterrupt sl@0: */ sl@0: KDmaAsymFrameCallback = 0x40, sl@0: /** This transfer (only) should use the channel priority indicated by sl@0: TDmaTransferArgs::iChannelPriority. sl@0: */ sl@0: KDmaRequestChannelPriority = 0x80 sl@0: }; sl@0: sl@0: sl@0: /** Values which can be used with the priority field when opening a channel sl@0: and/or when fragmenting a transfer request. sl@0: sl@0: @see TDmaChannel::SCreateInfo::iPriority sl@0: @see TDmaTransferArgs::iChannelPriority sl@0: */ sl@0: enum TDmaPriority sl@0: { sl@0: /** No transfer priority preference (don't care value) */ sl@0: KDmaPriorityNone = 0x0, sl@0: /** Platform-independent transfer priority 1 (lowest) */ sl@0: KDmaPriority1 = 0x80000001, sl@0: /** Platform-independent transfer priority 2 */ sl@0: KDmaPriority2 = 0x80000002, sl@0: /** Platform-independent transfer priority 3 */ sl@0: KDmaPriority3 = 0x80000003, sl@0: /** Platform-independent transfer priority 4 */ sl@0: KDmaPriority4 = 0x80000004, sl@0: /** Platform-independent transfer priority 5 */ sl@0: KDmaPriority5 = 0x80000005, sl@0: /** Platform-independent transfer priority 6 */ sl@0: KDmaPriority6 = 0x80000006, sl@0: /** Platform-independent transfer priority 7 */ sl@0: KDmaPriority7 = 0x80000007, sl@0: /** Platform-independent transfer priority 8 (highest) */ sl@0: KDmaPriority8 = 0x80000008 sl@0: }; sl@0: sl@0: sl@0: /** Contains the configuration values for either the source or the sl@0: destination side of a DMA transfer. sl@0: sl@0: Note that some fields (notably iElementSize, iElementsPerFrame and sl@0: iFramesPerTransfer) may only differ between source and destination if sl@0: the underlying DMAC supports this. sl@0: sl@0: @see SDmacCaps::iSrcDstAsymmetry sl@0: @see TDmaTransferArgs::iSrcConfig sl@0: @see TDmaTransferArgs::iDstConfig sl@0: */ sl@0: struct TDmaTransferConfig sl@0: { sl@0: friend struct TDmaTransferArgs; sl@0: sl@0: /** Default constructor. Initializes all fields with meaningful default sl@0: values. sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferConfig(); sl@0: sl@0: /** Intended for general use ie. not 2D or 1D transfers sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferConfig ( sl@0: TUint32 aAddr, sl@0: TUint aTransferFlags, sl@0: TDmaAddrMode aAddrMode = KDmaAddrModePostIncrement, sl@0: TUint aSyncFlags = KDmaSyncAuto, sl@0: TDmaBurstSize aBurstSize = KDmaBurstSizeAny, sl@0: TUint aElementSize = 0, sl@0: TUint aElementsPerPacket = 0, sl@0: TUint aPslTargetInfo = 0, sl@0: TInt aRepeatCount = 0 sl@0: ); sl@0: sl@0: /** Intended for 1D and 2D transfers sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferConfig ( sl@0: TUint32 aAddr, sl@0: TUint aElementSize, sl@0: TUint aElementsPerFrame, sl@0: TUint aFramesPerTransfer, sl@0: TInt aElementSkip, sl@0: TInt aFrameSkip, sl@0: TUint aTransferFlags, sl@0: TUint aSyncFlags = KDmaSyncAuto, sl@0: TDmaBurstSize aBurstSize = KDmaBurstSizeAny, sl@0: TUint aElementsPerPacket = 0, sl@0: TUint aPslTargetInfo = 0, sl@0: TInt aRepeatCount = 0 sl@0: ); sl@0: sl@0: /** Transfer start address */ sl@0: TUint32 iAddr; sl@0: /** Address mode */ sl@0: TDmaAddrMode iAddrMode; sl@0: /** Element size in bytes (1/2/4/8) */ sl@0: TUint iElementSize; sl@0: /** Number of elements per frame */ sl@0: TUint iElementsPerFrame; sl@0: /** Number of elements per packet */ sl@0: TUint iElementsPerPacket; sl@0: /** Number of frames to transfer (result is the transfer block) */ sl@0: TUint iFramesPerTransfer; sl@0: /** Element skip in bytes (for addr modes E1DIndex or E2DIndex) */ sl@0: TInt iElementSkip; sl@0: /** Frame skip in bytes (for addr mode E2DIndex) */ sl@0: TInt iFrameSkip; sl@0: /** Use burst transactions of the specified size (in bytes) sl@0: @see TDmaBurstSize sl@0: */ sl@0: TInt iBurstSize; sl@0: /** PIL src/dst config flags. sl@0: @see TDmaTransferFlags sl@0: */ sl@0: TUint32 iFlags; sl@0: /** Transfer synchronization flags. sl@0: @see TDmaTransferSyncFlags sl@0: */ sl@0: TUint32 iSyncFlags; sl@0: /** Information passed to the PSL */ sl@0: TUint iPslTargetInfo; sl@0: /** How often to repeat this (sub-)transfer: sl@0: 0 no repeat (the default) sl@0: 1..n once / n times sl@0: -1 endlessly. sl@0: */ sl@0: TInt iRepeatCount; sl@0: /** Structure contents delta vector (usage tbd) */ sl@0: TUint32 iDelta; sl@0: /** Reserved for future use */ sl@0: TUint32 iReserved; sl@0: sl@0: private: sl@0: /** Private constructor. Initializes fields with the values passed in by sl@0: the legacy version of the DDmaRequest::Fragment() call. sl@0: */ sl@0: TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc); sl@0: }; sl@0: sl@0: sl@0: /** To be used by the client to pass DMA transfer request details to the sl@0: framework. sl@0: sl@0: Also used internally by the framework as a pseudo descriptor if the sl@0: controller doesn't support hardware descriptors (scatter/gather LLI). sl@0: sl@0: @see DDmaRequest::Fragment sl@0: */ sl@0: struct TDmaTransferArgs sl@0: { sl@0: friend class DDmaRequest; sl@0: friend class TDmaChannel; sl@0: friend class TDmac; sl@0: friend class DmaChannelMgr; sl@0: sl@0: /** Default constructor. Initializes all fields with meaningful default sl@0: values. sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferArgs(); sl@0: sl@0: /** For transfers where src and dst TDmaTransferConfig structs share some sl@0: of the same options ie. iDmaTransferFlags, iAddrMode, iSyncFlags, sl@0: iBurstSize, and iElementSize. sl@0: sl@0: @param aSrcAddr sl@0: @param aDstAddr sl@0: @param aCount Number of bytes to transfer sl@0: @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst sl@0: @param aDmaSyncFlags Bitmask of TDmaTransferSyncFlags for src and dst sl@0: @param aMode Address mode for src and dst sl@0: @param aDmaPILFlags Bitmask of TDmaPILFlags sl@0: @param aElementSize In bytes (1/2/4/8) for src and dst sl@0: @param aChannelPriority sl@0: @param aBurstSize for src and dst sl@0: @param aPslRequestInfo Info word passed to the PSL sl@0: @param aGraphicOp Graphics operation to be executed sl@0: @param aColour Colour value for graphics operation sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferArgs ( sl@0: TUint aSrcAddr, TUint aDstAddr, TUint aCount, sl@0: TUint aDmaTransferFlags, TUint aDmaSyncFlags = KDmaSyncAuto, sl@0: TUint aDmaPILFlags = 0, sl@0: TDmaAddrMode aMode = KDmaAddrModePostIncrement, TUint aElementSize = 0, sl@0: TUint aChannelPriority = KDmaPriorityNone, sl@0: TDmaBurstSize aBurstSize = KDmaBurstSizeAny, TUint aPslRequestInfo = 0, sl@0: TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0 sl@0: ); sl@0: sl@0: /** For transfers needing specific options for source and destination sl@0: TDmaTransferConfig structs. sl@0: sl@0: @param aSrc Configuration values for the source sl@0: @param aDst Configuration values for the destination sl@0: @param aFlags @see TDmaPILFlags sl@0: @param aChannelPriority Use for this request (only) the indicated sl@0: channel priority. Requires KDmaRequestChannelPriority to be set in sl@0: iFlags as well. @see TDmaPriority sl@0: sl@0: @param aPslRequestInfo Info word passed to the PSL sl@0: @param aGraphicOp Graphics operation to be executed sl@0: @param aColour Colour value for graphics operation sl@0: */ sl@0: #ifdef DMA_APIV2 sl@0: KIMPORT_C sl@0: #endif sl@0: TDmaTransferArgs ( sl@0: const TDmaTransferConfig& aSrc, sl@0: const TDmaTransferConfig& aDst, sl@0: TUint32 aFlags = 0, sl@0: TUint aChannelPriority = KDmaPriorityNone, sl@0: TUint aPslRequestInfo = 0, sl@0: TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0 sl@0: ); sl@0: sl@0: /** Configuration values for the source */ sl@0: TDmaTransferConfig iSrcConfig; sl@0: /** Configuration values for the destination */ sl@0: TDmaTransferConfig iDstConfig; sl@0: sl@0: /** Number of bytes to transfer (optional). sl@0: sl@0: A non-zero value here must be consistent with iElementSize, sl@0: iElementsPerFrame and iFramesPerTransfer in iSrcConfig and iDstConfig sl@0: if the latter are specified as well (or instead, they may be left at sl@0: their default values of zero). sl@0: sl@0: If zero, the PIL will fill in a value calculated from multiplying sl@0: iElementSize, iElementsPerFrame and iFramesPerTransfer in iSrcConfig, sl@0: so that the PSL can rely on it being always non-zero and valid. sl@0: */ sl@0: TUint iTransferCount; sl@0: /** Graphics operation to be executed */ sl@0: TDmaGraphicsOps iGraphicsOps; sl@0: /** Colour value for graphics operations */ sl@0: TUint32 iColour; sl@0: /** PIL common flags sl@0: @see TDmaPILFlags sl@0: */ sl@0: TUint32 iFlags; sl@0: /** Use for this request (only) the indicated channel priority. sl@0: Requires KDmaRequestChannelPriority to be set in iFlags as well. sl@0: @see TDmaPriority sl@0: */ sl@0: TUint iChannelPriority; sl@0: /** Info word passed to the PSL */ sl@0: TUint iPslRequestInfo; sl@0: sl@0: /** Structure contents delta vector (usage tbd) */ sl@0: TUint32 iDelta; sl@0: /** Reserved for future use */ sl@0: TUint32 iReserved1; sl@0: sl@0: private: sl@0: /** Private constructor. Initializes fields with the values passed in by sl@0: the legacy version of the DDmaRequest::Fragment() call. sl@0: */ sl@0: TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount, sl@0: TUint aFlags, TUint32 aPslInfo); sl@0: /** Stores the PSL cookie returned by TDmaChannel::PslId() at request sl@0: fragmentation time. sl@0: The value PslId() is often (but not necessarily) identical with the sl@0: client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the sl@0: PIL into DmaChannelMgr::Open() as 'aOpenId'. sl@0: */ sl@0: TUint32 iChannelCookie; sl@0: /** Reserved for future use */ sl@0: TUint32 iReserved2; sl@0: }; sl@0: sl@0: sl@0: /** DMAC capabilities info structure. sl@0: sl@0: Instances are to be filled in by the PSL and then linked to via TDmaChannel sl@0: objects after they have been opened. sl@0: sl@0: The contents may vary even between channels on the same DMAC (but will sl@0: remain constant for a given channel for the duration that it is open), sl@0: depending on static or dynamic factors which only the PSL knows about. sl@0: sl@0: @see TDmaChannel::Open sl@0: @see TDmaChannel::DmacCaps sl@0: */ sl@0: struct SDmacCaps sl@0: { sl@0: /** DMAC supports n + 1 different channel priorities. */ sl@0: TUint iChannelPriorities; sl@0: /** DMAC supports the pausing and resuming of channels. */ sl@0: TBool iChannelPauseAndResume; sl@0: /** DMA addresses must be aligned on an element size boundary. */ sl@0: TBool iAddrAlignedToElementSize; sl@0: /** DMAC supports 1D (element) index addressing in hardware. */ sl@0: TBool i1DIndexAddressing; sl@0: /** DMAC supports 2D (frame) index addressing in hardware. */ sl@0: TBool i2DIndexAddressing; sl@0: /** DMAC supports these transfer synchronization types (bitmap of values). sl@0: sl@0: @see TDmaTransferSyncFlags sl@0: */ sl@0: TUint iSynchronizationTypes; sl@0: /** DMAC supports burst transactions with these sizes (bitmap of values). sl@0: sl@0: @see TDmaBurstSize sl@0: */ sl@0: TUint iBurstTransactions; sl@0: /** DMAC supports a 'h/w descriptor complete' interrupt. */ sl@0: TBool iDescriptorInterrupt; sl@0: /** DMAC supports a 'frame transfer complete' interrupt. */ sl@0: TBool iFrameInterrupt; sl@0: /** DMAC supports a 'linked-list pause event' interrupt. */ sl@0: TBool iLinkedListPausedInterrupt; sl@0: /** DMAC supports endianness conversion. */ sl@0: TBool iEndiannessConversion; sl@0: /** DMAC supports these graphics operations (bitmap of values). sl@0: sl@0: @see TDmaGraphicsOps sl@0: */ sl@0: TUint iGraphicsOps; sl@0: /** DMAC supports repeated transfers (loops). */ sl@0: TBool iRepeatingTransfers; sl@0: /** DMAC supports logical channel linking (chaining). */ sl@0: TBool iChannelLinking; sl@0: /** DMAC supports scatter/gather mode (linked list items). */ sl@0: TBool iHwDescriptors; sl@0: /** DMAC supports asymmetric source and destination transfer sl@0: parameters (such as element size). sl@0: */ sl@0: TBool iSrcDstAsymmetry; sl@0: /** DMAC supports asymmetric h/w descriptor lists. sl@0: sl@0: ETrue here requires ETrue for iHwDescriptors and iSrcDstAsymmetry as sl@0: well. sl@0: */ sl@0: TBool iAsymHwDescriptors; sl@0: /** DMAC with asymmetric descriptor support has the limitation that the sl@0: number of bytes transferred in source and destination must be equal in sl@0: every link segment (i.e. in each src/dst descriptor pair). sl@0: sl@0: ETrue here requires ETrue for iAsymHwDescriptors as well. sl@0: */ sl@0: TBool iBalancedAsymSegments; sl@0: /** DMAC supports separate transfer completion notifications for source and sl@0: destination side subtransfers. sl@0: sl@0: This capability is required for the asymmetric transfer completion sl@0: callback API feature. sl@0: sl@0: @see TDmaPILFlags::KDmaAsymCompletionCallback sl@0: */ sl@0: TBool iAsymCompletionInterrupt; sl@0: /** DMAC supports separate descriptor completion notifications for source and sl@0: destination side. sl@0: sl@0: This capability is required for the asymmetric descriptor completion sl@0: callback API feature. sl@0: sl@0: ETrue here requires ETrue for both iDescriptorInterrupt and sl@0: iAsymHwDescriptors as well. sl@0: sl@0: @see TDmaPILFlags::KDmaAsymDescriptorCallback sl@0: */ sl@0: TBool iAsymDescriptorInterrupt; sl@0: /** DMAC supports separate frame completion notifications for source and sl@0: destination side. sl@0: sl@0: This capability is required for the asymmetric frame completion sl@0: callback API feature. sl@0: sl@0: ETrue here requires ETrue for iFrameInterrupt as well. sl@0: sl@0: @see TDmaPILFlags::KDmaAsymFrameCallback sl@0: */ sl@0: TBool iAsymFrameInterrupt; sl@0: sl@0: /** Reserved for future use */ sl@0: TUint32 iReserved[5]; sl@0: }; sl@0: sl@0: sl@0: struct TDmaV2TestInfo sl@0: { sl@0: enum {KMaxChannels=32}; sl@0: /** Maximum transfer size in bytes for all channels (ie. the minimum of all channels' maximum size)*/ sl@0: TUint iMaxTransferSize; sl@0: /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ sl@0: TUint iMemAlignMask; sl@0: /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ sl@0: TUint32 iMemMemPslInfo; sl@0: /** Number of test single-buffer channels */ sl@0: TInt iMaxSbChannels; sl@0: /** Pointer to array containing single-buffer test channel ids */ sl@0: TUint32 iSbChannels[KMaxChannels]; sl@0: /** Number of test double-buffer channels */ sl@0: TInt iMaxDbChannels; sl@0: /** Pointer to array containing double-buffer test channel ids */ sl@0: TUint32 iDbChannels[KMaxChannels]; sl@0: /** Number of test scatter-gather channels */ sl@0: TInt iMaxSgChannels; sl@0: /** Pointer to array containing scatter-gather test channel ids */ sl@0: TUint32 iSgChannels[KMaxChannels]; sl@0: }; sl@0: sl@0: sl@0: #endif // #ifndef __DMADEFS_H__