sl@0: ; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: ; All rights reserved. sl@0: ; This component and the accompanying materials are made available sl@0: ; under the terms of the License "Eclipse Public License v1.0" sl@0: ; which accompanies this distribution, and is available sl@0: ; at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: ; sl@0: ; Initial Contributors: sl@0: ; Nokia Corporation - initial contribution. sl@0: ; sl@0: ; Contributors: sl@0: ; sl@0: ; Description: sl@0: ; template/bootstrap/template.s sl@0: ; Template for platform specific boot code sl@0: ; sl@0: sl@0: GBLL __VARIANT_S__ ; indicates that this is platform-specific code sl@0: GBLL __TEMPLATE_S__ ; indicates which source file this is sl@0: sl@0: INCLUDE bootcpu.inc sl@0: sl@0: ; sl@0: ;******************************************************************************* sl@0: ; sl@0: ; Platform specific constant definitions sl@0: sl@0: RamBank0Base EQU 0x10000000 sl@0: RamBank0MaxSize EQU 0x00800000 sl@0: RamBank1Base EQU 0x20000000 sl@0: RamBank1MaxSize EQU 0x00000000 sl@0: sl@0: PrimaryRomBase EQU 0x00000000 sl@0: PrimaryRomSize EQU 0x00800000 sl@0: ExtensionRomBase EQU 0x08000000 sl@0: ExtensionRomSize EQU 0x00000000 sl@0: sl@0: Serial0PhysBase EQU 0x80000000 sl@0: Serial1PhysBase EQU 0x80000100 sl@0: sl@0: ; sl@0: ;******************************************************************************* sl@0: ; sl@0: sl@0: AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 sl@0: sl@0: ; sl@0: ;******************************************************************************* sl@0: ; sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Initialise Hardware sl@0: ; Initialise CPU registers sl@0: ; Determine the hardware configuration sl@0: ; Determine the reset reason. If it is wakeup from a low power mode, perform sl@0: ; whatever reentry sequence is required and jump back to the kernel. sl@0: ; Set up the memory controller so that at least some RAM is available sl@0: ; Set R10 to point to the super page or to a temporary version of the super page sl@0: ; with at least the following fields valid: sl@0: ; iBootTable, iCodeBase, iActiveVariant, iCpuId sl@0: ; In debug builds initialise the debug serial port sl@0: ; sl@0: ; Enter with: sl@0: ; R12 points to TRomHeader sl@0: ; NO STACK sl@0: ; R14 = return address (as usual) sl@0: ; sl@0: ; All registers may be modified by this call sl@0: ;******************************************************************************* sl@0: IF CFG_BootLoader sl@0: ; For bootloader we only get here on a full reset sl@0: ; Other resets will simply jump back into the previously-loaded image sl@0: EXPORT DoInitialiseHardware sl@0: DoInitialiseHardware ROUT sl@0: ELSE sl@0: EXPORT InitialiseHardware sl@0: InitialiseHardware ROUT sl@0: ENDIF sl@0: MOV r13, lr ; save return address sl@0: ADRL r1, ParameterTable ; pass address of parameter table sl@0: BL InitCpu ; initialise CPU/MMU registers sl@0: sl@0: ; Put your hardware initialising code here sl@0: sl@0: IF CFG_DebugBootRom sl@0: BL InitDebugPort sl@0: ENDIF sl@0: sl@0: ; Set up the required super page values sl@0: LDR r10, =0xC0000000 ; initial super page sl@0: LDR r0, =0x05040001 ; variant code sl@0: STR r0, [r10, #SSuperPageBase_iActiveVariant] sl@0: STR r0, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason (from hardware) sl@0: ADD r1, r10, #CpuPageOffset sl@0: STR r1, [r10, #SSuperPageBase_iMachineData] sl@0: ADRL r0, BootTable sl@0: STR r0, [r10, #SSuperPageBase_iBootTable] ; Set the boot function table sl@0: STR r12, [r10, #SSuperPageBase_iCodeBase] ; Set the base address of bootstrap code sl@0: MRC p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 (remove if no CP15) sl@0: STR r0, [r10, #SSuperPageBase_iCpuId] sl@0: sl@0: MOV pc, r13 ; return sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Notify an unrecoverable error during the boot process sl@0: ; sl@0: ; Enter with: sl@0: ; R14 = address at which fault detected sl@0: ; sl@0: ; Don't return sl@0: ;******************************************************************************* sl@0: EXPORT Fault sl@0: Fault ROUT sl@0: B BasicFaultHandler ; generic handler dumps registers via debug sl@0: ; serial port sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Reboot the system sl@0: ; sl@0: ; Enter with: sl@0: ; R0 = reboot reason code sl@0: ; sl@0: ; Don't return (of course) sl@0: ;******************************************************************************* sl@0: ALIGN 32, 0 sl@0: EXPORT RestartEntry sl@0: RestartEntry ROUT sl@0: ; save R0 parameter in HW dependent register which is preserved over reset sl@0: ; put HW specific code here to reset system sl@0: SUB pc, pc, #8 sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Get a pointer to the list of RAM banks sl@0: ; sl@0: ; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where sl@0: ; BASE is the physical base address of the bank and MAXSIZE is the maximum sl@0: ; amount of RAM which may be present in that bank. MAXSIZE should be a power of sl@0: ; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the sl@0: ; specified range of addresses and determine the actual amount of RAM if any sl@0: ; present in the bank. The list is terminated by an entry with zero size. sl@0: ; sl@0: ; The pointer returned will usually be to constant data, but could equally well sl@0: ; point to RAM if dynamic determination of the list is required. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R12 points to ROM header sl@0: ; R13 points to valid stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0 = pointer sl@0: ; Nothing else modified sl@0: ;******************************************************************************* sl@0: GetRamBanks ROUT sl@0: ADR r0, %FT1 sl@0: MOV pc, lr sl@0: 1 sl@0: DCD RamBank0Base, RamBank0MaxSize sl@0: DCD RamBank1Base, RamBank1MaxSize sl@0: DCD 0,0 ; terminator sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Get a pointer to the list of ROM banks sl@0: ; sl@0: ; The pointer returned should point to a list of entries of SRomBank structures, sl@0: ; usually declared with the ROM_BANK macro. sl@0: ; The list is terminated by a zero size entry (four zero words) sl@0: ; sl@0: ; ROM_BANK PB, SIZE, LB, W, T, RS, SS sl@0: ; PB = physical base address of bank sl@0: ; SIZE = size of bank sl@0: ; LB = linear base if override required - usually set this to 0 sl@0: ; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32) sl@0: ; T = type (see TRomType enum in kernboot.h) sl@0: ; RS = random speed sl@0: ; SS = sequential speed sl@0: ; sl@0: ; Only PB, SIZE, LB are used by the rest of the bootstrap. sl@0: ; The information given here can be modified by the SetupRomBank call, if sl@0: ; dynamic detection and sizing of ROMs is required. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R12 points to ROM header sl@0: ; R13 points to valid stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0 = pointer sl@0: ; Nothing else modified sl@0: ;******************************************************************************* sl@0: GetRomBanks ROUT sl@0: ADR r0, %FT1 sl@0: MOV pc, lr sl@0: 1 sl@0: ROM_BANK PrimaryRomBase, PrimaryRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 sl@0: ROM_BANK ExtensionRomBase, ExtensionRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 sl@0: DCD 0,0,0,0 ; terminator sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Get a pointer to the list of hardware banks sl@0: ; sl@0: ; The pointer returned should point to a list of hardware banks declared with sl@0: ; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list. sl@0: ; For the direct memory model, all hardware on the system should be mapped here sl@0: ; and the mapping will set linear address = physical address. sl@0: ; For the moving or multiple model, only the hardware required to boot the kernel sl@0: ; and do debug tracing needs to be mapped here. The linear addresses used will sl@0: ; start at KPrimaryIOBase and step up as required with the order of banks in sl@0: ; the list being maintained in the linear addresses used. sl@0: ; sl@0: ; HW_MAPPING PB, SIZE, MULT sl@0: ; This declares a block of I/O with physical base PB and address range SIZE sl@0: ; blocks each of which has a size determined by MULT. The page size used for sl@0: ; the mapping is determined by MULT. The linear address base of the mapping sl@0: ; will be the next free linear address rounded up to the size specified by sl@0: ; MULT. sl@0: ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). sl@0: ; sl@0: ; HW_MAPPING_EXT PB, SIZE, MULT sl@0: ; This declares a block of I/O with physical base PB and address range SIZE sl@0: ; blocks each of which has a size determined by MULT. The page size used for sl@0: ; the mapping is determined by MULT. The linear address base of the mapping sl@0: ; will be the next free linear address rounded up to the size specified by sl@0: ; MULT. sl@0: ; The permissions used for the mapping are determined by a BTP_ENTRY macro sl@0: ; immediately following this macro in the HW bank list or by a DCD directive sl@0: ; specifying a different standard permission type. sl@0: ; sl@0: ; HW_MAPPING_EXT2 PB, SIZE, MULT, LIN sl@0: ; This declares a block of I/O with physical base PB and address range SIZE sl@0: ; blocks each of which has a size determined by MULT. The page size used for sl@0: ; the mapping is determined by MULT. The linear address base of the mapping sl@0: ; is specified by the LIN parameter. sl@0: ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). sl@0: ; sl@0: ; HW_MAPPING_EXT3 PB, SIZE, MULT, LIN sl@0: ; This declares a block of I/O with physical base PB and address range SIZE sl@0: ; blocks each of which has a size determined by MULT. The page size used for sl@0: ; the mapping is determined by MULT. The linear address base of the mapping sl@0: ; is specified by the LIN parameter. sl@0: ; The permissions used for the mapping are determined by a BTP_ENTRY macro sl@0: ; immediately following this macro in the HW bank list or by a DCD directive sl@0: ; specifying a different standard permission type. sl@0: ; sl@0: ; Configurations without an MMU need not implement this function. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R12 points to ROM header sl@0: ; R13 points to valid stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0 = pointer sl@0: ; Nothing else modified sl@0: ;******************************************************************************* sl@0: GetHwBanks ROUT sl@0: ADR r0, %FT1 sl@0: MOV pc, lr sl@0: 1 sl@0: IF CFG_MMDirect sl@0: ; for direct model we must map all peripherals here sl@0: ; use section mappings to reduce number of page tables required sl@0: HW_MAPPING 0x00100000, 31, HW_MULT_1M ; 0x00100000 - 0x01FFFFFF sl@0: HW_MAPPING 0x08000000, 32, HW_MULT_1M ; 0x08000000 - 0x09FFFFFF sl@0: HW_MAPPING 0x80000000, 1, HW_MULT_1M ; 0x80000000 - 0x800FFFFF sl@0: HW_MAPPING 0x90000000, 1, HW_MULT_1M ; 0x90000000 - 0x900FFFFF sl@0: HW_MAPPING 0xA0000000, 1, HW_MULT_1M ; 0xA0000000 - 0xA00FFFFF sl@0: HW_MAPPING 0xB0000000, 1, HW_MULT_1M ; 0xB0000000 - 0xB00FFFFF sl@0: HW_MAPPING 0xB0100000, 1, HW_MULT_1M ; 0xB0100000 - 0xB01FFFFF sl@0: ELSE sl@0: HW_MAPPING 0x80000000, 1, HW_MULT_4K ; 0x80000000 - 0x80000FFF mapped at KPrimaryIOBase + 0 sl@0: HW_MAPPING 0x80010000, 1, HW_MULT_4K ; 0x80010000 - 0x80010FFF mapped at KPrimaryIOBase + 0x1000 sl@0: HW_MAPPING 0x80020000, 1, HW_MULT_64K ; 0x80020000 - 0x8002FFFF mapped at KPrimaryIOBase + 0x10000 sl@0: HW_MAPPING_EXT 0x90000000, 1, HW_MULT_4K ; 0x90000000 - 0x90000FFF mapped at KPrimaryIOBase + 0x20000 ... sl@0: DCD BTP_Rom ; ... with same permissions as ROM sl@0: ENDIF sl@0: DCD 0 ; terminator sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Set up RAM bank sl@0: ; sl@0: ; Do any additional RAM controller initialisation for each RAM bank which wasn't sl@0: ; done by InitialiseHardware. sl@0: ; Called twice for each RAM bank :- sl@0: ; First with R3 = 0xFFFFFFFF before bank has been probed sl@0: ; Then, if RAM is present, with R3 indicating validity of each byte lane, ie sl@0: ; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc. sl@0: ; For each call R1 specifies the bank physical base address. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R12 points to ROM header sl@0: ; R13 points to stack sl@0: ; R1 = physical base address of bank sl@0: ; R3 = width (bottom 4 bits indicate validity of byte lanes) sl@0: ; 0xffffffff = preliminary initialise sl@0: ; sl@0: ; Leave with : sl@0: ; No registers modified sl@0: ;******************************************************************************* sl@0: SetupRamBank ROUT sl@0: MOV pc, lr sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Set up ROM bank sl@0: ; sl@0: ; Do any required autodetection and autosizing of ROMs and any additional memory sl@0: ; controller initialisation for each ROM bank which wasn't done by sl@0: ; InitialiseHardware. sl@0: ; sl@0: ; The first time this function is called R11=0 and R0 points to the list of sl@0: ; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup sl@0: ; before autodetection begins. sl@0: ; sl@0: ; This function is subsequently called once for each ROM bank with R11 pointing sl@0: ; to the current information held about that ROM bank (SRomBank structure). sl@0: ; The structure pointed to by R11 should be updated with the size and width sl@0: ; determined. The size should be set to zero if there is no ROM present in the sl@0: ; bank. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R12 points to ROM header sl@0: ; R13 points to stack sl@0: ; R11 points to SRomBank info for this bank sl@0: ; R11 = 0 for preliminary initialise (all banks) sl@0: ; sl@0: ; Leave with : sl@0: ; Update SRomBank info with detected size/width sl@0: ; Set the size field to 0 if the ROM bank is absent sl@0: ; Can modify R0-R4 but not other registers sl@0: ; sl@0: ;******************************************************************************* sl@0: SetupRomBank ROUT sl@0: MOV pc, lr sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Reserve physical memory sl@0: ; sl@0: ; Reserve any physical RAM needed for platform-specific purposes before the sl@0: ; bootstrap begins allocating RAM for page tables/kernel data etc. sl@0: ; sl@0: ; There are two methods for this: sl@0: ; 1. The function ExciseRamArea may be used. This will remove a contiguous sl@0: ; region of physical RAM from the RAM bank list. That region will never sl@0: ; again be identified as RAM. sl@0: ; 2. A list of excluded physical address ranges may be written at [R11]. sl@0: ; This should be a list of (base,size) pairs terminated by a (0,0) entry. sl@0: ; This RAM will still be identified as RAM by the kernel but will not sl@0: ; be allocated by the bootstrap and will subsequently be marked as sl@0: ; allocated by the kernel immediately after boot. sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R11 indicates where preallocated RAM list should be written. sl@0: ; R12 points to ROM header sl@0: ; R13 points to stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0-R3 may be modified. Other registers should be preserved. sl@0: ;******************************************************************************* sl@0: ReservePhysicalMemory ROUT sl@0: MOV pc, lr sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Return parameter specified by R0 (see TBootParam enum) sl@0: ; sl@0: ; Enter with : sl@0: ; R0 = parameter number sl@0: ; sl@0: ; Leave with : sl@0: ; If parameter value is supplied, R0 = value and N flag clear sl@0: ; If parameter value is not supplied, N flag set. In this case the sl@0: ; parameter may be defaulted or the system may fault. sl@0: ; R0,R1,R2 modified. No other registers modified. sl@0: ; sl@0: ;******************************************************************************* sl@0: GetParameters ROUT sl@0: ADR r1, ParameterTable sl@0: B FindParameter sl@0: ParameterTable sl@0: ; Include any parameters specified in TBootParam enum here sl@0: ; if you want to override them. sl@0: DCD BPR_UncachedLin, 0 ; parameter number, parameter value sl@0: IF :DEF: CFG_CPU_ARM1136 :LAND: (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_364296_FIXED) sl@0: DCD BPR_FinalMMUCRSet, ExtraMMUCR + MMUCR_FI sl@0: DCD BPR_AuxCRSet, DefaultAuxCRSet + 0x80000000 sl@0: ENDIF sl@0: DCD -1 ; terminator sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Do final platform-specific initialisation before booting the kernel sl@0: ; sl@0: ; Typical uses for this call would be: sl@0: ; 1. Mapping cache flushing areas sl@0: ; 2. Setting up pointers to routines in the bootstrap which are used by sl@0: ; the variant or drivers (eg idle code). sl@0: ; sl@0: ; Enter with : sl@0: ; R10 points to super page sl@0: ; R11 points to TRomImageHeader for the kernel sl@0: ; R12 points to ROM header sl@0: ; R13 points to stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0-R9 may be modified. Other registers should be preserved. sl@0: ; sl@0: ;******************************************************************************* sl@0: FinalInitialise ROUT sl@0: STMFD sp!, {lr} sl@0: sl@0: IF CFG_Template sl@0: sl@0: ; set up main cache flush area sl@0: MOV r1, #0xE0000000 ; physical address sl@0: IF CFG_MMDirect sl@0: MOV r0, r1 ; direct, linear = physical sl@0: ELSE sl@0: LDR r0, =KDCacheFlushArea ; linear sl@0: ENDIF sl@0: STR r0, [r10, #SSuperPageBase_iDCacheFlushArea] sl@0: MOV r2, #BTP_MainCache ; permissions sl@0: MOV r3, #0x100000 ; size sl@0: MOV r4, #20 ; use section sl@0: BL MapContiguous sl@0: sl@0: ; set up mini cache flush area sl@0: ADD r1, r1, r3 ; physical address sl@0: ADD r0, r0, r3 ; linear sl@0: STR r0, [r10, #SSuperPageBase_iAltDCacheFlushArea] sl@0: MOV r2, #BTP_MiniCache ; permissions sl@0: BL MapContiguous sl@0: sl@0: MOV r3, #0x80000 ; wrap for cache flush sl@0: STR r3, [r10, #SSuperPageBase_iDCacheFlushWrap] sl@0: STR r3, [r10, #SSuperPageBase_iAltDCacheFlushWrap] sl@0: sl@0: ; set up idle code address sl@0: ADR r0, IdleCode sl@0: ADD r5, r10, #CpuPageOffset sl@0: STR r0, [r5, #CPUPage_Idle] sl@0: sl@0: ENDIF sl@0: sl@0: LDMFD sp!, {pc} sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; Output a character to the debug port sl@0: ; sl@0: ; Enter with : sl@0: ; R0 = character to output sl@0: ; R13 points to valid stack sl@0: ; sl@0: ; Leave with : sl@0: ; nothing modified sl@0: ;******************************************************************************* sl@0: DoWriteC ROUT sl@0: IF CFG_DebugBootRom sl@0: STMFD sp!, {r1,lr} sl@0: BL GetDebugPortBase sl@0: sl@0: ; wait for debug port to be ready for data sl@0: ; output character to debug port sl@0: sl@0: LDMFD sp!, {r1,pc} sl@0: ELSE sl@0: MOV pc, lr sl@0: ENDIF sl@0: sl@0: IF CFG_DebugBootRom sl@0: sl@0: ;******************************************************************************* sl@0: ; Initialise the debug port sl@0: ; sl@0: ; Enter with : sl@0: ; R12 points to ROM header sl@0: ; There is no valid stack sl@0: ; sl@0: ; Leave with : sl@0: ; R0-R2 modified sl@0: ; Other registers unmodified sl@0: ;******************************************************************************* sl@0: InitDebugPort ROUT sl@0: MOV r0, lr sl@0: BL GetDebugPortBase ; r1 = base address of debug port sl@0: sl@0: ; set up debug port sl@0: sl@0: MOV pc, r0 sl@0: sl@0: ;******************************************************************************* sl@0: ; Get the base address of the debug UART sl@0: ; sl@0: ; Enter with : sl@0: ; R12 points to ROM header sl@0: ; There may be no stack sl@0: ; sl@0: ; Leave with : sl@0: ; R1 = base address of port sl@0: ; No other registers modified sl@0: ;******************************************************************************* sl@0: GetDebugPortBase ROUT sl@0: LDR r1, [r12, #TRomHeader_iDebugPort] sl@0: CMP r1, #1 sl@0: BNE %FA1 ; skip if not port 1 sl@0: GET_ADDRESS r1, Serial1PhysBase, Serial1LinBase sl@0: MOV pc, lr sl@0: 1 sl@0: GET_ADDRESS r1, Serial0PhysBase, Serial0LinBase sl@0: MOV pc, lr sl@0: sl@0: ENDIF ; CFG_DebugBootRom sl@0: sl@0: sl@0: sl@0: sl@0: sl@0: ;******************************************************************************* sl@0: ; BOOT FUNCTION TABLE sl@0: ;******************************************************************************* sl@0: sl@0: BootTable sl@0: DCD DoWriteC ; output a debug character sl@0: DCD GetRamBanks ; get list of RAM banks sl@0: DCD SetupRamBank ; set up a RAM bank sl@0: DCD GetRomBanks ; get list of ROM banks sl@0: DCD SetupRomBank ; set up a ROM bank sl@0: DCD GetHwBanks ; get list of HW banks sl@0: DCD ReservePhysicalMemory ; reserve physical RAM if required sl@0: DCD GetParameters ; get platform dependent parameters sl@0: DCD FinalInitialise ; Final initialisation before booting the kernel sl@0: IF :LNOT: CFG_MMUPresent ; no mmu, so use stub version ... sl@0: DCD AllocatorStub ; allocate memory sl@0: ELSE sl@0: DCD HandleAllocRequest ; allocate memory sl@0: DCD GetPdeValue ; usually in generic code sl@0: DCD GetPteValue ; usually in generic code sl@0: DCD PageTableUpdate ; usually in generic code sl@0: DCD EnableMmu ; Enable the MMU (usually in generic code) sl@0: ENDIF sl@0: sl@0: ; These entries specify the standard MMU permissions for various areas sl@0: ; They can be omitted if MMU is absent sl@0: IF CFG_MMUPresent sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; ROM sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; kernel data/stack/heap sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; super page/CPU page sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page directory/tables sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; exception vectors sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; hardware registers sl@0: DCD 0 ; unused (minicache flush) sl@0: DCD 0 ; unused (maincache flush) sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page table info sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; user RAM sl@0: BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, 0 ; temporary identity mapping sl@0: BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; uncached sl@0: ENDIF sl@0: sl@0: sl@0: END