sl@0: // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). sl@0: // All rights reserved. sl@0: // This component and the accompanying materials are made available sl@0: // under the terms of the License "Eclipse Public License v1.0" sl@0: // which accompanies this distribution, and is available sl@0: // at the URL "http://www.eclipse.org/legal/epl-v10.html". sl@0: // sl@0: // Initial Contributors: sl@0: // Nokia Corporation - initial contribution. sl@0: // sl@0: // Contributors: sl@0: // sl@0: // Description: sl@0: // template\template_assp\i2spsl.cpp sl@0: // sl@0: // sl@0: sl@0: #include sl@0: #include sl@0: sl@0: // TO DO: (mandatory) sl@0: // If your ASIC supports multiple I2S interfaces you need to design the most appropriate way of handling that: sl@0: // - it is possible that a common register per function is used on some of the functions, e.g. a single Control sl@0: // Register is used to select Master/Slave roles, Transmitter/Receiver/Bidirectional/Controller mode, word sl@0: // length etc for all interfaces supported. In this case handling the interface Id typically involves the use sl@0: // of shifts and masks; sl@0: // - some functions can never be covered by a single register common to all interfaces (e.g. the transmit/receive sl@0: // registers). Even if it was possible to use single registers to cover a number of interfaces the ASIC designer sl@0: // may decide to have separate registers for each interface. In this case each of the below APIs could be implemented sl@0: // as a switch(interface)-case and then use different sets of register addresses for each interface. This model makes sl@0: // sense when a single developer is responsible for implementing all interfaces (typically in a single source file). sl@0: // - when each interface is implemented independently it makes sense to separate the implementation into a interface sl@0: // independent layer and a specific layer and redirect each call from the interface independent layer into the relavant sl@0: // interface. This is exemplified with the NAVIENGINE implementation. sl@0: // sl@0: sl@0: enum TIs2Panic sl@0: { sl@0: ECalledFromIsr sl@0: }; sl@0: sl@0: EXPORT_C TInt I2s::ConfigureInterface(TInt aInterfaceId, TDes8* aConfig) sl@0: // sl@0: // Configures the interface: its type (Transmitter/Receiver/Bidirectional/Controller) and the role played by it (Master/Slave). sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Extracts the configuration information from aConfig and programs the relevant registers for the interface identified by aInterfaceId. sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::GetInterfaceConfiguration(TInt aInterfaceId, TDes8& aConfig) sl@0: // sl@0: // Reads the current configuration. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // Reads the relevant registers and assembles configuration information to be returned in aConfig. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::SetSamplingRate(TInt aInterfaceId, TI2sSamplingRate aSamplingRate) sl@0: // sl@0: // Sets the sampling rate. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Programs the required sampling rate onto the relevant registers for the interface identified by aInterfaceId . sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::GetSamplingRate(TInt aInterfaceId, TInt& aSamplingRate) sl@0: // sl@0: // Reads the sampling rate. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // Reads the relevant registers to obtain the currently programmed sampling rate to be returned in aSamplingRate. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::SetFrameLengthAndFormat(TInt aInterfaceId, TI2sFrameLength aFrameLength, TInt aLeftFramePhaseLength) sl@0: // sl@0: // Sets the frame format. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (mandatory) sl@0: // sl@0: // If the interface only allows symmetrical frame lengths this function programs the required sl@0: // overall frame length onto the relevant registers for the interface identified by aInterfaceId. sl@0: // In this case aLeftFramePhaseLength can be ignored. sl@0: // If the interface supports asymmetrical frame lengths, calculates the righ frame length as sl@0: // (aFrameLength-aLeftFramePhaseLength) and programs both the left and right frame lengths onto sl@0: // the relevant registers for the interface identified by aInterfaceId. sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::GetFrameFormat(TInt aInterfaceId, TInt& aLeftFramePhaseLength, TInt& aRightFramePhaseLength) sl@0: // sl@0: // Reads the frame format. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the interface only supports symmetrical frame lengths this function reads the relevant registers to obtain sl@0: // the currently programmed overall frame length for the interface identified by aInterfaceId: it returns the same sl@0: // value in both aLeftFramePhaseLength and aRightFramePhaseLength (that is overal frame length/2). sl@0: // If the interface supports asymmetrical frame lngths, reads the appropriate registers to obtain the left and right sl@0: // frame lengths to be returned in aLeftFramePhaseLength and aRightFramePhaseLength. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::SetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sSampleLength aSampleLength) sl@0: // sl@0: // Sets the sample length for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Programs the required sample length for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId . sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::GetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aSampleLength) sl@0: // sl@0: // Reads the sample length for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // Reads the relevant registers to obtain the sample length for the frame phase specified (left or right) to be returned in aSampleLength. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::SetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aDelayCycles) sl@0: // sl@0: // Sets the number of delay cycles for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function programs the required sl@0: // delay cycles for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId . sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::GetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aDelayCycles) sl@0: // sl@0: // Reads the sample length for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function reads the relevant sl@0: // registers to obtain the number of delay cycles for the frame phase specified (left or right) to be returned in aSampleLength. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::ReadReceiveRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData) sl@0: // sl@0: // Reads the receive data register for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Reads the contents of the receive register to obtain the data for the frame phase specified (left or right) to be returned in aData. sl@0: // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the sl@0: // function returns the contents of the single register. sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::WriteTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aData) sl@0: // sl@0: // Writes to the transmit data register for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (mandatory) sl@0: // sl@0: // Writes the Audio data passed in aData to the transmit register for the frame phase specified (left or right) for the interface identified sl@0: // by aInterfaceId. sl@0: // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored and the sl@0: // function writes to the single register. sl@0: // sl@0: return KErrNone; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::ReadTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData) sl@0: // sl@0: // Reads the transmit data register for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // Reads the contents of the transmit register to obtain the data for the frame phase specified (left or right) to be returned in aData. sl@0: // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the sl@0: // function returns the contents of the single transmit register. sl@0: // If the implementation does not support reading the transmit register simply return KErrNotSupported. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::ReadRegisterModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags) sl@0: // sl@0: // Reads the Register PIO access mode status flags for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports Register PIO mode this function reads the contents of the Register PIO mode status register to obtain sl@0: // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags. sl@0: // If the implementation does not support Register PIO mode simply return KErrNotSupported. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::EnableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) sl@0: // sl@0: // Enables Register PIO access mode related interrupts for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports Register PIO mode this function enables the mode interrupts specified by the bitmask aInterrupt sl@0: // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the sl@0: // corresponding interrupts sl@0: // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. sl@0: // If the implementation does not support Register PIO mode simply return KErrNotSupported. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::DisableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) sl@0: // sl@0: // Disables Register PIO access mode related interrupts for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports Register PIO mode this function disables the mode interrupts specified by the bitmask aInterrupt sl@0: // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the sl@0: // corresponding interrupts sl@0: // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. sl@0: // If the implementation does not support Register PIO mode simply return KErrNotSupported. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::IsRegisterInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) sl@0: // sl@0: // Reads the Register PIO access mode interrupt mask for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports Register PIO mode this function reads the relevant registers to find out which mode interrupts sl@0: // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled. sl@0: // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled sl@0: // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. sl@0: // If the implementation does not support Register PIO mode simply return KErrNotSupported. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::EnableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask) sl@0: // sl@0: // Enables receive and/or transmit FIFO on a per frame phase basis. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function enables the FIFOs for the directions specified in the bitmask aFifoMask sl@0: // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" enable the corresponding FIFO. sl@0: // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored. sl@0: // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::DisableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask) sl@0: // sl@0: // Disables receive and/or transmit FIFO on a per frame phase basis. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function disables the FIFOs for the directions specified in the bitmask aFifoMask sl@0: // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" disable the corresponding FIFO. sl@0: // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored. sl@0: // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::IsFIFOEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) sl@0: // sl@0: // Reads the enabled state of a frame phase's FIFOs. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function reads the relevant registers to find out which FIFOs sl@0: // are enabled (Transmit and/or Receive FIFO) for the frame phase specified (left or right), and returns a bitmask of enabled FIFOs in aEnabled. sl@0: // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled sl@0: // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the FIFO is enabled. sl@0: // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignore. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::SetFIFOThreshold(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt aThreshold) sl@0: // sl@0: // Sets the receive or transmit FIFO threshold on a per frame phase basis. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function sets the FIFO threshold for the direction specified in aDirection sl@0: // (Transmit or Receive) for the frame phase specified (left or right). sl@0: // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aDirection can be ignored. sl@0: // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::ReadFIFOModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags) sl@0: // sl@0: // Reads the FIFO PIO access mode status flags for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function reads the contents of the FIFO mode status register to obtain sl@0: // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags. sl@0: // A bit set to "1" indicates the condition described by the corresponding flag is occurring. sl@0: // If the implementation has a combined receive/transmit FIFO then aFlags should be set according to which operation (receive/transmit) is sl@0: // currently undergoing. sl@0: // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::EnableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) sl@0: // sl@0: // Enables FIFO related interrupts for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function enables the mode interrupts specified by the bitmask aInterrupt sl@0: // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the sl@0: // corresponding interrupts sl@0: // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::DisableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) sl@0: // sl@0: // Disables FIFO related interrupts for a frame phase. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function disables the mode interrupts specified by the bitmask aInterrupt sl@0: // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the sl@0: // corresponding interrupts sl@0: // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::IsFIFOInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) sl@0: // sl@0: // Reads the FIFO interrupt masks for a frame phase. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function reads the relevant registers to find out which mode interrupts sl@0: // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled. sl@0: // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled sl@0: // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::ReadFIFOLevel(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt& aLevel) sl@0: // sl@0: // Reads the receive or transmit FIFO current level on a per frame phase basis. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO mode this function reads the relevant registers to find out the current FIFO level sl@0: // for the direction specified and for the frame phase specified (left or right), and returns it in aLevel. sl@0: // If the implementation has a combined receive/transmit FIFO then aDirection is ignored. sl@0: // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::EnableDMA(TInt aInterfaceId, TInt aFifoMask) sl@0: // sl@0: // Enables receive and/or transmit DMA. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO DMA mode this function enables DMA in the directions (Transmit and/or Receive) specified sl@0: // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" enable DMA. sl@0: // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::DisableDMA(TInt aInterfaceId, TInt aFifoMask) sl@0: // sl@0: // Disables receive and/or transmit DMA. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO DMA mode this function disables DMA in the directions (Transmit and/or Receive) specified sl@0: // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" disable DMA. sl@0: // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::IsDMAEnabled(TInt aInterfaceId, TInt& aEnabled) sl@0: // sl@0: // Reads the enabled state of DMA. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the implementation supports FIFO DMA mode this function reads the relevant registers to find out which directions sl@0: // (Transmit and/or Receive) DMA is enabled for the frame phase specified (left or right), and returns a bitmask of enabled sl@0: // directions in aEnabled. A bit set to "1" indicates DMA is enabled for the corresponding direction. sl@0: // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the DMA is enabled. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::Start(TInt aInterfaceId, TInt aDirection) sl@0: // sl@0: // Starts data transmission and/or data reception unless interface is a Controller; sl@0: // if the device is also a Master, starts generation of data synchronisation signals. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // Programs the appropriate registers to start operation in the direction specified by aDirection. sl@0: // Should check if the interface has been configured coherently. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::Stop(TInt aInterfaceId, TInt aDirection) sl@0: // sl@0: // Stops data transmission and/or data reception; sl@0: // if device is also a Master, stops generation of data synchronisation signals. sl@0: // sl@0: { sl@0: __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); sl@0: // TO DO: (optional) sl@0: // sl@0: // If the interface has been started, programs the appropriate registers to stop operation in the direction specified by aDirection. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: EXPORT_C TInt I2s::IsStarted(TInt aInterfaceId, TI2sDirection aDirection, TBool& aStarted) sl@0: // sl@0: // Checks if a transmission or a reception is underway. sl@0: // sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // Reads the appropriate registers to check if the interface speficied by aInterfaceId is started in the direction sl@0: // specified by aDirection. Returns teh result (as TRUE or FALSE) in aStarted. sl@0: // If the interface is a Controller and a bus operation is underway, ETrue should be returned regardless of aDirection. sl@0: // sl@0: return KErrNotSupported; sl@0: } sl@0: sl@0: // dll entry point.. sl@0: DECLARE_STANDARD_EXTENSION() sl@0: { sl@0: // TO DO: (optional) sl@0: // sl@0: // The Kernel extension entry point: if your interface requires any early intialisation do it here. sl@0: // sl@0: return KErrNone; sl@0: }