1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32\memmodel\epoc\multiple\arm\xsched.cia
22 #define iMState iWaitLink.iSpare1
24 //#define __DEBUG_BAD_ADDR
26 #ifdef __REQUEST_COMPLETE_MACHINE_CODED__
28 extern "C" void __DebugMsgRequestComplete(TInt a0, TInt a1, TInt a2);
29 extern "C" void __DebugMsgReqCompleteWrite(TInt a0, TInt a1, TInt a2);
32 __NAKED__ void DThread::RequestComplete(TRequestStatus*& /*aStatus*/, TInt /*aReason*/)
34 // Signal this threads request semaphore.
35 // Enter with system locked, return with system unlocked.
38 ASM_DEBUG2(DThreadRequestComplete,r0,lr);
40 asm("ldr r3, [r1] "); // r3 points to TRequestStatus
42 asm("str r12, [r1] "); // aStatus=NULL
44 asm(".global _asm_RequestComplete ");
45 asm("_asm_RequestComplete: ");
47 #ifdef BTRACE_REQUESTS
48 asm("stmdb sp!,{r0-r3,lr}");
50 asm("mov r3,r2"); // arg3 = aReason
51 asm("mov r2,r1"); // arg2 = aStatus
52 asm("add r1,r0,#%a0" : : "i" _FOFF(DThread,iNThread)); // arg1 = &this->iNThread
53 asm("ldr r0,_threadReqequestCompleteTraceHeader"); // arg0 = header
54 asm("bl " CSM_ZN6BTrace4OutXEmmmm);
55 asm("ldmia sp!,{r0-r3,lr}");
58 ASM_DEBUG3(RequestComplete,r0,r3,r2);
60 // r0 -> DThread, r3 -> TRequestStatus in user space, r2 = aReason
61 asm("ldrb r12, [r0, #%a0]" : : "i" _FOFF(DThread,iMState));
62 asm("ldr r1, __TheScheduler "); // r1->TheScheduler
63 asm("stmfd sp!, {r4-r9} ");
64 asm("add r6, r0, #%a0" : : "i" _FOFF(DThread,iNThread)); // r6->target NThread
65 asm("ldr r4, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace)); // r4->current process
66 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DThread,iOwningProcess)); // r0->target process
67 asm("cmp r12, #%a0" : : "i" (DThread::EDead)); // test if iMState=EDead
68 asm("beq req_complete_dead_thread "); // if it is, finished
69 asm("ldr r5, [r1, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r5->current NThread
71 asm("mrc p15, 0, r7, c2, c0, 0 "); // save TTBR0
72 asm("ldr r9, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iLocalPageDir)); // r9 -> target process page directory
73 asm("ldr r8, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r8 = target ASID
74 asm("and r12, r7, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r12 = page table cache attributes
75 asm("orr r9, r9, r12 "); // r9 = target process TTBR0 value
76 asm("mrs r12, cpsr "); // save CPSR
77 CPSIDAIF; // disable all interrupts
78 asm("mcr p15, 0, r12, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs)
79 UPDATE_PW_CACHING_ATTRIBUTES(,r9); // ERRATUM 1136_317041
80 asm("mcr p15, 0, r9, c2, c0, 0 "); // change TTBR0
81 asm("mcr p15, 0, r8, c13, c0, 1 "); // change ASID
83 #if defined(__CPU_ARM11MP__)
84 // On other platforms, tha ASID change above has already flushed the branch prediction buffers
85 asm("mcr p15, 0, r12, c7, c5, 6 "); // flush BTAC
88 asm("str r0, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace));
89 asm("str r0, [r5, #%a0]" : : "i" _FOFF(NThread,iAddressSpace));
90 asm("msr cpsr, r12 "); // restore interrupts
92 USER_MEMORY_GUARD_OFF(,r12,r12);
93 asm(".global __magic_address_reqc "); // NOTE: Z flag always clear here
94 asm("__magic_address_reqc: "); // this instruction is magically immune from exceptions
95 asm("strt r2, [r3] "); // store completion code with user permissions
96 // MAY MODIFY Z and R12
97 USER_MEMORY_GUARD_ON(,r12,r12);
99 asm("mrs r12, cpsr "); // save CPSR and Z flag which indicates whether write succeeded
100 asm("ldr r2, [r4, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r2 = current process ASID
101 CPSIDAIF; // disable all interrupts
102 asm("mcr p15, 0, r12, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs)
103 UPDATE_PW_CACHING_ATTRIBUTES(,r7); // ERRATUM 1136_317041
104 asm("mcr p15, 0, r7, c2, c0, 0 "); // restore TTBR0
105 asm("mcr p15, 0, r2, c13, c0, 1 "); // restore ASID
107 #if defined(__CPU_ARM11MP__)
108 // On other platforms, tha ASID change above has already flushed the branch prediction buffers
109 asm("mcr p15, 0, r12, c7, c5, 6 "); // flush BTAC
112 asm("str r4, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace));
113 asm("str r4, [r5, #%a0]" : : "i" _FOFF(NThread,iAddressSpace));
114 asm("msr cpsr, r12 "); // restore interrupts and Z flag
116 #ifdef __DEBUG_BAD_ADDR
117 asm("moveq r12, #0xde000000 ");
118 asm("streq r12, [r12, #0xaf] "); //HACK-CRASH SYSTEM IF WRITE FAILED
121 asm("movne r0, r6 "); // if write OK, r0->iNThread
122 asm("req_complete_dead_thread: "); // NOTE: Z flag set if thread dead
123 asm("ldmfd sp!, {r4-r9} "); // restore registers whether OK or not
124 asm("movne r1, #0 ");
125 asm("bne " CSM_ZN5NKern19ThreadRequestSignalEP7NThreadP10NFastMutex );
126 asm("b " CSM_ZN5NKern12UnlockSystemEv); // if any error, unlock system and return
128 #ifdef BTRACE_REQUESTS
129 asm("_threadReqequestCompleteTraceHeader:");
130 asm(".word %a0" : : "i" (BTRACE_HEADER_C(16,BTrace::ERequests,BTrace::ERequestComplete)));
135 GLDEF_C __NAKED__ void DoProcessSwitch()
137 // Enter and return with kernel locked
138 // r0->scheduler, r3->current thread
139 // r5->old process, r9->new process
140 // Return with r2 = (r2<<8) | ASID
141 // Must preserve r0,r3, can modify other registers
143 // This code is optimized with the ARM1136 static branch prediction scheme in mind.
144 // Unusually, ARM1136 flushes the BTAC on every ContextID write whether it needs to
145 // or not! We only need to flush the prefetch if there's differing local code... -jls
147 asm("cmp r5, r9 "); // check if current address space correct
148 asm("beq address_switch_done"); // skip if address space change not required
150 asm("mrc p15, 0, r1, c2, c0, 0 "); // get TTBR0
151 asm("ldr r4, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iLocalPageDir));
152 asm("and r1, r1, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r1 = page table cache attributes
153 asm("str r9, [r0, #%a0]" : : "i" _FOFF(TScheduler, iAddressSpace));
154 asm("orr r4, r4, r1 "); // r4 = new TTBR0 value
155 asm("ldr r1, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iSelfModChunks));
156 asm("mcr p15, 0, r4, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs)
157 UPDATE_PW_CACHING_ATTRIBUTES(,r4); // ERRATUM 1136_317041
158 asm("mcr p15, 0, r4, c2, c0, 0 "); // set TTBR0 - no TLB flush required due to ASID
159 asm("cmp r1, #0"); // do we have selfmod chunks? (probably not)
160 asm("bgt gotchunks "); // yes, so we need to look closer (will predict not taken)
162 asm("address_switch_done:");
163 asm("ldr r4, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iOsAsid));
164 asm("ldr r6, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasLinAddr)-_FOFF(DThread, iNThread)) );
165 asm("orr r2, r4, r2, lsl #8 "); // r2 = original r2 << 8 | ASID
166 asm("cmp r6, #0"); // check if thread has an alias in place
167 asm("bne got_alias");
172 asm("ldr r7, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasPde)-_FOFF(DThread, iNThread)) );
173 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[1])); // Alias remap old address
174 asm("ldr r8, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasPdePtr)-_FOFF(DThread, iNThread)) );
175 asm("orr r6, r6, r4"); // put ASID into address for TLB flush later...
176 asm("eor r1, r1, r7 "); // compare old address with pde
177 asm("cmp r1, #0x1000 "); // if result only has perm bits, addresses were the same
178 asm("blo remap_alias ");
180 asm("alias_remap_done: ");
181 asm("str r7, [r8]"); // restore PDE for alias
183 CACHE_MAINTENANCE_PDE_PTE_UPDATED(r8);
190 FLUSH_DTLB_ENTRY(,r6); // flush TLB for aliased page
194 asm("remap_alias: ");
195 asm("ldr r7, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[2])); // Alias remap new address
196 asm("orr r7, r1, r7 "); // r1 has perm bits, left over from xor above
197 asm("b alias_remap_done ");
200 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[0])); // address of last selfmod process
201 asm("cmp r1, r9"); // was it whoever's next up? (probably)
202 asm("beq address_switch_done");
203 asm("mcr p15, 0, r4, c7, c5, 4 "); // prefetch flush before returning
204 #ifdef __CPU_HAS_UNFLUSHED_BTB
208 FLUSH_BTB(,r1); // flush the dynamic branch predictor table
211 asm("str r9, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[0])); // update it
212 asm("b address_switch_done");
214 asm("__TheScheduler: ");
215 asm(".word TheScheduler ");
219 Restore the address space of the current thread so it matches its owning process.
221 __NAKED__ void DMemModelThread::RestoreAddressSpace()
223 asm("ldr r12, __TheScheduler "); // r12->TheScheduler
224 asm("ldr r3, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r3->current NThread
225 asm("ldr r0, [r3, #%a0]" : : "i" (-_FOFF(DThread,iNThread)+_FOFF(DThread,iOwningProcess))); // r0->process
227 // switch address space to process r0...
228 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iLocalPageDir));// r1->process page directory
229 asm("mrc p15, 0, r2, c2, c0, 0 "); // get TTBR0
230 asm("and r2, r2, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r2 = page table cache attributes
231 asm("orr r1, r1, r2 "); // r1 = new TTBR0 value
232 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r2 = ASID
233 CPSIDAIF; // disable all interrupts
234 asm("mcr p15, 0, r2, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs)
235 UPDATE_PW_CACHING_ATTRIBUTES(,r1); // ERRATUM 1136_317041
236 asm("mcr p15, 0, r1, c2, c0, 0 "); // change TTBR0
237 asm("mcr p15, 0, r2, c13, c0, 1 "); // change ASID
239 #if defined(__CPU_ARM11MP__)
240 // On other platforms, tha ASID change above has already flushed the branch prediction buffers
241 asm("mcr p15, 0, r2, c7, c5, 6 "); // flush BTAC
244 asm("str r0, [r12, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace));
245 asm("str r0, [r3, #%a0]" : : "i" _FOFF(NThread,iAddressSpace));
246 CPSIEAIF; // enable all interrupts