1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // eka\include\kernel\kernboot.h
15 // Interface between bootstrap and kernel
16 // This header file should contain only POD structures with members having
17 // only the following types:
18 // TInt8, TUint8, TInt16, TUint16, TInt32, TUint32, TInt64, TUint64
19 // TInt, TUint, TLinAddr, T* where T is an alphanumeric string
20 // If TInt64/TUint64 are used, manual padding should be used to guarantee
21 // that these start on an 8 byte boundary.
23 // WARNING: This file contains some APIs which are internal and are subject
24 // to change without notice. Such APIs should therefore not be used
25 // outside the Kernel and Hardware Services package.
28 #ifndef __KERNBOOT_H__
29 #define __KERNBOOT_H__
32 The part of SSuperPageBase class.
33 Holds the stack base address and the stack size of IRQ, FIQ, Undefined & Abort cpu modes.
40 void* iIrqStackBase; /**< Stack base address of IRQ CPU mode*/
41 TInt iIrqStackSize; /**< Stack size of IRQ CPU mode*/
42 void* iFiqStackBase; /**< Stack base address of FIQ CPU mode*/
43 TInt iFiqStackSize; /**< Stack size of FIQ CPU mode*/
44 void* iUndStackBase; /**< Stack base address of Undefined CPU mode*/
45 TInt iUndStackSize; /**< Stack size of Undefined CPU mode*/
46 void* iAbtStackBase; /**< Stack base address of Abort CPU mode*/
47 TInt iAbtStackSize; /**< Stack size of Abort CPU mode*/
50 /** The part of the super page used by the bootstrap.
52 Optional fields in this structure may be set to
53 KSuperPageAddressFieldUndefined (-1) if not used during boot time.
54 Current optional fields are: iSmrData
61 TInt iRamDriveSize; /**< @internalComponent */ // current size of RAM drive
62 TInt iTotalRomSize; /**< total size of ROM */
63 TInt iTotalRamSize; /**< total size of RAM, excluding simulated ROM*/
64 TLinAddr iPageDir; /**< @internalComponent */ // address of page directory
65 TInt iKernelFault; /**< flag to indicate reboot due to fault - cleared by bootstrap on hardware reset*/
66 TLinAddr iRamBootData; /**< @internalComponent */ // pointer to RAM description
67 TLinAddr iRomBootData; /**< @internalComponent */ // pointer to ROM description
68 TLinAddr iBootTable; /**< @internalComponent */ // used temporarily by bootstrap
69 TLinAddr iCodeBase; /**< @internalComponent */ // used temporarily by bootstrap
70 TUint32 iBootFlags; /**< @internalComponent */ // used temporarily by bootstrap
71 TLinAddr iBootAlloc; /**< @internalComponent */ // used temporarily by bootstrap
72 TLinAddr iMachineData; /**< pointer to variant specific information*/
73 TUint iActiveVariant; /**< Active Hardware Variant Descriptor*/
74 TLinAddr iPrimaryEntry; /**< pointer to TRomEntry for active kernel image*/
75 TInt iInitialHeapSize; /**< initial size of kernel stack/heap chunk*/
76 TInt iDebugPort; /**< debug port number*/
77 TUint iCpuId; /**< CPU identifier*/
78 TLinAddr iUncachedAddress; /**< Virtual address mapped to uncached memory if required*/
79 TLinAddr iRootDirList; /**< pointer to ROM root directory list (for extension ROMs)*/
80 TInt iHwStartupReason; /**< startup reason code (hardware dependent)*/
81 TLinAddr iKernelLimit; /**< @internalComponent */ // linear address of top of kernel region (direct model only)
82 TLinAddr iRamBase; /**< @internalComponent */ // linear address base of RAM (direct model only)
83 TLinAddr iDCacheFlushArea; /**< linear address of DCache flush area (direct model only)*/
84 TLinAddr iDCacheFlushWrap; /**< size of DCache flush area (direct model only)*/
85 TLinAddr iAltDCacheFlushArea; /**< linear address of alternate DCache flush area (direct model only)*/
86 TLinAddr iAltDCacheFlushWrap; /**< size of alternate DCache flush area (direct model only)*/
87 TStackInfo iStackInfo; /**< base address & size of Irq & Fiq CPU mode's stacks*/
88 TLinAddr iArmL2CacheBase; /**< base address of the external cache controller (e.g. L210, L220,...)*/
89 TUint32 iRomHeaderPhys; /**< @internalComponent */
90 TUint32 iAPBootPagePhys; /**< @internalComponent */
91 TUint32 iAPBootPageLin; /**< @internalComponent */
92 TUint32 iAPBootPageDirPhys; /**< @internalComponent */
93 TUint32 iSmrData; /**< address of shadow memory region information block (SMRIB), optional field set by bootstrap PSL */
94 TInt iReserved[26]; /**< reserved for the future use*/
98 /** Descriptor for a single contiguous block of RAM
105 TUint32 iBase; /**< physical base address of block*/
106 TUint32 iSize; /**< size of block in bytes*/
109 /** Maximum number of RAM zones.
114 const TUint KMaxRamZones = 64;
116 /** Flag to indicate that no further fixed pages can be allocated into a
118 This flag still allows device drivers to allocate pages into a RAM zone
119 using Epoc::ZoneAllocPhysicalRam().
124 const TUint KRamZoneFlagNoFixed = 0x01;
126 /** Flag to indicate that no further movable pages can be allocated into a
132 const TUint KRamZoneFlagNoMovable = 0x02;
134 /** Flag to indicate that no further discardable pages can be allocated into a
140 const TUint KRamZoneFlagNoDiscard = 0x04;
142 /** RAM zone flag that ensures no further pages are allocated into
148 const TUint KRamZoneFlagNoAlloc = 0x80;
150 /** RAM zone flag mask that ensures only discardable pages are allocated into
152 This flag mask still allows device drivers to allocate pages into a RAM zone
153 using Epoc::ZoneAllocPhysicalRam().
158 const TUint KRamZoneFlagDiscardOnly = KRamZoneFlagNoFixed | KRamZoneFlagNoMovable;
160 /** RAM zone flag to indicate that a RAM zone should be temporarily blocked
161 from further allocations.
165 const TUint KRamZoneFlagTmpBlockAlloc = 0x08000000;
167 /** RAM zone flag to indicate that a RAM zone has been inspected by a general defrag.
171 const TUint KRamZoneFlagGenDefrag = 0x20000000;
174 /** RAM zone flag to indicate that a RAM zone should not be allocated
175 into by a general defrag operation.
179 const TUint KRamZoneFlagGenDefragBlock = 0x10000000;
181 /** RAM zone flag to indicate that a RAM zone is being claimed and therefore shouldn't
186 const TUint KRamZoneFlagClaiming = 0x40000000;
188 /** RAM zone flag that is used to detect RAM zone activity.
192 const TUint KRamZoneFlagMark = 0x80000000;
196 A mask of RAM zone flag bits that can not be set by device driver or base port code.
200 const TUint KRamZoneFlagInvalid = ~(KRamZoneFlagNoAlloc | KRamZoneFlagNoFixed | KRamZoneFlagNoMovable | KRamZoneFlagNoDiscard);
202 /** Value that cannot be used for a RAM zone ID.
206 const TUint KRamZoneInvalidId = 0xffffffff;
208 /** Specifies a single RAM zone and its properties.
214 TUint32 iBase; /**< Physical base address of the RAM zone*/
215 TUint32 iSize; /**< Size of the RAM zone in bytes, the end of the SRamZone array is indicated by a RAM zone size of zero*/
216 TUint iId; /**< ID number of the RAM zone*/
217 TUint iFlags; /**< Zone flags - specify whether the RAM zone should be reserved for contiguous buffer or h/w use etc*/
218 TUint8 iPref; /**< Preference value for this RAM zone, lower preference RAM zones are used first*/
219 TUint8 iReserved[3];/**< @internalComponent*/
222 /** Defines an SRamZone struct object.
227 #define __SRAM_ZONE(aBase, aSize, aId, aFlags, aPref) \
228 {aBase, aSize, aId, aFlags, aPref, {0,0,0,},}
230 /** Ends the RAM zone declarations by defining the iSize of a RAM zone as zero.
235 #define __SRAM_ZONE_END {0,0,0,0,0,{0,0,0,},}
237 /** Descriptor for a single contiguous block of ROM
245 TUint32 iBase; /**< physical base address of block*/
246 TUint32 iSize; /**< size of block*/
247 TUint8 iWidth; /**< log2(bus width in bits)*/
248 TUint8 iType; /**< device type*/
249 TUint8 iSpeedR; /**< random access speed*/
250 TUint8 iSpeedS; /**< sequential access speed*/
251 TUint32 iLinBase; /**< linear base address of block*/
255 /* Enumeration for type of ROM
262 ERomTypeXIPFlash = 0x01,
264 ERomTypeRamAsRom = 0x04
273 const TUint KCpuIdISS = 0x80000000u; // Instruction Set Simulator
281 const TUint32 KBootFlagRunFromRAM = 0x80000000u;
284 /** This cosnstant is used in optional fields in the SSuperPageBase struct
285 (e.g. iSmrData) to indicate the field is not used/set during the boot process.
287 This maybe because the baseport does not support this field/feature or that
288 the feature is not enabled/available as determined by bootstrap PSL in
289 InitialiseHardware() at boot time.
294 const TUint32 KSuperPageAddressFieldUndefined = 0xffffffff;
297 /** Descriptor for a single contiguous block of RAM initialised with a SMR
298 image. Typically these are initialised by the pre-OS loader.
299 The structure represents an entry in the Shadow Memory Region Information
300 Block (SMRIB). SMRIB is pointed to by the SuperPage iSmrData member.
301 SMRIB ends with zero sized SSmrBank entry. The iSize is in bytes and must be a
309 TUint32 iBase; /**< physical base address of block */
310 TUint32 iSize; /**< size of block in bytes, multiple of 4Kb */
311 TUint32 iPayloadUID; /**< SMR Payload UID */
312 TUint32 iPayloadFlags; /**< SMR Payload flags */
316 /** Structure defining the SMR partition image header format.
317 The SMR Rom Header has a fixed size of 256 bytes.
324 TUint32 iFingerPrint[2]; /**< "SMR_PART" [0]=0x5F524D53[1]=0x54524150 */
325 TUint32 iReserved0; /**< Reserved for future use, always 0 */
327 TUint32 iImageVersion; /**< Version number of image format */
328 TUint32 iImageSize; /**< Size in bytes of the image (hdr+payload)*/
329 TUint32 iImageTimestamp; /**< Image creation time in seconds since midnight Jan 1st 1970 */
330 TUint32 iReserved1; /**< Reserved for future use, always 0 */
332 TUint32 iPayloadChecksum; /**< Calculated checksum at build time */
333 TUint32 iPayloadUID; /**< Alloc'd UID identifying payload content */
334 TUint32 iPayloadFlags; /**< Payload specific flag word */
335 TUint32 iReserved[54]; /**< Reserved for future use, always 0 */