1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32\memmodel\epoc\moving\arm\xkernel.cia
21 __NAKED__ void DArmPlatChunk::MoveHomePdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/)
23 asm("mov r2, r2, lsr #20 "); // r2=pde index for new addr
24 asm("subs r2, r2, r1, lsr #20 "); // subtract pde index for old addr
25 __JUMP(eq,lr); // if zero, nothing to do
26 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
28 __JUMP(eq,lr); // if chunk empty, nothing to do
29 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
30 asm("add r1, r1, r2, asl #2 "); // move home pde address
31 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
35 __NAKED__ void DArmPlatChunk::MoveCurrentPdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/)
37 asm("mov r2, r2, lsr #20 "); // r2=pde index for new addr
38 asm("subs r2, r2, r1, lsr #20 "); // subtract pde index for old addr
39 __JUMP(eq,lr); // if zero, nothing to do
40 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
42 __JUMP(eq,lr); // if chunk empty, nothing to do
43 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
44 asm("add r1, r1, r2, asl #2 "); // move current pde address
45 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
49 __NAKED__ void DArmPlatChunk::AddPde(TInt /*aOffset*/)
51 asm("mov r1, r1, lsr #20 "); // r1=pde number
52 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize));
53 asm("cmp r2, #0x02000000 ");
54 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
55 asm("bhi add_pde_large ");
57 asm("orr r3, r3, ip, lsl r1 "); // set bit in bitmap
58 asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
59 asm("b scan_small_bitmap ");
61 asm("add_pde_large: ");
62 asm("stmfd sp!, {r4,lr} ");
63 asm("mov lr, r1, lsr #5 "); // lr=word number in bitmap
64 asm("and r1, r1, #31 "); // r1=bit number in word
65 asm("ldr r4, [r3, lr, lsl #2] ");
67 asm("orr r4, r4, ip, lsl r1 ");
68 asm("str r4, [r3, lr, lsl #2] "); // set bit in bitmap
69 asm("b scan_large_bitmap ");
72 __NAKED__ void DArmPlatChunk::RemovePde(TInt /*anOffset*/)
74 asm("mov r1, r1, lsr #20 "); // r1=pde number
75 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize));
76 asm("cmp r2, #0x02000000 ");
77 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
78 asm("bhi rem_pde_large ");
80 asm("bics r3, r3, ip, lsl r1 "); // clear bit in bitmap
81 asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap));
82 asm("beq empty_chunk "); // if chunk empty, skip rest
84 asm("scan_small_bitmap: "); // r3 contains nonzero bitmap
85 #ifdef __CPU_ARM_HAS_CLZ
86 asm("sub r2, r3, #1 "); // ip will hold index of first pde
87 asm("eor r2, r2, r3 ");
89 asm("rsb r12, r12, #31 ");
90 asm("mov r3, r3, lsr r12 "); // shift bitmap so bit 0 set
92 asm("rsb r1, r1, #32 "); // r1 will be 1+most significant 1 in r3
94 asm("mov ip, #0 "); // ip will hold index of first pde
95 asm("movs r2, r3, lsl #16 "); // test if bottom 16 bits zero
96 asm("moveq r3, r3, lsr #16 "); // if bottom 16 zero, shift right by 16
97 asm("addeq ip, ip, #16 "); // and add 16 to lsb index
98 asm("tst r3, #0xff ");
99 asm("moveq r3, r3, lsr #8 ");
100 asm("addeq ip, ip, #8 ");
101 asm("tst r3, #0x0f ");
102 asm("moveq r3, r3, lsr #4 ");
103 asm("addeq ip, ip, #4 ");
104 asm("tst r3, #0x03 ");
105 asm("moveq r3, r3, lsr #2 ");
106 asm("addeq ip, ip, #2 ");
107 asm("tst r3, #0x01 ");
108 asm("moveq r3, r3, lsr #1 ");
109 asm("addeq ip, ip, #1 "); // ip=number of right shifts applied, r3 bit 0 set
110 asm("mov r1, #32 "); // r1 will be 1+most significant 1 in r3
111 asm("cmp r3, #0x00010000 ");
112 asm("movcc r3, r3, lsl #16 ");
113 asm("subcc r1, r1, #16 ");
114 asm("cmp r3, #0x01000000 ");
115 asm("movcc r3, r3, lsl #8 ");
116 asm("subcc r1, r1, #8 ");
117 asm("cmp r3, #0x10000000 ");
118 asm("movcc r3, r3, lsl #4 ");
119 asm("subcc r1, r1, #4 ");
120 asm("cmp r3, #0x40000000 ");
121 asm("movcc r3, r3, lsl #2 ");
122 asm("subcc r1, r1, #2 ");
123 asm("cmp r3, #0x80000000 ");
124 asm("movcc r3, r3, lsl #1 ");
125 asm("subcc r1, r1, #1 ");
128 asm("scan_bitmap_end: ");
129 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes)); // r1 gives number of PDEs in range
130 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iBase));
131 asm("add r2, ip, r2, lsr #20 "); // r2=pde index of first current pde
132 asm("mov r2, r2, lsl #2 ");
133 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase)); // r2->first current pde
134 asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
135 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeBase));
136 asm("add r2, ip, r2, lsr #20 "); // r2=pde index of first home pde
137 asm("mov r2, r2, lsl #2 ");
138 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase)); // r2->first home pde
139 asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
142 asm("empty_chunk: ");
144 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes));
145 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes));
146 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes));
149 asm("rem_pde_large: ");
150 asm("stmfd sp!, {r4,lr} ");
151 asm("mov lr, r1, lsr #5 "); // lr=word number in bitmap
152 asm("and r1, r1, #31 "); // r1=bit number in word
153 asm("ldr r4, [r3, lr, lsl #2] ");
155 asm("bic r4, r4, ip, lsl r1 ");
156 asm("str r4, [r3, lr, lsl #2] "); // set bit in bitmap
158 asm("scan_large_bitmap: ");
159 // r0=this, r2=max size, r3->pde bit map
160 asm("add r2, r2, #0x1f00000 ");
161 asm("mov r2, r2, lsr #25 "); // r2=number of words in bitmap
162 asm("add r2, r3, r2, lsl #2 "); // r2=bitmap end address
163 asm("mov r4, r3 "); // save bitmap start address
165 asm("scan_large_1: ");
166 asm("ldr ip, [r3], #4 ");
168 asm("bne scan_large_2 "); // found non-empty word
170 asm("bne scan_large_1 "); // if not reached end, do next word
171 asm("ldmfd sp!, {r4,lr} ");
172 asm("b empty_chunk "); // branch if no bits set
174 asm("scan_large_2: ");
175 asm("sub r1, r3, r4 ");
176 asm("sub r1, r1, #4 ");
177 asm("mov r1, r1, lsl #3 "); // r1=bit number of lsb of this word
178 #ifdef __CPU_ARM_HAS_CLZ
179 asm("sub lr, ip, #1 "); // ip will hold index of first pde
180 asm("eor ip, lr, ip ");
182 asm("rsb ip, ip, #31 ");
183 asm("add r1, r1, ip "); // r1 now = first occupied pde offset
185 asm("movs lr, ip, lsl #16 ");
186 asm("moveq ip, ip, lsr #16 ");
187 asm("addeq r1, r1, #16 ");
188 asm("tst ip, #0xff ");
189 asm("moveq ip, ip, lsr #8 ");
190 asm("addeq r1, r1, #8 ");
191 asm("tst ip, #0x0f ");
192 asm("moveq ip, ip, lsr #4 ");
193 asm("addeq r1, r1, #4 ");
194 asm("tst ip, #0x03 ");
195 asm("moveq ip, ip, lsr #2 ");
196 asm("addeq r1, r1, #2 ");
197 asm("tst ip, #0x01 ");
198 asm("moveq ip, ip, lsr #1 ");
199 asm("addeq r1, r1, #1 "); // r1 now = first occupied pde offset
202 asm("scan_large_3: ");
203 asm("ldr ip, [r2, #-4]! "); // fetch words from end of bitmap
205 asm("beq scan_large_3 "); // we know there is at least one non-zero word
206 asm("sub r2, r2, r4 ");
207 asm("mov r2, r2, lsl #3 "); // r2=bit number of lsb of this word
208 #ifdef __CPU_ARM_HAS_CLZ
210 asm("rsb ip, ip, #31 ");
211 asm("add r2, r2, ip "); // r2 now = last occupied pde offset
213 asm("movs lr, ip, lsr #16 ");
214 asm("movne ip, lr ");
215 asm("addne r2, r2, #16 ");
216 asm("movs lr, ip, lsr #8 ");
217 asm("movne ip, lr ");
218 asm("addne r2, r2, #8 ");
219 asm("movs lr, ip, lsr #4 ");
220 asm("movne ip, lr ");
221 asm("addne r2, r2, #4 ");
222 asm("movs lr, ip, lsr #2 ");
223 asm("movne ip, lr ");
224 asm("addne r2, r2, #2 ");
225 asm("movs lr, ip, lsr #1 ");
226 asm("movne ip, lr ");
227 asm("addne r2, r2, #1 "); // r2 now = last occupied pde offset
229 asm("sub r3, r2, r1 "); // r3=last-first
230 asm("mov ip, r1 "); // ip=first
231 asm("add r1, r3, #1 "); // r1 = number of pdes in range
232 asm("ldmfd sp!, {r4,lr} ");
233 asm("b scan_bitmap_end "); // go back to set pde info
236 __NAKED__ TBool Exc::IsMagic(TLinAddr /*anAddress*/)
238 // Return TRUE if anAddress is a 'magic' exception handling instruction
241 asm("adr r1, __magic_addresses "); // r1 points to list of magic addresses
243 asm("ldr r2, [r1], #4 "); // r2=next magic address to check
244 asm("cmp r2, r0 "); // is r0=magic address?
245 asm("cmpne r2, #0 "); // if not, have we reached end of list?
246 asm("bne is_magic_1 "); // if neither, check next address
247 asm("movs r0, r2 "); // r0=0 if not magic, r0 unchanged if magic
250 asm("__magic_addresses: ");
251 asm(".word __magic_address_kusaferead ");
252 asm(".word __magic_address_saferead ");
253 asm(".word __magic_address_kusafewrite ");
254 asm(".word __magic_address_safewrite ");
255 asm(".word __magic_address_msg_lookup_1 "); // in preprocess handler
256 asm(".word __magic_address_readdesheader1 ");
257 asm(".word __magic_address_readdesheader2 ");
258 asm(".word __magic_address_readdesheader3 ");
259 #ifdef __MESSAGE_MACHINE_CODED_2__
260 asm(".word __magic_address_msg_lookup_2 ");
262 #ifdef __CLIENT_REQUEST_MACHINE_CODED__
263 asm(".word __magic_address_client_request_callback");
264 asm(".word __magic_address_svr_accept_1 ");
265 asm(".word __magic_address_svr_accept_2 ");
266 asm(".word __magic_address_svr_accept_3 ");
267 asm(".word __magic_address_svr_accept_4 ");
268 asm(".word __magic_address_svr_accept_5 ");
269 asm(".word __magic_address_svr_accept_6 ");
270 asm(".word __magic_address_svr_accept_7 ");
271 asm(".word __magic_address_svr_accept_8 ");
273 #ifdef __REQUEST_COMPLETE_MACHINE_CODED__
274 asm(".word __magic_address_reqc ");
275 asm(".word __magic_address_kern_request_complete ");
281 __NAKED__ TAny* MM::CurrentAddress(DThread* /*aThread*/, const TAny* /*aPtr*/, TInt /*aSize*/, TBool /*aWrite*/)
283 // Return the current base address corresponding to run address region
284 // aPtr to aPtr+aBase-1 in the context of aThread.
285 // aWrite indicates whether the address is intended for writing (aWrite=TRUE) or reading (aWrite=FALSE).
286 // Return NULL if the address range is not all accessible to aThread for access type specified by aWrite.
287 // aWrite=FALSE allows access to the ROM and RAM-loaded code chunks whereas aWrite=TRUE disallows these.
288 // NOTE THIS FUNCTION CONTAINS KNOWLEDGE OF FIXED LINEAR ADDRESSES (the RAM drive and HIVECS area).
290 // ALLERT! the ip register returns a pointer to the chunk which contains the addresses (null if none)
293 asm("CurrentAddress:");
294 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DThread, iOwningProcess));
295 asm("stmfd sp!, {r4,r5,lr} ");
296 asm("eor r4, r1, #0x40000000 "); // r4<0x20000000u for RAM drive
297 asm("cmp r4, #0x20000000 "); // Check for RAM drive - ASSUMES RAM DRIVE IS AT 40000000-5FFFFFFF
298 asm("ldr lr, [r0, #%a0]!" : : "i" _FOFF(DMemModelProcess, iNumChunks)); // step r0 on to iChunks[0]
299 asm("bcc lookup_chunk_3 "); // branch if RAM drive
300 asm("subs lr, lr, #1 ");
301 asm("bcc lookup_chunk_2 "); // no chunks so do read check
302 asm("lookup_chunk_1: ");
303 asm("ldmib r0!, {r4,ip} "); // r4=data section base, ip=chunk ptr
304 asm("add r0, r0, #4 "); // move to next entry
305 asm("subs r4, r1, r4 "); // r4=offset
306 asm("ldrcs r5, [ip, #%a0]" : : "i" _FOFF(DChunk,iMaxSize)); // if offset>=0, r5=chunk max size
307 asm("cmpcs r4, r5 "); // and compare offset to max size
308 asm("subcss lr, lr, #1 "); // if offset>=max size, decrement counter
309 asm("bcs lookup_chunk_1 "); // loop if more chunks to check
310 asm("cmp lr, #0 "); // did we find chunk?
311 asm("ldrge r0, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionOffset));
312 asm("ldrge r5, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionSize));
313 asm("ldrge lr, [ip, #%a0]" : : "i" _FOFF(DChunk,iBase));
314 asm("cmpge r4, r0 "); // if chunk not found or offset<iHomeRegionOffset, do read check
315 asm("blt lookup_chunk_2 ");
316 asm("add r0, r0, r5 "); // r0=home region offset+home region size
317 asm("add r5, r4, r2 "); // r5=offset after end of block
318 asm("cmp r5, r0 "); // check if offset after end<=iHomeRegionOffset+iHomeRegionSize
319 asm("addle r0, lr, r4 "); // if so, r0=current chunk base + offset
320 asm("ldmlefd sp!, {r4,r5,pc} "); // and we are done
322 asm("lookup_chunk_2: "); // come here if address not found in a chunk
323 asm("mov ip, #0"); // ip = 0 to indicate chunk not found
324 asm("ldr r4, __code_limit ");
326 asm("cmn r1, #0x00100000 "); // address in hivecs area?
327 asm("ldr r4, [r4] "); // r4 = lowest legitimate code address
328 asm("ldmcsfd sp!, {r4,r5,pc} "); // if in hivecs, return NULL
329 asm("cmp r3, #0 "); // is this address intended for writing?
330 asm("ldmnefd sp!, {r4,r5,pc} "); // if it is, return NULL
331 asm("cmp r1, r4 "); // check if address is in RAM-loaded code or ROM
332 asm("ldmccfd sp!, {r4,r5,pc} "); // if not, return NULL
333 asm("adds r4, r1, r2 "); // r4 = end address of requested region
334 asm("ldmcsfd sp!, {r4,r5,pc} "); // if it wrapped, return NULL
335 asm("cmn r4, #0x100000 "); // if it didn't wrap, check if it reaches into hivecs area
336 asm("movls r0, r1 "); // if not, addr is OK for reading
337 asm("ldmfd sp!, {r4,r5,pc} ");
339 asm("lookup_chunk_3: "); // come here if address in RAM drive
340 asm("mov ip, #0"); // ip = 0 to indicate chunk not found
341 asm("ldr r3, __f32 "); // r3=&K::TheFileServerProcess
342 asm("sub r4, r0, #%a0" : : "i" _FOFF(DMemModelProcess, iNumChunks)); // r4=aThread->iOwningProcess
344 asm("ldr r3, [r3] "); // r3=K::TheFileServerProcess
345 asm("add r5, r1, r2 "); // r5=end address of requested region + 1
346 asm("cmp r5, #0x60000000 "); // is this past the end of the RAM drive? ASSUMES ADDRESS OF RAM DRIVE
347 asm("cmpls r3, r4 "); // if not, is aThread part of F32?
348 asm("moveq r0, r1 "); // if it is, allow the access and return the address unaltered
349 asm("ldmfd sp!, {r4,r5,pc} "); // else return NULL
352 asm(".word " CSM_ZN1K20TheFileServerProcessE );
353 asm("__code_limit: ");
354 asm(".word %a0" : : "i" ((TInt)&::TheMmu.iUserCodeBase) );