os/kernelhwsrv/kernel/eka/include/nkernsmp/arm/arm_scu.h
author sl
Tue, 10 Jun 2014 14:32:02 +0200
changeset 1 260cb5ec6c19
permissions -rw-r--r--
Update contrib.
     1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
     2 // All rights reserved.
     3 // This component and the accompanying materials are made available
     4 // under the terms of the License "Eclipse Public License v1.0"
     5 // which accompanies this distribution, and is available
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
     7 //
     8 // Initial Contributors:
     9 // Nokia Corporation - initial contribution.
    10 //
    11 // Contributors:
    12 //
    13 // Description:
    14 // e32\include\nkernsmp\arm\arm_scu.h
    15 // Register definitions for ARM Snoop Control Unit
    16 // 
    17 // WARNING: This file contains some APIs which are internal and are subject
    18 //          to change without notice. Such APIs should therefore not be used
    19 //          outside the Kernel and Hardware Services package.
    20 //
    21 
    22 #ifndef	__ARM_SCU_H__
    23 #define	__ARM_SCU_H__
    24 #include <e32def.h>
    25 
    26 #ifdef	__STANDALONE_NANOKERNEL__
    27 #undef	__IN_KERNEL__
    28 #define	__IN_KERNEL__
    29 #endif
    30 
    31 #if defined(__CPU_ARM11MP__)
    32 struct ArmScu
    33 	{
    34 	volatile TUint32	iCtrl;				// 00 Control register
    35 	volatile TUint32	iConfig;			// 04 Configuration register (RO)
    36 	volatile TUint32	iCpuStatus;			// 08 SCU CPU Status register
    37 	volatile TUint32	iInvalidateAll;		// 0C Invalidate All register (WO)
    38 	volatile TUint32	iPMCtrl;			// 10 Performance Monitor Control register
    39 	volatile TUint32	iMonitorEvents0;	// 14 Monitor Counter Events 0
    40 	volatile TUint32	iMonitorEvents1;	// 18 Monitor Counter Events 1
    41 	volatile TUint32	iMonitorCount0;		// 1C Monitor Counter 0
    42 	volatile TUint32	iMonitorCount1;		// 20 Monitor Counter 1
    43 	volatile TUint32	iMonitorCount2;		// 24 Monitor Counter 2
    44 	volatile TUint32	iMonitorCount3;		// 28 Monitor Counter 3
    45 	volatile TUint32	iMonitorCount4;		// 2C Monitor Counter 4
    46 	volatile TUint32	iMonitorCount5;		// 30 Monitor Counter 5
    47 	volatile TUint32	iMonitorCount6;		// 34 Monitor Counter 6
    48 	volatile TUint32	iMonitorCount7;		// 38 Monitor Counter 7
    49 	volatile TUint32	i_Skip_1[49];		// 3C unused
    50 	};
    51 
    52 __ASSERT_COMPILE(sizeof(ArmScu)==0x100);
    53 
    54 enum TArmScuCtrl
    55 	{
    56 	E_ArmScuCtrl_Enable			=1u,			// SCU Enable
    57 	E_ArmScuCtrl_AccessShift	=1u,
    58 	E_ArmScuCtrl_AccessMask		=0x1eu,			// bits 1-4 = SCU access control for CPU0-3
    59 	E_ArmScuCtrl_IIAliasShift	=5u,
    60 	E_ArmScuCtrl_IIAliasMask	=0x1e0u,		// bits 5-8 = Interrupt Interface Alias enable for CPU0-3
    61 	E_ArmScuCtrl_PIAliasShift	=9u,
    62 	E_ArmScuCtrl_PIAliasMask	=0x1e00u,		// bits 9-12 = Peripheral Interface Alias enable for CPU0-3
    63 	};
    64 
    65 enum TArmScuPMCR
    66 	{
    67 	E_ArmScuPMCR_Enable			=1u,			// 0=all counters disabled
    68 	E_ArmScuPMCR_ResetAll		=2u,			// write 1 resets all counters
    69 	E_ArmScuPMCR_IntEn0			=0x100u,		// Interrupt Enable for MN0
    70 	E_ArmScuPMCR_IntEn1			=0x200u,		// Interrupt Enable for MN1
    71 	E_ArmScuPMCR_IntEn2			=0x400u,		// Interrupt Enable for MN2
    72 	E_ArmScuPMCR_IntEn3			=0x800u,		// Interrupt Enable for MN3
    73 	E_ArmScuPMCR_IntEn4			=0x1000u,		// Interrupt Enable for MN4
    74 	E_ArmScuPMCR_IntEn5			=0x2000u,		// Interrupt Enable for MN5
    75 	E_ArmScuPMCR_IntEn6			=0x4000u,		// Interrupt Enable for MN6
    76 	E_ArmScuPMCR_IntEn7			=0x8000u,		// Interrupt Enable for MN7
    77 	E_ArmScuPMCR_Ovfw0			=0x10000u,		// Overflow Flag for MN0 (write 1 to clear)
    78 	E_ArmScuPMCR_Ovfw1			=0x20000u,		// Overflow Flag for MN1
    79 	E_ArmScuPMCR_Ovfw2			=0x40000u,		// Overflow Flag for MN2
    80 	E_ArmScuPMCR_Ovfw3			=0x80000u,		// Overflow Flag for MN3
    81 	E_ArmScuPMCR_Ovfw4			=0x100000u,		// Overflow Flag for MN4
    82 	E_ArmScuPMCR_Ovfw5			=0x200000u,		// Overflow Flag for MN5
    83 	E_ArmScuPMCR_Ovfw6			=0x400000u,		// Overflow Flag for MN6
    84 	E_ArmScuPMCR_Ovfw7			=0x800000u,		// Overflow Flag for MN7
    85 	};
    86 
    87 
    88 #elif defined(__CPU_CORTEX_A9__)
    89 struct ArmScu
    90 	{
    91 	volatile TUint32	iCtrl;				// 00 Control register
    92 	volatile TUint32	iConfig;			// 04 Configuration register (RO)
    93 	volatile TUint32	iCpuStatus;			// 08 SCU CPU Power Status register
    94 	volatile TUint32	iInvalidateAll;		// 0C Invalidate All register (WO)
    95 	volatile TUint32	i_Skip_1[12];		// 10-3F unused
    96 	volatile TUint32	i_FSAR;				// 40 Filtering Start Address Register
    97 	volatile TUint32	i_FEAR;				// 44 Filtering End Address Register
    98 	volatile TUint32	i_Skip_2[2];		// 48-4F unused
    99 	volatile TUint32	i_SAC;				// 50 SCU Access Control Register
   100 	volatile TUint32	i_SSAC;				// 54 SCU Secure Access Control Register
   101 	volatile TUint32	i_Skip_3[42];		// 58-FF unused
   102 	};
   103 
   104 __ASSERT_COMPILE(sizeof(ArmScu)==0x100);
   105 
   106 enum TArmScuCtrl
   107 	{
   108 	E_ArmScuCtrl_Enable			=1u,			// SCU Enable
   109 	E_ArmScuCtrl_AFEnable		=2u,			// SCU Address Filtering Enable
   110 	E_ArmScuCtrl_ParityEnable	=4u,			// SCU Parity Enable
   111 	};
   112 
   113 enum TArmScuSAC
   114 	{
   115 	E_ArmScuSAC_CPU0			=1u,			// If set, CPU0 can access SCU registers
   116 	E_ArmScuSAC_CPU1			=2u,			// If set, CPU1 can access SCU registers
   117 	E_ArmScuSAC_CPU2			=4u,			// If set, CPU2 can access SCU registers
   118 	E_ArmScuSAC_CPU3			=8u,			// If set, CPU3 can access SCU registers
   119 	};
   120 
   121 enum TArmScuSSAC
   122 	{
   123 	E_ArmScuSSAC_CPU0			=1u,			// If set, CPU0 can access SCU registers in nonsecure state
   124 	E_ArmScuSSAC_CPU1			=2u,			// If set, CPU1 can access SCU registers in nonsecure state
   125 	E_ArmScuSSAC_CPU2			=4u,			// If set, CPU2 can access SCU registers in nonsecure state
   126 	E_ArmScuSSAC_CPU3			=8u,			// If set, CPU3 can access SCU registers in nonsecure state
   127 	E_ArmScuSSAC_Timer0			=16u,			// If set, CPU0 private timer is accessible in nonsecure state
   128 	E_ArmScuSSAC_Timer1			=32u,			// If set, CPU1 private timer is accessible in nonsecure state
   129 	E_ArmScuSSAC_Timer2			=64u,			// If set, CPU2 private timer is accessible in nonsecure state
   130 	E_ArmScuSSAC_Timer3			=128u,			// If set, CPU3 private timer is accessible in nonsecure state
   131 	};
   132 
   133 #else
   134 #error	Unknown SCU
   135 #endif
   136 
   137 enum TArmScuConfig
   138 	{
   139 	E_ArmScuCfg_NCpusMask		=3u,			// bits0,1 = number of CPUs - 1
   140 	E_ArmScuCfg_CpuSMPShift		=4u,
   141 	E_ArmScuCfg_CpuSMPMask		=0xf0u,			// bits4-7 = CPU0-3 SMP mode indicator
   142 	E_ArmScuCfg_TagShift		=8u,
   143 	E_ArmScuCfg_TagMask			=0xff00u,		// two bits per CPU, tag RAM size = 16KB<<n (n=0,1,2 n=3 reserved)
   144 	};
   145 
   146 // Bits 2n,2n+1 of CPU status refer to CPU n
   147 enum TArmScuCPUStatus
   148 	{
   149 	E_ArmScuCpuStat_Normal		=0u,			// normal mode
   150 												// 1 reserved
   151 	E_ArmScuCpuStat_Dormant		=2u,			// dormant mode
   152 	E_ArmScuCpuStat_PowerDown	=3u,			// power down mode
   153 	};
   154 
   155 #endif	// 	__ARM_SCU_H__