1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
2 // All rights reserved.
3 // This component and the accompanying materials are made available
4 // under the terms of the License "Eclipse Public License v1.0"
5 // which accompanies this distribution, and is available
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
8 // Initial Contributors:
9 // Nokia Corporation - initial contribution.
14 // e32\include\nkernsmp\arm\arm_gic.h
15 // Register definitions for ARM Generic Interrupt Controller
17 // WARNING: This file contains some APIs which are internal and are subject
18 // to change without notice. Such APIs should therefore not be used
19 // outside the Kernel and Hardware Services package.
26 #ifdef __STANDALONE_NANOKERNEL__
33 E_GicIntId_Soft0 =0, // IDs 0-15 are for software triggered IPIs
43 E_GicIntId_Soft10 =10,
44 E_GicIntId_Soft11 =11,
45 E_GicIntId_Soft12 =12,
46 E_GicIntId_Soft13 =13,
47 E_GicIntId_Soft14 =14,
48 E_GicIntId_Soft15 =15,
50 E_GicIntId_Private0 =16, // IDs 16-31 are for private peripherals
51 E_GicIntId_Private1 =17,
52 E_GicIntId_Private2 =18,
53 E_GicIntId_Private3 =19,
54 E_GicIntId_Private4 =20,
55 E_GicIntId_Private5 =21,
56 E_GicIntId_Private6 =22,
57 E_GicIntId_Private7 =23,
58 E_GicIntId_Private8 =24,
59 E_GicIntId_Private9 =25,
60 E_GicIntId_Private10 =26,
61 E_GicIntId_Private11 =27,
62 E_GicIntId_Private12 =28,
63 E_GicIntId_Private13 =29,
64 E_GicIntId_Private14 =30,
65 E_GicIntId_Private15 =31,
67 E_GicIntId_Normal0 =32, // first normal interrupt ID
69 E_GicIntId_NormalLast =1019, // last possible normal interrupt ID
70 E_GicIntId_Reserved0 =1020, // reserved interrupt ID
71 E_GicIntId_Reserved1 =1021, // reserved interrupt ID
72 E_GicIntId_NS =1022, // only nonsecure interrupts are serviceable
73 E_GicIntId_Spurious =1023 // no interrupts are serviceable
78 volatile TUint32 iCtrl; // 000 Control register
79 volatile TUint32 iType; // 004 Type register
80 volatile TUint32 iImpId; // 008 Implementor Identification register (not on MPCore)
81 volatile TUint32 i_Skip_1[29]; // 00C unused
82 volatile TUint32 iIntSec[32]; // 080 Interrupt Security register (not on MPCore) (1 bit per interrupt)
83 volatile TUint32 iEnableSet[32]; // 100 Enable set register (1 bit per interrupt)
84 volatile TUint32 iEnableClear[32]; // 180 Enable clear register (1 bit per interrupt)
85 volatile TUint32 iPendingSet[32]; // 200 Pending set register (1 bit per interrupt)
86 volatile TUint32 iPendingClear[32]; // 280 Pending clear register (1 bit per interrupt)
87 volatile TUint32 iActive[32]; // 300 Active status register (1 bit per interrupt)
88 volatile TUint32 i_Skip_2[32]; // 380 unused
89 volatile TUint32 iPriority[256]; // 400 Interrupt priority register (8 bits per interrupt)
90 volatile TUint32 iTarget[256]; // 800 Interrupt target CPUs register (8 bits per interrupt)
91 volatile TUint32 iConfig[64]; // C00 Interrupt configuration register (2 bits per interrupt)
92 volatile TUint32 iImpDef[64]; // D00 Implementation defined registers
93 // = Interrupt line level on MPCore
94 volatile TUint32 i_Skip_3[64]; // E00 unused
95 volatile TUint32 iSoftIrq; // F00 Software triggered interrupt register
96 volatile TUint32 i_Skip_4[51]; // F04 unused
97 volatile TUint32 iIdent[12]; // FD0 Identification registers
100 __ASSERT_COMPILE(sizeof(GicDistributor)==0x1000);
104 volatile TUint32 iCtrl; // 00 Control register
105 volatile TUint32 iPriMask; // 04 Priority mask register
106 volatile TUint32 iBinaryPoint; // 08 Binary point register
107 volatile TUint32 iAck; // 0C Interrupt acknowledge register
108 volatile TUint32 iEoi; // 10 End of interrupt register
109 volatile TUint32 iRunningPri; // 14 Running priority register
110 volatile TUint32 iHighestPending; // 18 Highest pending interrupt register
111 volatile TUint32 iNSBinaryPoint; // 1C Aliased nonsecure binary point register (not on MPCore)
112 volatile TUint32 i_Skip_1[8]; // 20 unused
113 volatile TUint32 iImpDef[36]; // 40 Implementation defined (not present on MPCore)
114 volatile TUint32 i_Skip_2[11]; // D0 unused
115 volatile TUint32 iImpId; // FC Implementor Identification register (not on MPCore)
118 __ASSERT_COMPILE(sizeof(GicCpuIfc)==0x100);
122 E_GicDistCtrl_Enable =1, // Enable interrupt distributor
127 E_GicDistType_ITShift =0u, // bits 0-4 = number of sets of 32 interrupts supported
128 E_GicDistType_ITMask =0x1fu,
129 E_GicDistType_CPUNShift =5u, // bits 5-7 = number of CPUs supported - 1
130 E_GicDistType_CPUNMask =0xe0u,
131 E_GicDistType_Domains =0x400u, // set if two security domains supported
132 E_GicDistType_LSPIShift =11u, // bits 11-15 = number of lockable shared peripheral interrupts
133 E_GicDistType_LSPIMask =0xf800u,
136 enum TGicDistIntConfig
138 E_GicDistICfg1N =1u, // if set use 1-N model else use N-N model
139 // peripheral interrupts support only 1-N model, s/w interrupts N-N
140 // 1-N means the interrupt is cleared by the first CPU to accept it
141 E_GicDistICfgEdge =2u, // if set, rising edge triggered, else active high level triggered
144 enum TGicDistSoftIrqDestType
146 E_GicDestTypeList =0u, // send to all CPUs in list (bit mask)
147 E_GicDestTypeOthers =1u, // send to all CPUs other than self
148 E_GicDestTypeSelf =2u, // send to self only
149 E_GicDestTypeRsvd =3u
152 // Compile word to generate IPI
153 // dt = destination type, dl = bit mask of destination CPUs, id = interrupt ID (0-15)
154 #define GIC_SOFT_IRQ_WORD(dt,dl,id) ((TUint32(dt)<<24)|(TUint32(dl)<<16)|(TUint32(id)))
156 #define GIC_IPI_SELF(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeSelf, 0, id)
157 #define GIC_IPI_OTHERS(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeOthers, 0, id)
158 #define GIC_IPI(dl,id) GIC_SOFT_IRQ_WORD(E_GicDestTypeList, dl, id)
161 #endif // __ARM_GIC_H__