Symaptic: os/kernelhwsrv/kernel/eka/include/memmodel/epoc/multiple/memmodel.h@260cb5ec6c19

     1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // e32\include\memmodel\epoc\multiple\memmodel.h

    15 //

    16 // WARNING: This file contains some APIs which are internal and are subject

    17 //          to change without notice. Such APIs should therefore not be used

    18 //          outside the Kernel and Hardware Services package.

    19 //

    21 #ifndef __MEMMODEL_H__

    22 #define __MEMMODEL_H__

    23 #include <memmodel/epoc/mmubase/mmubase.h>

    25 #ifdef __SMP__

    26 // SubScheduler fields for each processor

    27 #define	i_AliasLinAddr			iExtras[0]

    28 #define	i_AliasPdePtr			iExtras[1]

    29 #endif

    31 /********************************************

    32  * Dynamic Branch Predictor Support

    33  ********************************************/

    35 /**

    36 @internalComponent

    37 */

    38 #ifdef __SMP__

    39 //#define LastUserSelfMod                   ((DProcess*&)SubScheduler().iExtras[0])

    40 #else

    41 #define LastUserSelfMod                   ((DProcess*&)TheScheduler.iExtras[0])

    42 #endif

    44 /********************************************

    45  * RAM Defrag Page Table Moving Support

    46  ********************************************/

    48 /**

    49 @internalComponent

    50 */

    51 #define AliasRemapOld					((TPhysAddr&)TheScheduler.iExtras[1])

    53 /**

    54 @internalComponent

    55 */

    56 #define AliasRemapNew					((TPhysAddr&)TheScheduler.iExtras[2])

    58 /********************************************

    59  * Thread Control Block

    60  ********************************************/

    62 class DMemModelProcess;

    64 /**

    65 @internalComponent

    66 */

    67 class DMemModelThread : public DThread

    68 	{

    69 public:

    70 	TInt Alias(TLinAddr aAddr, DMemModelProcess* aProcess, TInt aSize, TInt aPerm, TLinAddr& aAliasAddr, TInt& aAliasSize);

    71 	void RemoveAlias();

    72 	virtual void DoExit1();

    73 	static void RestoreAddressSpace();

    74 public:

    75 	TLinAddr iAliasLinAddr;	// linear address to access aliased memory (0 means no alias is present).

    76 	TPde* iAliasPdePtr;		// Address of PDE which has been modified to make aliased memory accessible.

    77 	TPde iAliasPde;			// PDE to store at iAliasPdePtr.

    78 	TInt iAliasOsAsid;		// asid for the process whoes memory is aliased.

    79 	SDblQueLink iAliasLink;	// link to make TheMmu.iAliasList.

    80 	TLinAddr iAliasTarget;	// linear address of the memory which has been aliased

    81 #ifdef __SMP__

    82 	TInt iCpuRestoreCookie;

    83 #endif

    84 	};

    87 /********************************************

    88  * Process Control Block

    89  ********************************************/

    91 class DMemModelChunk;

    92 class DMemModelCodeSegMemory;

    94 /**

    95 @internalComponent

    96 */

    97 class DMemModelProcess : public DEpocProcess

    98 	{

    99 public:

   100 	void Destruct();

   101 public:

   102 	virtual TInt DoCreate(TBool aKernelProcess, TProcessCreateInfo& aInfo);

   103 	virtual TInt NewChunk(DChunk*& aChunk, SChunkCreateInfo& aInfo, TLinAddr& aRunAddr);

   104 	virtual TInt AddChunk(DChunk* aChunk,TBool isReadOnly);

   105 	virtual TInt NewShPool(DShPool*& aPool, TShPoolCreateInfo& aInfo);

   106 	virtual TInt CreateDataBssStackArea(TProcessCreateInfo& aInfo);

   107 	virtual TInt MapCodeSeg(DCodeSeg* aCodeSeg);

   108 	virtual void UnmapCodeSeg(DCodeSeg* aCodeSeg);

   109 	virtual void RemoveDllData();

   110 	virtual void FinalRelease();

   111 public:

   112 	virtual TInt GetNewChunk(DMemModelChunk*& aChunk, SChunkCreateInfo& aInfo)=0;

   113 public:

   114 	TInt AddChunk(DMemModelChunk* aChunk, TLinAddr& aDataSectionBase, TBool isReadOnly);

   115 	TInt AllocateDataSectionBase(DMemModelChunk& aChunk, TUint& aBase);

   116 	TUint8* DataSectionBase(DMemModelChunk* aChunk);

   117 	void RemoveChunk(DMemModelChunk *aChunk);

   118 	void DoRemoveChunk(TInt aIndex);

   119 	TInt ChunkIndex(DMemModelChunk* aChunk,TInt& aPos);

   120 	TInt CreateCodeChunk();

   121 	void FreeCodeChunk();

   122 	TInt CreateDllDataChunk();

   123 	void FreeDllDataChunk();

   124 	TInt CommitDllData(TLinAddr aBase, TInt aSize);

   125 	void DecommitDllData(TLinAddr aBase, TInt aSize);

   126 	TInt MapUserRamCode(DMemModelCodeSegMemory* aMemory, TBool aLoading);

   127 	void UnmapUserRamCode(DMemModelCodeSegMemory* aMemory, TBool aLoading);

   128 public:

   129 	enum TMemModelProcessAttributes

   130 		{

   131 		ESeparateGlobalSpace=0x40000000,

   132 		EMMProcessAttributesMask = ESeparateGlobalSpace,

   133 		};

   135 	struct SChunkInfo

   136 		{

   137 		DMemModelChunk* iChunk;

   138 		TInt16 iAccessCount;

   139 		TInt16 isReadOnly;

   140 		};

   142 	TInt iChunkCount;

   143 	TInt iChunkAlloc;

   144 	SChunkInfo* iChunks;

   145 	TLinearSection* iLocalSection;

   146 	TInt iOsAsid;

   147 	TPhysAddr iLocalPageDir;

   148 	TPhysAddr iGlobalPageDir;

   149 	TUint32 iAddressCheckMaskR;

   150 	TUint32 iAddressCheckMaskW;

   151 	DMemModelChunk* iCodeChunk;

   152 	DMemModelChunk* iDllDataChunk;

   153 	TInt iSelfModChunks;

   154 public:

   155 	friend class Monitor;

   156 	};

   159 /********************************************

   160  * Chunk Control Block

   161  ********************************************/

   163 /**

   164 @internalComponent

   165 */

   166 class DMemModelChunk : public DChunk

   167 	{

   168 public:

   169 	/**

   170 	@see DChunk::TChunkAttributes for generic attribute flags

   171 	*/

   172 	enum TMemModelChunkAttributes

   173 		{

   174 		EPrivate			=0x80000000,

   175 		ECode				=0x40000000,

   176 		EAddressAllocDown	=0x20000000,

   178 		EAddressRangeMask	=0x0f000000,

   179 		EAddressRangeShift	=24,

   180 		EAddressLocal		=0x00000000,

   181 		EAddressShared		=0x01000000,

   182 		EAddressUserGlobal	=0x02000000,

   183 		EAddressKernel		=0x03000000,

   184 		EAddressFixed		=0x04000000,

   186 		EMapTypeMask		=0x00c00000,

   187 		EMapTypeLocal		=0x00000000,

   188 		EMapTypeGlobal		=0x00400000,

   189 		EMapTypeShared		=0x00800000,

   191 		EMMChunkAttributesMask = EPrivate|ECode|EAddressAllocDown|EAddressRangeMask|EMapTypeMask,

   192 		};

   194 public:

   195 	DMemModelChunk();

   196 	void Destruct();

   197 public:

   198 	virtual TInt Close(TAny* aPtr);

   199 	virtual TInt DoCreate(SChunkCreateInfo& aInfo);

   200 	virtual TInt Adjust(TInt aNewSize);

   201 	virtual TInt AdjustDoubleEnded(TInt aBottom, TInt aTop);

   202 	virtual TInt CheckAccess();

   203 	virtual TInt Commit(TInt aOffset, TInt aSize, TCommitType aCommitType=DChunk::ECommitDiscontiguous, TUint32* aExtraArg=0);

   204 	virtual TInt Allocate(TInt aSize, TInt aGuard=0, TInt aAlign=0);

   205 	virtual TInt Decommit(TInt aOffset, TInt aSize);

   206 	virtual TInt Lock(TInt anOffset, TInt aSize);

   207 	virtual TInt Unlock(TInt anOffset, TInt aSize);

   208 	virtual TInt Address(TInt aOffset, TInt aSize, TLinAddr& aKernelAddress);

   209 	virtual TInt PhysicalAddress(TInt aOffset, TInt aSize, TLinAddr& aKernelAddress, TUint32& aPhysicalAddress, TUint32* aPhysicalPageList=NULL);

   210 	virtual void BTracePrime(TInt aCategory);

   211 	virtual void Substitute(TInt aOffset, TPhysAddr aOldAddr, TPhysAddr aNewAddr);

   212 	virtual TUint8* Base(DProcess* aProcess);

   213 	inline TUint8* Base() const { return DChunk::Base(); }

   214 public:

   215 	TInt Decommit(TInt aOffset, TInt aSize, TDecommitType aDecommitType);

   216 	void ClaimInitialPages();

   217 	void SetFixedAddress(TLinAddr aAddr, TInt aInitialSize);

   218 	TInt Reserve(TInt aInitialSize);

   219 	TInt DoCommit(TInt aOffset, TInt aSize, TCommitType aCommitType=DChunk::ECommitDiscontiguous, TUint32* aExtraArg=0);

   220 	void DoDecommit(TInt aOffset, TInt aSize, TDecommitType aDecommitType=EDecommitNormal);

   221 	TInt AllocateAddress();

   222 	void ApplyPermissions(TInt aOffset, TInt aSize, TPte aPtePerm);

   223 	TLinearSection* LinearSection();

   224 	TZonePageType GetPageType();

   226 public:

   227 	virtual TInt SetupPermissions()=0;

   229 public:

   230 	TBitMapAllocator* iOsAsids;			// NULL for local or fully global else list of OS ASIDs

   231 	TPte iPtePermissions;

   232 	TPde iPdePermissions;

   233 	TUint16* iPageTables;

   234 	TBitMapAllocator* iPageBitMap;		// NULL if not disconnected chunk

   235 	TBitMapAllocator* iPermanentPageBitMap;

   236 	DMemModelChunk* iKernelMirror;

   237 public:

   238 	friend class Monitor;

   239 	};

   242 /********************************************

   243  * Code segment

   244  ********************************************/

   246 /**

   247 @internalComponent

   248 */

   249 class DMemModelCodeSegMemory : public DMmuCodeSegMemory

   250 	{

   251 public:

   252 	DMemModelCodeSegMemory(DEpocCodeSeg* aCodeSeg);

   253 	~DMemModelCodeSegMemory();

   254 	TInt Create(TCodeSegCreateInfo& aInfo);

   255 	TInt Loaded(TCodeSegCreateInfo& aInfo);

   256 	void Substitute(TInt aOffset, TPhysAddr aOld, TPhysAddr aNew);

   257 	void Destroy();

   258 public:

   259 	DMemModelProcess* iCreator;	// process loading this code segment

   261 	TPhysAddr* iPages;			// list of physical pages (iPageCount+iDataPageCount)

   263 	/**

   264 	List of OS ASIDs this code segment is mapped into.

   265 	Protected by RamAllocMutex and System Lock.

   266 	*/

   267 	TBitMapAllocator* iOsAsids;

   269 	TLinAddr* iCopyOfExportDir;	// kernel side copy of export directory or NULL

   270 	};

   272 /**

   273 @internalComponent

   274 */

   275 class DMemModelCodeSeg: public DEpocCodeSeg

   276 	{

   277 public:

   278 	DMemModelCodeSeg();

   279 	virtual ~DMemModelCodeSeg();

   280 	virtual TInt DoCreateRam(TCodeSegCreateInfo& aInfo, DProcess* aProcess);

   281 	virtual TInt DoCreateXIP(DProcess* aProcess);

   282 	virtual TInt Loaded(TCodeSegCreateInfo& aInfo);

   283 	virtual void ReadExportDir(TUint32* aDest);

   284 	virtual TBool FindCheck(DProcess* aProcess);

   285 	virtual TBool OpenCheck(DProcess* aProcess);

   286 	virtual void BTracePrime(TInt aCategory);

   287 	inline DMemModelCodeSegMemory* Memory()

   288 		{ return (DMemModelCodeSegMemory*)iMemory; }

   289 	inline TPhysAddr* Pages()

   290 		{ return iMemory!=0 ? Memory()->iPages : (TPhysAddr*)0; }

   291 public:

   292 	TInt iCodeAllocBase;

   293 	TInt iDataAllocBase;

   294 	TAny* iKernelData;			// only for kernel modules

   295 	};

   298 /********************************************

   299  * MMU stuff

   300  ********************************************/

   302 /**

   303 @internalComponent

   304 Indicates that corresponding linear address applies to unknown address space.

   305 Common for EMemTypeShared types of chunks with no owning process.

   306 */

   307 #define	UNKNOWN_MAPPING	((TInt)-2)

   309 /**

   310 @internalComponent

   311 Indicates that corresponding linear address applies to global address space.

   312 */

   313 #define	GLOBAL_MAPPING	((const TAny*)-1)

   315 	/**

   316 @internalComponent

   317 Indicates that corresponding linear address applies to kernel process (either global or Kernel's local space).

   318 */

   319 #define	KERNEL_MAPPING	((TInt)0)

   322 /**

   323 @internalComponent

   324 */

   325 class Mmu : public MmuBase

   326 	{

   327 public:

   328 	enum TFlushFlags	{

   329 						EFlushDTLB=0x01,

   330 						EFlushDCache=0x02,

   331 						EFlushITLB=0x04,

   332 						EFlushICache=0x08,

   333 						EFlushDDecommit=0x80000000,

   334 						EFlushDPermChg=0x20000000,

   335 						EFlushDMove=0x40000000,

   336 						EFlushIPermChg=0x04000000,

   337 						EFlushIMove=0x10000000,

   338 						EFlushInheritMask=EFlushDPermChg|EFlushDMove|EFlushIPermChg|EFlushIMove,

   339 						};

   341 	enum TPanic

   342 		{

   343 		ELocalPageDirBadAsid,

   344 		EGlobalPageDirBadAsid,

   345 		EPDEBadAsid,

   346 		EFreeOsAsidBadAsid,

   347 		EOsAsidAllocCreateFailed,

   348 		EBadInitialPageAddr,

   349 		EAssignPageTableInvalidUsage,

   350 		EUserCodeAllocatorCreateFailed,

   351 		EDllDataAllocatorCreateFailed,

   352 		ERomUserDataAddressInvalid,

   353 		ERomUserDataSizeInvalid,

   354 		ECreateSharedSectionFailed,

   355 		ECreateUserGlobalSectionFailed,

   356 		ERemapPageFailed,

   357 		ERemapPageTableFailed,

   358 		EFixupXPTFailed,

   359 		ETempMappingFailed,

   360 		EDefragDisablePageFailed,

   361 		EDefragFaultWhilstFMHeld,

   362 		};

   364 public:

   365 	TPde* LocalPageDir(TInt aOsAsid);

   366 	TPde* GlobalPageDir(TInt aOsAsid);

   367 	TPde& PDE(TLinAddr aAddr, TInt aOsAsid);

   368 	TInt NewOsAsid(TBool aSeparateGlobal);

   369 	void FreeOsAsid(TInt aOsAsid);

   370 	void CreateUserGlobalSection(TLinAddr aBase, TLinAddr aEnd);

   371 	TInt CreateGlobalCodeChunk();

   373 	// virtual - inherited/overridden from MmuBase

   374 	virtual void Init1();

   375 //	virtual void Init2();

   376 	virtual void DoInit2();

   377 //	virtual TBool PteIsPresent(TPte aPte)=0;

   378 //	virtual TPhysAddr PtePhysAddr(TPte aPte, TInt aPteIndex)=0;

   379 //	virtual TPhysAddr PdePhysAddr(TLinAddr aAddr)=0;

   380 	virtual void SetupInitialPageInfo(SPageInfo* aPageInfo, TLinAddr aChunkAddr, TInt aPdeIndex);

   381 	virtual void SetupInitialPageTableInfo(TInt aId, TLinAddr aChunkAddr, TInt aNumPtes);

   382 	virtual void AssignPageTable(TInt aId, TInt aUsage, TAny* aObject, TLinAddr aAddr, TPde aPdePerm);

   383 	virtual TInt UnassignPageTable(TLinAddr aAddr);

   384 //	virtual void BootstrapPageTable(TInt aXptId, TPhysAddr aXptPhys, TInt aId, TPhysAddr aPhysAddr)=0;

   385 	virtual TInt PageTableId(TLinAddr aAddr);

   386 //	virtual TInt BootPageTableId(TLinAddr aAddr, TPhysAddr& aPtPhys)=0;

   387 //	virtual void ClearPageTable(TInt aId, TInt aFirstIndex=0)=0;

   388 	virtual TPhysAddr LinearToPhysical(TLinAddr aAddr);

   389 	virtual TInt LinearToPhysical(TLinAddr aAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList=NULL);

   390 //	virtual void MapRamPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, const TPhysAddr* aPageList, TInt aNumPages, TPte aPtePerm)=0;

   391 //	virtual void MapPhysicalPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, TPhysAddr aPhysAddr, TInt aNumPages, TPte aPtePerm)=0;

   392 //	virtual TInt UnmapPages(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TBool aSetPagesFree, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess)=0;

   393 //	virtual void ClearRamDrive(TLinAddr aStart)=0;

   394 //	virtual TInt PdePtePermissions(TUint& aMapAttr, TPde& aPde, TPte& aPte)=0;

   395 //	virtual void Map(TLinAddr aLinAddr, TPhysAddr aPhysAddr, TInt aSize, TPde aPdePerm, TPte aPtePerm, TInt aMapShift)=0;

   396 //	virtual void Unmap(TLinAddr aLinAddr, TInt aSize)=0;

   397 //	virtual void InitShadowPageTable(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0;

   398 //	virtual void InitShadowPage(TPhysAddr aShadowPhys, TLinAddr aRomAddr)=0;

   399 //	virtual void DoUnmapShadowPage(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0;

   400 //	virtual TInt UnassignShadowPageTable(TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0;

   401 //	virtual void DoFreezeShadowPage(TInt aId, TLinAddr aRomAddr)=0;

   402 //	virtual void FlushShadow(TLinAddr aRomAddr)=0;

   403 //	virtual void AssignShadowPageTable(TInt aId, TLinAddr aRomAddr)=0;

   404 //	virtual void ClearPages(TInt aNumPages, TPhysAddr* aPageList)=0;

   405 	virtual TPte PtePermissions(TChunkType aChunkType)=0;

   406 	virtual TInt MoveKernelPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest);

   407 	virtual TInt MoveCodeSegMemoryPage(DMemModelCodeSegMemory* aCodeSegMemory, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest);

   408 	virtual TInt MoveCodeChunkPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest);

   409 	virtual TInt MoveDataChunkPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest);

   411 	// pure virtual - new in Mmu

   412 	virtual TInt NewPageDirectory(TInt aOsAsid, TBool aSeparateGlobal, TPhysAddr& aPhysAddr, TInt& aNumPages)=0;

   413 	virtual void InitPageDirectory(TInt aOsAsid, TBool aGlobal)=0;

   414 	virtual TInt PageTableId(TLinAddr aAddr, TInt aOsAsid)=0;

   415 	virtual TPhysAddr LinearToPhysical(TLinAddr aAddr, TInt aOsAsid)=0;

   416 	virtual TInt LinearToPhysical(TLinAddr aAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList, TInt aOsAsid)=0;

   417 	virtual TInt PreparePagesForDMA(TLinAddr aAddr, TInt aSize, TInt aOsAsid, TPhysAddr* aPhysicalPageList)=0;

   418 	virtual TInt ReleasePagesFromDMA(TPhysAddr* aPhysicalPageList, TInt aPageCount)=0;

   419 	virtual void DoAssignPageTable(TInt aId, TLinAddr aAddr, TPde aPdePerm, const TAny* aOsAsids)=0;

   420 	virtual void RemapPageTableSingle(TPhysAddr aOld, TPhysAddr aNew, TLinAddr aAddr, TInt aOsAsid)=0;

   421 	virtual void RemapPageTableMultiple(TPhysAddr aOld, TPhysAddr aNew, TLinAddr aAddr, const TAny* aOsAsids)=0;

   422 	virtual void RemapPageTableGlobal(TPhysAddr aOld, TPhysAddr aNew, TLinAddr aAddr)=0;

   423 	virtual void RemapPageTableAliases(TPhysAddr aOld, TPhysAddr aNew)=0;

   424 	virtual void DoUnassignPageTable(TLinAddr aAddr, const TAny* aOsAsids)=0;

   425 	virtual TPde PdePermissions(TChunkType aChunkType, TBool aRO)=0;

   426 	virtual void ApplyTopLevelPermissions(TLinAddr aAddr, TInt aOsAsid, TInt aNumPdes, TPde aPdePerm)=0;

   427 	virtual void ApplyPagePermissions(TInt aId, TInt aPageOffset, TInt aNumPages, TPte aPtePerm)=0;

   428 	virtual void GenericFlush(TUint32 aMask)=0;

   429 	virtual TLinAddr MapTemp(TPhysAddr aPage,TLinAddr aLinAddr, TInt aPages=1)=0;

   430 	virtual TLinAddr MapTemp(TPhysAddr aPage,TLinAddr aLinAddr,TInt aPages, TMemoryType aMemType)=0;

   431 	virtual TLinAddr MapSecondTemp(TPhysAddr aPage,TLinAddr aLinAddr, TInt aPages=1)=0;

   432 	virtual void UnmapTemp()=0;

   433 	virtual void UnmapSecondTemp()=0;

   434 	virtual TBool ValidateLocalIpcAddress(TLinAddr aAddr,TInt aSize,TBool aWrite)=0;

   435 	virtual TInt UnlockRamCachePages(TLinAddr aLinAddr, TInt aNumPages, DProcess* aProcess)=0;

   436 	virtual TInt LockRamCachePages(TLinAddr aLinAddr, TInt aNumPages, DProcess* aProcess)=0;

   437 	virtual void MapVirtual(TInt aId, TInt aNumPages)=0;

   438 	virtual TInt UnmapUnownedPages(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TLinAddr* aLAPageList, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess)=0;

   439 	virtual TInt UnmapVirtual(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TBool aSetPagesFree, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess)=0;

   440 	virtual TInt UnmapUnownedVirtual(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TLinAddr* aLAPageList, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess)=0;

   441 	virtual void RemapPageByAsid(TBitMapAllocator* aOsAsids, TLinAddr aLinAddr, TPhysAddr aOldAddr, TPhysAddr aNewAddr, TPte aPtePerm)=0;

   442 	virtual void CacheMaintenanceOnDecommit(const TPhysAddr* aPhysAddr, TInt aPageCount)=0;

   443 	virtual void CacheMaintenanceOnDecommit(const TPhysAddr aPhysAddr)=0; // Maintains physical (VIPT & PIPT) cache for pages to be reused.

   444 	virtual void CacheMaintenanceOnPreserve(const TPhysAddr* aPhysAddr, TInt aPageCount, TUint iMapAttr)=0;

   445 	virtual void CacheMaintenanceOnPreserve(const TPhysAddr aPhysAddr, TUint iMapAttr)=0;

   446 	virtual void CacheMaintenanceOnPreserve(TPhysAddr aPhysAddr, TInt aSize, TLinAddr aLinAddr, TUint iMapAttr)=0;

   448 public:

   449 	inline static Mmu& Get()

   450 		{return *(Mmu*)TheMmu;}

   451 	static void Panic(TPanic aPanic);

   452 public:

   453 	TInt iNumOsAsids;

   454 	TInt iNumGlobalPageDirs;

   455 	TBitMapAllocator* iOsAsidAllocator;

   456 	TInt iGlobalPdSize;

   457 	TInt iGlobalPdShift;

   458 	TInt iLocalPdSize;

   459 	TInt iLocalPdShift;

   460 	TInt iAsidGroupSize;			// number of global page directories mapped by a page table

   461 	TInt iAsidGroupMask;			// number of global page directories mapped by a page table - 1

   462 	TInt iAsidGroupShift;			// log2(number of global page directories mapped by a page table)

   463 	TInt iAliasSize;				// minimum allowed spacing between synonyms of any physical address

   464 	TInt iAliasMask;

   465 	TInt iAliasShift;

   466 	TLinAddr iUserLocalBase;		// lowest local data address

   467 	TLinAddr iUserLocalEnd;			// 1+highest local data address (lowest DLL data address)

   468 	TLinAddr iUserSharedBase;		// lowest shared data address (1+highest DLL data address)

   469 	TLinAddr iUserSharedEnd;		// 1+highest shared data address (=local PD size)

   470 	TLinAddr iDllDataBase;

   471 	TInt iMaxDllDataSize;

   472 	TLinAddr iUserCodeBase;

   473 	TInt iMaxUserCodeSize;

   474 	TUint32* iAsidInfo;

   475 	TLinAddr iPdeBase;

   476 	TPte iPdPtePerm;

   477 	TPde iPdPdePerm;

   478 	TPte iUserCodeLoadPtePerm;

   479 	TPte iKernelCodePtePerm;

   480 	TPte iGlobalCodePtePerm;

   481 	TUint32 iRamDriveMask;

   482 	TLinearSection* iSharedSection;

   483 	TLinearSection* iUserGlobalSection;

   484 	DMemModelChunk* iGlobalCode;

   485 	SDblQue iAliasList;

   486 	TInt iTempMapCount;

   487 	TInt iSecondTempMapCount;

   488 	TPte* iSecondTempPte;		// second PTE used for temporary mappings

   489 	TLinAddr iSecondTempAddr;	// address corresponding to iSecondTempPte

   490 	TInt iCacheMaintenanceTempMapAttr;	// holds SP_PTE's attr. entry for cache maintenance

   491 										// temporary mapping.

   492 public:

   493 	friend class Monitor;

   494 	friend TPte& PageTableEntry(TLinAddr aLinAddr);

   495 	};

   498 /********************************************

   499  * Functions/Data defined in memory model

   500  ********************************************/

   502 /**

   503 @internalComponent

   504 */

   505 class MM

   506 	{

   507 public:

   508 	enum TMemModelPanic

   509 		{

   510 		EChunkTransferBadOwner=0,

   511 		EChunkDecommitNoPageTable=1,

   512 		EChunkTransferAllocAddrFailed=2,

   513 		EFsRegisterThread=3,

   514 		EClaimInitialPagesBadPageTable=4,

   515 		EChunkNotDisconnected1=5,

   516 		EChunkNotDisconnected2=6,

   517 		EChunkCommitNoPageTable=7,

   518 		EProcessDestructChunksRemaining=8,

   519 		ECommitInvalidDllDataAddress=9,

   520 		EDecommitInvalidDllDataAddress=10,

   521 		EChunkApplyPermissions1=11,

   522 		EChunkApplyPermissions2=12,

   523 		ECodeSegLoadedNotCreator=13,

   524 		EChunkBadAddressRange=14,

   525 		EPdeAlreadyInUse=15,

   526 		EPteAlreadyInUse=16,

   527 		EMmuMapNoPageTable=17,

   528 		EUnmapBadAlignment=18,

   529 		EBootstrapPageTableBadAddr=19,

   530 		ETempMappingAlreadyInUse=20,

   531 		EDecommitFailed=21,

   532 		EPageTableNotFound=22,

   533 		EUnexpectedPageType=23,

   534 		EOperationNotSupported=24,

   535 		EChunkRemapNoPageTable=25,

   536 		EChunkRemapUnsupported=26,

   537 		ECodeSegRemapWrongPage=27,

   538 		EChunkRemapWrongPageTable=28,

   539 		ETempMappingNoRoom=29,

   540 		};

   542 	static void Panic(TMemModelPanic aPanic);

   543 public:

   544 	static void Init1();

   545 	static void StartCrashDebugger();

   546 public:

   547 	static TInt MaxPagesInOneGo;

   548 	static DMemModelChunk* SvStackChunk;

   549 	static DMemModelChunk* TheRamDriveChunk;

   550 	static TBitMapAllocator* UserCodeAllocator;

   551 	static TBitMapAllocator* DllDataAllocator;

   552 	};

   554 #endif

author	sl
	Tue, 10 Jun 2014 14:32:02 +0200
changeset 1	260cb5ec6c19
permissions	-rw-r--r--