1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/rm_debug/d_rmdebug_step_test.s Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,266 @@
1.4 +; Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +; All rights reserved.
1.6 +; This component and the accompanying materials are made available
1.7 +; under the terms of the License "Eclipse Public License v1.0"
1.8 +; which accompanies this distribution, and is available
1.9 +; at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +;
1.11 +; Initial Contributors:
1.12 +; Nokia Corporation - initial contribution.
1.13 +;
1.14 +; Contributors:
1.15 +;
1.16 +; Description:
1.17 +;
1.18 +
1.19 + AREA |d-rmdebug-bkpt$$Code|, CODE, READONLY, ALIGN=6
1.20 +
1.21 + CODE32
1.22 +
1.23 + ; ARM tests
1.24 +
1.25 +;
1.26 +; Non-PC modifying
1.27 +;
1.28 + EXPORT RMDebug_StepTest_Non_PC_Modifying
1.29 + EXPORT RMDebug_StepTest_Non_PC_Modifying_OK
1.30 +
1.31 +RMDebug_StepTest_Non_PC_Modifying
1.32 + mov r0,r0 ; nop
1.33 +RMDebug_StepTest_Non_PC_Modifying_OK
1.34 + bx lr ; should return to normal execution of the test thread
1.35 +
1.36 +;
1.37 +; Branch
1.38 +;
1.39 + EXPORT RMDebug_StepTest_Branch
1.40 + EXPORT RMDebug_StepTest_Branch_1
1.41 +
1.42 +RMDebug_StepTest_Branch
1.43 + b RMDebug_StepTest_Branch_1
1.44 + mov r0, #2 ; if the pc ends up here, we know its gone wrong
1.45 +RMDebug_StepTest_Branch_1
1.46 + bx lr ; return
1.47 +
1.48 +;
1.49 +; Branch and Link
1.50 +;
1.51 + EXPORT RMDebug_StepTest_Branch_And_Link
1.52 + EXPORT RMDebug_StepTest_Branch_And_Link_1
1.53 + EXPORT RMDebug_StepTest_Branch_And_Link_2
1.54 +
1.55 +RMDebug_StepTest_Branch_And_Link
1.56 + mov r0, lr ; preserve lr for the moment
1.57 +RMDebug_StepTest_Branch_And_Link_1
1.58 + bl RMDebug_StepTest_Branch_And_Link_2
1.59 + mov r1, #1 ; insert a gap in the instruction stream so we know we branched.
1.60 +RMDebug_StepTest_Branch_And_Link_2
1.61 + mov lr, r0 ; restore lr
1.62 + bx lr ; should return to normal execution of the test thread
1.63 +
1.64 +;
1.65 +; MOV PC
1.66 +;
1.67 + EXPORT RMDebug_StepTest_MOV_PC
1.68 + EXPORT RMDebug_StepTest_MOV_PC_1
1.69 + EXPORT RMDebug_StepTest_MOV_PC_2
1.70 +
1.71 +RMDebug_StepTest_MOV_PC
1.72 + mov r0, #4
1.73 +RMDebug_StepTest_MOV_PC_1
1.74 + add pc, pc, r0 ; should be a jump (bear in mind reading pc = current inst + 8bytes for arm)
1.75 + mov r0, #1 ; Simple instructions which allow us to test where the PC really is
1.76 + mov r0, #2 ; just by reading r0.
1.77 +RMDebug_StepTest_MOV_PC_2
1.78 + mov r0, #3 ;
1.79 + mov r0, #4 ;
1.80 + bx lr ; should return to normal execution of the test thread
1.81 +
1.82 +;
1.83 +; LDR PC
1.84 +;
1.85 + EXPORT RMDebug_StepTest_LDR_PC
1.86 + EXPORT RMDebug_StepTest_LDR_PC_1
1.87 +
1.88 +RMDebug_StepTest_LDR_PC
1.89 + ldr pc, =RMDebug_StepTest_LDR_PC_1
1.90 + mov r0, #1 ; separate the branch target so we can prove it works
1.91 +RMDebug_StepTest_LDR_PC_1
1.92 + bx lr ; should return to normal execution of the test thread
1.93 +
1.94 +;
1.95 +; ARM -> Thumb -> ARM interworking test
1.96 +;
1.97 +; Note: We always start and finish this test
1.98 +; in ARM mode.
1.99 + EXPORT RMDebug_StepTest_Interwork
1.100 + EXPORT RMDebug_StepTest_Interwork_1
1.101 + EXPORT RMDebug_StepTest_Interwork_2
1.102 + EXPORT RMDebug_StepTest_Interwork_3
1.103 +RMDebug_StepTest_Interwork
1.104 + mov r0, lr ; preserve lr
1.105 +RMDebug_StepTest_Interwork_1
1.106 + blx RMDebug_StepTest_Interwork_2
1.107 +
1.108 + CODE16
1.109 +RMDebug_StepTest_Interwork_2
1.110 + blx RMDebug_StepTest_Interwork_3
1.111 +
1.112 + CODE32
1.113 +
1.114 +RMDebug_StepTest_Interwork_3
1.115 + bx r0
1.116 +
1.117 +;
1.118 +; Stepping performance tests
1.119 +;
1.120 +; This counts down from 100000 to 0
1.121 +; This means that for all practical purposes
1.122 +; we can single-step as much as we like
1.123 +; in less than one second and have some likelyhood
1.124 +; that we will not step too far from our loop
1.125 +
1.126 + EXPORT RMDebug_StepTest_Count
1.127 + EXPORT RMDebug_StepTest_Count_1
1.128 + EXPORT RMDebug_StepTest_Count_2
1.129 +
1.130 +RMDebug_StepTest_Count
1.131 + ldr r2, =100000
1.132 +RMDebug_StepTest_Count_1
1.133 + subs r2, r2, #1
1.134 +RMDebug_StepTest_Count_2
1.135 + bne RMDebug_StepTest_Count_1
1.136 + bx lr
1.137 +
1.138 +; Thumb tests
1.139 +
1.140 +; Thumb non-pc modifying
1.141 +;
1.142 +;
1.143 +RMDebug_StepTest_Thumb_Non_PC_Modifying
1.144 + mov r0, lr ; preserve lr
1.145 + blx RMDebug_StepTest_Thumb_Non_PC_Modifying_1
1.146 + bx r0
1.147 +
1.148 +;
1.149 +; Thumb Branch
1.150 +;
1.151 +RMDebug_StepTest_Thumb_Branch
1.152 + mov r0, lr ; preserve lr
1.153 + blx RMDebug_StepTest_Thumb_Branch_1
1.154 + bx r0
1.155 +
1.156 +;
1.157 +; Thumb Branch and link
1.158 +;
1.159 +RMDebug_StepTest_Thumb_Branch_And_Link
1.160 + mov r0, lr ; preserve lr
1.161 + blx RMDebug_StepTest_Thumb_Branch_And_Link_1
1.162 + bx r0
1.163 +
1.164 +;
1.165 +; Thumb Back Branch and link
1.166 +;
1.167 +RMDebug_StepTest_Thumb_Back_Branch_And_Link
1.168 + mov r0, lr ; preserve lr
1.169 + blx RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
1.170 + bx r0
1.171 +
1.172 +;
1.173 +; Thumb ADD PC,PC, #0
1.174 +;
1.175 +RMDebug_StepTest_Thumb_AddPC
1.176 + mov r0, lr ; preserve lr
1.177 + blx RMDebug_StepTest_Thumb_AddPC_1
1.178 + bx r0
1.179 +
1.180 + CODE16
1.181 +
1.182 + ; Thumb tests
1.183 + EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying
1.184 + EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying_1
1.185 + EXPORT RMDebug_StepTest_Thumb_Non_PC_Modifying_2
1.186 +
1.187 + EXPORT RMDebug_StepTest_Thumb_Branch
1.188 + EXPORT RMDebug_StepTest_Thumb_Branch_1
1.189 + EXPORT RMDebug_StepTest_Thumb_Branch_2
1.190 +
1.191 + EXPORT RMDebug_StepTest_Thumb_Branch_And_Link
1.192 + EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_1
1.193 + EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_2
1.194 + EXPORT RMDebug_StepTest_Thumb_Branch_And_Link_3
1.195 +
1.196 + EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link
1.197 + EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
1.198 + EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_2
1.199 + EXPORT RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
1.200 +
1.201 +RMDebug_StepTest_Thumb_Non_PC_Modifying_1
1.202 + mov r0, r0 ; nop
1.203 +RMDebug_StepTest_Thumb_Non_PC_Modifying_2
1.204 + bx lr
1.205 +
1.206 +RMDebug_StepTest_Thumb_Branch_1
1.207 + b RMDebug_StepTest_Thumb_Branch_2
1.208 + mov r0, r0
1.209 +RMDebug_StepTest_Thumb_Branch_2
1.210 + bx lr
1.211 +
1.212 +RMDebug_StepTest_Thumb_Branch_And_Link_1
1.213 + mov r1, lr
1.214 +RMDebug_StepTest_Thumb_Branch_And_Link_2
1.215 + bl RMDebug_StepTest_Thumb_Branch_And_Link_3
1.216 + mov r0, r0
1.217 +RMDebug_StepTest_Thumb_Branch_And_Link_3
1.218 + bx r1
1.219 +
1.220 +RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
1.221 + bx r1
1.222 +
1.223 +RMDebug_StepTest_Thumb_Back_Branch_And_Link_1
1.224 + mov r1, lr
1.225 +RMDebug_StepTest_Thumb_Back_Branch_And_Link_2
1.226 + bl RMDebug_StepTest_Thumb_Back_Branch_And_Link_3
1.227 + bx r1
1.228 +
1.229 +;
1.230 +; ADD PC
1.231 +;
1.232 + EXPORT RMDebug_StepTest_Thumb_AddPC
1.233 + EXPORT RMDebug_StepTest_Thumb_AddPC_1
1.234 + EXPORT RMDebug_StepTest_Thumb_AddPC_2
1.235 + EXPORT RMDebug_StepTest_Thumb_AddPC_3
1.236 +
1.237 +RMDebug_StepTest_Thumb_AddPC_1
1.238 + mov r1, lr
1.239 + mov r2, #4
1.240 +RMDebug_StepTest_Thumb_AddPC_2
1.241 + add pc, pc, r2 ; should arrive at RMDebug_StepTest_Thumb_AddPC_3
1.242 + mov r0, r0
1.243 + mov r0, r0
1.244 + mov r0, r0
1.245 +RMDebug_StepTest_Thumb_AddPC_3
1.246 + bx r1
1.247 +
1.248 + ALIGN 4
1.249 +
1.250 + CODE32
1.251 +
1.252 +;
1.253 +; ARM multiple-step ( 5 steps )
1.254 +;
1.255 + EXPORT RMDebug_StepTest_ARM_Step_Multiple
1.256 + EXPORT RMDebug_StepTest_ARM_Step_Multiple_1
1.257 +
1.258 +RMDebug_StepTest_ARM_Step_Multiple
1.259 + mov r0,r0 ; nop
1.260 + mov r0,r0 ; nop
1.261 + mov r0,r0 ; nop
1.262 + mov r0,r0 ; nop
1.263 + mov r0,r0 ; nop
1.264 +RMDebug_StepTest_ARM_Step_Multiple_1
1.265 + bx lr
1.266 +
1.267 + END
1.268 +
1.269 +; End of file - d_rmdebug_bkpt.s