1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/misc/strataflash32.cpp	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,145 @@
     1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +// e32test\misc\strataflash32.cpp
    1.18 +// 
    1.19 +//
    1.20 +
    1.21 +#include <e32def.h>
    1.22 +#include <e32def_private.h>
    1.23 +#include "flash.h"
    1.24 +
    1.25 +#include <e32test.h>
    1.26 +GLREF_C RTest test;
    1.27 +
    1.28 +class StrataFlash32 : public Flash
    1.29 +	{
    1.30 +public:
    1.31 +	virtual TInt Read(TUint32 anAddr, TUint32 aSize, TUint8* aDest);
    1.32 +	virtual TInt BlankCheck(TUint32 anAddr, TUint32 aSize);
    1.33 +	virtual TInt Erase(TUint32 anAddr, TUint32 aSize);
    1.34 +	virtual TInt Write(TUint32 anAddr, TUint32 aSize, const TUint8* aSrc);
    1.35 +	};
    1.36 +
    1.37 +
    1.38 +Flash* Flash::New(TUint32 /*anAddr*/)
    1.39 +	{
    1.40 +	return new StrataFlash32;
    1.41 +	}
    1.42 +
    1.43 +TInt StrataFlash32::Read(TUint32 anAddr, TUint32 aSize, TUint8* aDest)
    1.44 +	{
    1.45 +	Mem::Move(aDest,(const TUint32*)anAddr,aSize);
    1.46 +	return KErrNone;
    1.47 +	}
    1.48 +
    1.49 +TInt StrataFlash32::BlankCheck(TUint32 anAddr, TUint32 aSize)
    1.50 +	{
    1.51 +	const TUint32* p=(const TUint32*)anAddr;
    1.52 +	const TUint32* pE=p+(aSize+3)/4;
    1.53 +	while(p<pE)
    1.54 +		{
    1.55 +		if (*p++!=0xffffffff)
    1.56 +			return (TUint32)p-anAddr;
    1.57 +		}
    1.58 +	return 0;
    1.59 +	}
    1.60 +
    1.61 +TInt StrataFlash32::Erase(TUint32 anAddr, TUint32 aSize)
    1.62 +	{
    1.63 +	TUint32 base=anAddr&~0x3ffff;	// round base address down to block
    1.64 +	TUint32 end=anAddr+aSize;
    1.65 +	end=(end+0x3ffff)&~0x3ffff;	// round end address up to block
    1.66 +	TUint32 size=end-base;
    1.67 +	volatile TUint32* p=(volatile TUint32*)base;
    1.68 +	*p=0x00500050;	// clear status reg
    1.69 +	for (; size; size-=0x40000, p+=0x40000/4)
    1.70 +		{
    1.71 +		*p=0x00200020;	// block erase
    1.72 +		*p=0x00d000d0;	// block erase confirm
    1.73 +		while ((*p & 0x00800080)!=0x00800080) {}
    1.74 +		TUint32 s=*p;
    1.75 +		*p=0x00500050;	// clear status reg
    1.76 +		*p=0x00ff00ff;	// read mode
    1.77 +		if (s&0x00200020)
    1.78 +			{
    1.79 +			// error
    1.80 +			return (TUint32)p-anAddr+1;
    1.81 +			}
    1.82 +		}
    1.83 +	return 0;
    1.84 +	}
    1.85 +
    1.86 +TInt StrataFlash32::Write(TUint32 anAddr, TUint32 aSize, const TUint8* aSrc)
    1.87 +	{
    1.88 +	volatile TUint32* p=(volatile TUint32*)anAddr;
    1.89 +	const TUint32* pS=(const TUint32*)aSrc;
    1.90 +	aSize=(aSize+63)&~63;
    1.91 +/*
    1.92 +	const TUint32* pE=pS+aSize/4;
    1.93 +	for (; pS<pE; pS++, p++)
    1.94 +		{
    1.95 +		*p=0x00400040;	// word write
    1.96 +		*p=*pS;		// write data
    1.97 +		while ((*p & 0x00800080)!=0x00800080);
    1.98 +		TUint32 s=*p;
    1.99 +		*p=0x00500050;	// clear status reg
   1.100 +		*p=0x00ff00ff;	// read mode
   1.101 +		if (s&0x00100010)
   1.102 +			{
   1.103 +			// error
   1.104 +			return (TUint32)p-anAddr+1;
   1.105 +			}
   1.106 +		}
   1.107 +*/
   1.108 +
   1.109 +	TUint32 s=0;
   1.110 +	*p=0x00500050;	// clear status reg
   1.111 +	while(aSize)
   1.112 +		{
   1.113 +		TUint32 wb_offset=((TUint32)p)&0x3f;
   1.114 +		TUint32 max_count=(64-wb_offset)/4;
   1.115 +		TUint32 count=Min(aSize/4,max_count);
   1.116 +		TUint32 cwd=count-1;
   1.117 +		cwd|=(cwd<<16);
   1.118 +
   1.119 +		s=0;
   1.120 +		do	{
   1.121 +			*p=0x00e800e8;	// Write to Buffer
   1.122 +			*p=0x00700070;	// Read status register
   1.123 +			s=*p;
   1.124 +			} while ((s&0x00800080)!=0x00800080);
   1.125 +		s=*p;
   1.126 +		*p=cwd;
   1.127 +		TUint32 i;
   1.128 +		for (i=0; i<count; ++i)
   1.129 +			*p++=*pS++;
   1.130 +		*p=0x00d000d0;	// Write confirm
   1.131 +		aSize-=4*count;
   1.132 +		while ((*p & 0x00800080)!=0x00800080) {}	// Wait for write to complete
   1.133 +		s=*p;
   1.134 +		if (s&0x00300030)
   1.135 +			break;
   1.136 +		}
   1.137 +	*p=0x00500050;	// clear status reg
   1.138 +	*p=0x00ff00ff;	// read mode
   1.139 +	if (s&0x00300030)
   1.140 +		{
   1.141 +		// error
   1.142 +		return (TUint32)p-anAddr+1;
   1.143 +		}
   1.144 +
   1.145 +	return 0;
   1.146 +	}
   1.147 +
   1.148 +