1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/debug/d_debugapi.cia	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,67 @@
     1.4 +// Copyright (c) 2005-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +// e32test\debug\d_debugapi.cia
    1.18 +// 
    1.19 +//
    1.20 +
    1.21 +#include <arm.h>
    1.22 +#include "d_debugapi.h"
    1.23 +
    1.24 +__NAKED__ TInt DDebugAPIChecker::ReadFromOtherProcessArmv6()
    1.25 +	{	
    1.26 +
    1.27 +	//Save regs.
    1.28 +    asm("stmfd    sp!,{r4-r7,lr}");
    1.29 +
    1.30 +	//Copy all data we need into regs. We can not access the memory of ...
    1.31 +	//...the current process once we start changing MMU content.
    1.32 +	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iOtherProcess_OsAsid));
    1.33 +	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iOtherProcess_LocalPageDir));
    1.34 +	asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iCurrentProcess_OsAsid));
    1.35 +	asm("ldr r4, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iCurrentProcess_LocalPageDir));
    1.36 +	asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iAddress));
    1.37 +
    1.38 +	asm("mrc p15, 0, r6, c2, c0, 0 ");
    1.39 +	asm("and r6, r6, #0x7f ");			// r6 = page table cache/sharing attributes
    1.40 +	asm("orr r2, r2, r6 ");				// add in to other process page directory address
    1.41 +	asm("orr r4, r4, r6 ");				// add in to this process page directory address
    1.42 +	asm("mov r6, #0 ");
    1.43 +
    1.44 +	//Disable interrupts
    1.45 +	asm("mov r7, #0xd3 ");
    1.46 +	asm("msr cpsr, r7 ");
    1.47 +
    1.48 +	//Switch MMU to the-other-process
    1.49 +	asm("mcr p15, 0, r6, c7, c10, 4 ");	// drain write buffer before changing MMU registers (see ARMv6 specs)
    1.50 +//!	asm("orr r2, r2 #0x18"); //Uncomment this line on 1136 (r0p2) with L2 cache due to Erratum 317041.	
    1.51 +	asm("mcr p15, 0, r2, c2, c0, 0 ");		// set TTBR0 - no TLB flush required due to ASID
    1.52 +	asm("mcr p15, 0, r1, c13, c0, 1 ");		// set ASID
    1.53 +
    1.54 +	//Read the memory from the-other-process
    1.55 +	asm("ldr r0, [r5]");
    1.56 +
    1.57 +	//Switch MMU back to the-current-process
    1.58 +	asm("mcr p15, 0, r6, c7, c10, 4 ");	// drain write buffer before changing MMU registers (see ARMv6 specs)
    1.59 +//!	asm("orr r4, r4 #0x18"); //Uncomment this line on 1136 (r0p2) with L2 cache due to Erratum 317041.	
    1.60 +	asm("mcr p15, 0, r4, c2, c0, 0 ");		// set TTBR0 - no TLB flush required due to ASID
    1.61 +	asm("mcr p15, 0, r3, c13, c0, 1 ");		// set ASID
    1.62 +
    1.63 +
    1.64 +	//Re-enable interrupts
    1.65 +	asm("mov r7, #0x13 ");
    1.66 +	asm("msr cpsr, r7 ");
    1.67 +	
    1.68 +	//Return
    1.69 +    asm("ldmfd    sp!,{r4-r7,pc}");
    1.70 +	}