1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kerneltest/e32test/debug/context.cia Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,321 @@
1.4 +// Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32test\debug\context.cia
1.18 +//
1.19 +//
1.20 +
1.21 +#ifndef __KERNEL_MODE__
1.22 +#include "context.h"
1.23 +#include <u32exec.h>
1.24 +
1.25 +__NAKED__ void SetRegs()
1.26 + {
1.27 + asm("SetRegs:");
1.28 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR0));
1.29 + asm("add r1, r1, #1 ");
1.30 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR1));
1.31 + asm("add r2, r1, #1 ");
1.32 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR2));
1.33 + asm("add r3, r2, #1 ");
1.34 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR3));
1.35 + asm("add r4, r3, #1 ");
1.36 + asm("str r4, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR4));
1.37 + asm("add r5, r4, #1 ");
1.38 + asm("str r5, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR5));
1.39 + asm("add r6, r5, #1 ");
1.40 + asm("str r6, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR6));
1.41 + asm("add r7, r6, #1 ");
1.42 + asm("str r7, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR7));
1.43 + asm("add r8, r7, #1 ");
1.44 + asm("str r8, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR8));
1.45 + asm("add r9, r8, #1 ");
1.46 + asm("str r9, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR9));
1.47 + asm("add r10, r9, #1 ");
1.48 + asm("str r10, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR10));
1.49 + asm("add r11, r10, #1 ");
1.50 + asm("str r11, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR11));
1.51 + asm("add r12, r11, #1 ");
1.52 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR12));
1.53 + asm("str r13, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR13));
1.54 + asm("str r14, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR14));
1.55 + asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,iR0));
1.56 + __JUMP(,lr);
1.57 + }
1.58 +
1.59 +#define CHECK_REGA(reg,val) \
1.60 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,reg)); \
1.61 + asm("ldr r3, ="#val); \
1.62 + asm("cmp r2, r3"); \
1.63 + asm("movne r0, #0"); \
1.64 + __JUMP(ne,lr);
1.65 +
1.66 +#define CHECK_REG(reg) \
1.67 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TArmRegSet,reg)); \
1.68 + asm("ldr r3, [r1, #%a0]" : : "i" _FOFF(TArmRegSet,reg)); \
1.69 + asm("cmp r2, r3"); \
1.70 + asm("movne r0, #0"); \
1.71 + __JUMP(ne,lr);
1.72 +
1.73 +
1.74 +
1.75 +__NAKED__ TInt ThreadContextHwExc(TAny*)
1.76 + {
1.77 + asm("stmdb sp!, {r4-r11,lr} ");
1.78 + asm("mov r1, #0x80000000");
1.79 + asm("bl SetRegs");
1.80 + asm("ldr r0,[r13, #1]"); // Cause alignment fault
1.81 + asm("ThreadContextHwExc_pc:");
1.82 + asm("mov r0, #0 ");
1.83 + asm("ldmia sp!, {r4-r11,pc} ");
1.84 + }
1.85 +
1.86 +__NAKED__ TInt CheckContextHwExc(TArmRegSet* aContext,TArmRegSet* aSavedData)
1.87 + {
1.88 + CHECK_REG(iR0);
1.89 + CHECK_REG(iR1);
1.90 + CHECK_REG(iR2);
1.91 + CHECK_REG(iR3);
1.92 + CHECK_REG(iR4);
1.93 + CHECK_REG(iR5);
1.94 + CHECK_REG(iR6);
1.95 + CHECK_REG(iR7);
1.96 + CHECK_REG(iR8);
1.97 + CHECK_REG(iR9);
1.98 + CHECK_REG(iR10);
1.99 + CHECK_REG(iR11);
1.100 + CHECK_REG(iR12);
1.101 + CHECK_REG(iR13);
1.102 + CHECK_REG(iR14);
1.103 + CHECK_REGA(iR15,ThreadContextHwExc_pc)
1.104 + asm("mov r0,#1");
1.105 + __JUMP(,lr);
1.106 + }
1.107 +
1.108 +
1.109 +
1.110 +__NAKED__ TInt ThreadContextUserInt(TAny*)
1.111 + {
1.112 + asm("mov r1, #0x70000000");
1.113 + asm("bl SetRegs");
1.114 + asm("ThreadContextUserInt_pc:");
1.115 + asm("b ThreadContextUserInt_pc");
1.116 + }
1.117 +
1.118 +__NAKED__ TInt CheckContextUserInt(TArmRegSet*,TArmRegSet*)
1.119 + {
1.120 + CHECK_REG(iR0);
1.121 + CHECK_REG(iR1);
1.122 + CHECK_REG(iR2);
1.123 + CHECK_REG(iR3);
1.124 + CHECK_REG(iR4);
1.125 + CHECK_REG(iR5);
1.126 + CHECK_REG(iR6);
1.127 + CHECK_REG(iR7);
1.128 + CHECK_REG(iR8);
1.129 + CHECK_REG(iR9);
1.130 + CHECK_REG(iR10);
1.131 + CHECK_REG(iR11);
1.132 + CHECK_REG(iR12);
1.133 + CHECK_REG(iR13);
1.134 + CHECK_REG(iR14);
1.135 + CHECK_REGA(iR15,ThreadContextUserInt_pc)
1.136 + asm("mov r0,#1");
1.137 + __JUMP(,lr);
1.138 + }
1.139 +
1.140 +__NAKED__ TInt CheckContextUserIntDied(TArmRegSet*,TArmRegSet*)
1.141 + {
1.142 + CHECK_REG(iR0);
1.143 + CHECK_REG(iR1);
1.144 + CHECK_REG(iR2);
1.145 + CHECK_REG(iR3);
1.146 + CHECK_REG(iR12);
1.147 + CHECK_REG(iR13);
1.148 + CHECK_REG(iR14);
1.149 + CHECK_REGA(iR15,ThreadContextUserInt_pc)
1.150 + asm("mov r0,#1");
1.151 + __JUMP(,lr);
1.152 + }
1.153 +
1.154 +
1.155 +__NAKED__ TInt ThreadContextWFAR(TAny*)
1.156 + {
1.157 + asm("stmdb sp!, {r4-r11,lr} ");
1.158 + asm("mov r1, #0x60000000");
1.159 + asm("bl SetRegs");
1.160 + asm("adr lr, ThreadContextWFAR_return");
1.161 + FAST_EXEC0(EFastExecWaitForAnyRequest);
1.162 + asm("ThreadContextWFAR_return:");
1.163 + asm("mov r0, #0 ");
1.164 + asm("ldmia sp!, {r4-r11,pc} ");
1.165 + }
1.166 +
1.167 +__NAKED__ TInt CheckContextWFAR(TArmRegSet*,TArmRegSet*)
1.168 + {
1.169 + CHECK_REG(iR4);
1.170 + CHECK_REG(iR5);
1.171 + CHECK_REG(iR6);
1.172 + CHECK_REG(iR7);
1.173 + CHECK_REG(iR8);
1.174 + CHECK_REG(iR9);
1.175 + CHECK_REG(iR10);
1.176 + CHECK_REG(iR11);
1.177 + CHECK_REG(iR13);
1.178 + CHECK_REGA(iR14,ThreadContextWFAR_return)
1.179 + CHECK_REGA(iR15,ThreadContextWFAR_return - 4)
1.180 + asm("mov r0,#1");
1.181 + __JUMP(,lr);
1.182 + }
1.183 +
1.184 +__NAKED__ TInt CheckContextWFARDied(TArmRegSet*,TArmRegSet*)
1.185 + {
1.186 + CHECK_REG(iR13);
1.187 + CHECK_REGA(iR14,ThreadContextWFAR_return)
1.188 + CHECK_REGA(iR15,ThreadContextWFAR_return - 4)
1.189 + asm("mov r0,#1");
1.190 + __JUMP(,lr);
1.191 + }
1.192 +
1.193 +
1.194 +
1.195 +__NAKED__ TInt ThreadContextExecCall(TAny*)
1.196 + {
1.197 + asm("stmdb sp!, {r4-r11,lr} ");
1.198 + asm("mov r1, #0x50000000");
1.199 + asm("bl SetRegs");
1.200 + asm("adr lr, ThreadContextExecCall_return");
1.201 + asm("ldr r0, current_thread_handle ");
1.202 + SLOW_EXEC1(EExecThreadSuspend);
1.203 + asm("ThreadContextExecCall_return:");
1.204 + asm("mov r0, #0 ");
1.205 + asm("ldmia sp!, {r4-r11,pc} ");
1.206 + asm("current_thread_handle: ");
1.207 + asm(".word 0xffff8001 ");
1.208 + }
1.209 +
1.210 +__NAKED__ TInt CheckContextExecCall(TArmRegSet*,TArmRegSet*)
1.211 + {
1.212 + CHECK_REG(iR4);
1.213 + CHECK_REG(iR5);
1.214 + CHECK_REG(iR6);
1.215 + CHECK_REG(iR7);
1.216 + CHECK_REG(iR8);
1.217 + CHECK_REG(iR9);
1.218 + CHECK_REG(iR10);
1.219 + CHECK_REG(iR11);
1.220 + CHECK_REG(iR13);
1.221 + CHECK_REGA(iR14,ThreadContextExecCall_return)
1.222 + CHECK_REGA(iR15,ThreadContextExecCall_return - 4)
1.223 + asm("mov r0,#1");
1.224 + __JUMP(,lr);
1.225 + }
1.226 +
1.227 +//
1.228 +// Simulate a software exception by invoking first the exec call which
1.229 +// triggers kernel-side handlers and on return panicking the current
1.230 +// thread.
1.231 +//
1.232 +
1.233 +__NAKED__ TInt ThreadContextSwExc(TAny*)
1.234 + {
1.235 + asm("stmdb sp!, {r4-r11,lr} ");
1.236 + asm("mov r1, #0x50000000");
1.237 + asm("bl SetRegs");
1.238 + asm("adr lr, ThreadContextSwExc_return");
1.239 + asm("ldr r0, current_thread_handle ");
1.240 + asm("mov r2, #1");
1.241 + SLOW_EXEC3(EExecIsExceptionHandled);
1.242 + asm("ThreadContextSwExc_return:");
1.243 + asm("ldr r0, current_thread_handle ");
1.244 + asm("ldr r3, null_descriptor");
1.245 + asm("mov r1, #%a0 " : : "i" ((TInt)EExitPanic));
1.246 + asm("mov r2, #0");
1.247 + SLOW_EXEC4(EExecThreadKill);
1.248 + asm("ldmia sp!, {r4-r11,pc} ");
1.249 + asm("null_descriptor:");
1.250 + asm(".word 0x00000000");
1.251 + asm(".word 0x00000000");
1.252 + }
1.253 +
1.254 +__NAKED__ TInt CheckContextSwExc(TArmRegSet*,TArmRegSet*)
1.255 + {
1.256 + CHECK_REG(iR4);
1.257 + CHECK_REG(iR5);
1.258 + CHECK_REG(iR6);
1.259 + CHECK_REG(iR7);
1.260 + CHECK_REG(iR8);
1.261 + CHECK_REG(iR9);
1.262 + CHECK_REG(iR10);
1.263 + CHECK_REG(iR11);
1.264 + CHECK_REG(iR13);
1.265 + CHECK_REGA(iR14,ThreadContextSwExc_return)
1.266 + CHECK_REGA(iR15,ThreadContextSwExc_return - 4)
1.267 + asm("mov r0,#1");
1.268 + __JUMP(,lr);
1.269 + }
1.270 +
1.271 +__NAKED__ TInt CheckContextKernel(TArmRegSet*,TArmRegSet*)
1.272 + {
1.273 + CHECK_REG(iR4);
1.274 + CHECK_REG(iR5);
1.275 + CHECK_REG(iR6);
1.276 + CHECK_REG(iR7);
1.277 + CHECK_REG(iR8);
1.278 + CHECK_REG(iR9);
1.279 + CHECK_REG(iR10);
1.280 + CHECK_REG(iR11);
1.281 + // can't test r13 because we don't know how much the irq vector pushes onto the stack
1.282 + // CHECK_REG(iR13);
1.283 + // can't really test r15 because pc is somewhere in the irq
1.284 + // vector and we don't export that address
1.285 + asm("mov r0,#1");
1.286 + __JUMP(,lr);
1.287 + }
1.288 +
1.289 +#else
1.290 +
1.291 +#include <e32def.h>
1.292 +#include <cpudefs.h>
1.293 +
1.294 +__NAKED__ TUint32 SpinInKernel(TBool)
1.295 + {
1.296 + asm("cmp r0, #0 ");
1.297 +#ifdef __SMP__
1.298 + asm("mov r0, sp ");
1.299 +#else
1.300 + asm("mov r0, sp");
1.301 +// asm("sub r0, sp, #32 "); // IRQ mode pushes 8 extra registers <--- NOT TRUE
1.302 +#endif
1.303 + asm("beq exit ");
1.304 + asm("mov r0, #0xa0000000 ");
1.305 + asm("add r1, r0, #1 ");
1.306 + asm("add r2, r1, #1 ");
1.307 + asm("add r3, r2, #1 ");
1.308 + asm("add r4, r3, #1 ");
1.309 + asm("add r5, r4, #1 ");
1.310 + asm("add r6, r5, #1 ");
1.311 + asm("add r7, r6, #1 ");
1.312 + asm("add r8, r7, #1 ");
1.313 + asm("add r9, r8, #1 ");
1.314 + asm("add r10, r9, #1 ");
1.315 + asm("add r11, r10, #1 ");
1.316 + asm("add r12, r11, #1 ");
1.317 + asm("add r14, r12, #2 ");
1.318 + asm("loopforever: ");
1.319 + asm("b loopforever ");
1.320 + asm("exit: ");
1.321 + __JUMP(,lr);
1.322 + }
1.323 +
1.324 +#endif