1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/nkernsmp/x86/vectors.cpp Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,172 @@
1.4 +// Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\nkernsmp\x86\vectors.cpp
1.18 +//
1.19 +//
1.20 +
1.21 +#include <x86.h>
1.22 +#include <apic.h>
1.23 +#include <nk_irq.h>
1.24 +#include "vectors.h"
1.25 +
1.26 +TUint32 __tr();
1.27 +void __ltr(TInt);
1.28 +
1.29 +extern "C" void _irqdebug(TUint a)
1.30 + {
1.31 + if (a>=0x30)
1.32 + return;
1.33 + __KTRACE_OPT(KSCHED2,DEBUGPRINT("!%02x",a));
1.34 + }
1.35 +
1.36 +extern "C" void IrqStartTrace(TUint32 aVector)
1.37 + {
1.38 + __ACQUIRE_BTRACE_LOCK();
1.39 + BTraceData.iHandler(BTRACE_HEADER(8,BTrace::ECpuUsage,BTrace::EIrqStart),0,0,aVector,0,0,0,0);
1.40 + __RELEASE_BTRACE_LOCK();
1.41 + }
1.42 +
1.43 +extern "C" void IrqEndTrace()
1.44 + {
1.45 + __ACQUIRE_BTRACE_LOCK();
1.46 + BTraceData.iHandler(BTRACE_HEADER(4,BTrace::ECpuUsage,BTrace::EIrqEnd),0,0,0,0,0,0,0);
1.47 + __RELEASE_BTRACE_LOCK();
1.48 + }
1.49 +
1.50 +
1.51 +/** Register the global IRQ handler
1.52 + Called by the base port at boot time to bind the top level IRQ dispatcher
1.53 + to the X86 common IRQ handler. Should not be called at any other time.
1.54 +
1.55 + The handler specified will be called with IRQs disabled. ESP will point
1.56 + to the top of the interrupt stack. On entry to the handler EAX will point
1.57 + to a block of saved registers, as follows:
1.58 +
1.59 + [EAX+00h] = saved ESI
1.60 + [EAX+04h] = saved EDI
1.61 + [EAX+08h] = saved EDX
1.62 + [EAX+0Ch] = saved ECX
1.63 + [EAX+10h] = saved EAX
1.64 + [EAX+14h] = saved ES
1.65 + [EAX+18h] = saved DS
1.66 + [EAX+1Ch] = interrupt vector number
1.67 + [EAX+20h] = return EIP
1.68 + [EAX+24h] = return CS
1.69 + [EAX+28h] = return EFLAGS
1.70 + [EAX+2Ch] = return ESP if interrupt occurred while CPL>0
1.71 + [EAX+30h] = return SS if interrupt occurred while CPL>0
1.72 +
1.73 + The handler should preserve all registers other than EAX, ECX, EDX
1.74 + and should return using a standard RET instruction.
1.75 +
1.76 + @param aHandler The address of the top level IRQ dispatcher routine
1.77 + */
1.78 +EXPORT_C void X86::SetIrqHandler(TLinAddr aHandler)
1.79 + {
1.80 + X86_IrqHandler = aHandler;
1.81 + }
1.82 +
1.83 +
1.84 +/** Return the address immediately after the end of the interrupt stack.
1.85 +
1.86 + @return Interrupt Stack Base + Interrupt Stack Size
1.87 + */
1.88 +EXPORT_C TLinAddr X86::IrqStackTop(TInt aCpu)
1.89 + {
1.90 + TLinAddr a = 0;
1.91 + if (aCpu>=0 && aCpu<KMaxCpus)
1.92 + a = TLinAddr(TheSubSchedulers[aCpu].i_IrqStackTop);
1.93 + else
1.94 + {
1.95 + TInt irq = NKern::DisableAllInterrupts();
1.96 + a = TLinAddr(SubScheduler().i_IrqStackTop);
1.97 + NKern::RestoreInterrupts(irq);
1.98 + }
1.99 + return a;
1.100 + }
1.101 +
1.102 +void SetTrapGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
1.103 + {
1.104 + aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
1.105 + aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8f00 | (aDPL<<13);
1.106 + }
1.107 +
1.108 +void SetInterruptGate(SX86Des* aEntry, PFV aHandler, TInt aDPL)
1.109 + {
1.110 + aEntry->iLow=(KRing0CS<<16)|(TUint32(aHandler)&0xffff);
1.111 + aEntry->iHigh=(TUint32(aHandler)&0xffff0000) | 0x8e00 | (aDPL<<13);
1.112 + }
1.113 +
1.114 +void SetTssDescriptor(SX86Des* aEntry, TX86Tss* aTss)
1.115 + {
1.116 + TUint addr3=TUint(aTss)>>24;
1.117 + TUint addr2=(TUint(aTss)>>16)&0xff;
1.118 + TUint addr01=TUint(aTss)&0xffff;
1.119 + aEntry->iLow=(addr01<<16)|(sizeof(TX86Tss)-1);
1.120 + aEntry->iHigh=(addr3<<24)|0x00108900|addr2;
1.121 + }
1.122 +
1.123 +void X86::Init1Interrupts()
1.124 +//
1.125 +// Initialise the interrupt and exception vector handlers.
1.126 +//
1.127 + {
1.128 +// TheIrqHandler=0; // done by placing TheIrqHandler, TheFiqHandler in .bss
1.129 + __KTRACE_OPT(KBOOT,DEBUGPRINT(">X86::Init1Interrupts()"));
1.130 +
1.131 + TCpuPages& cp=X86::CpuPage();
1.132 + memclr(cp.iIdt, KIdtSize*sizeof(SX86Des));
1.133 + TInt i;
1.134 + for (i=0; i<(TInt)(sizeof(TheExcVectors)/sizeof(PFV)); i++)
1.135 + {
1.136 + if (i==0x03 || i==0x20 || i==0x21)
1.137 + SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 3);
1.138 + else if (i<0x20 && i!=0x02)
1.139 + SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 0);
1.140 + if (i==0x02 || i>=0x27)
1.141 + SetInterruptGate(cp.iIdt+i, TheExcVectors[i], 0);
1.142 + }
1.143 + for (i=0; i<KMaxCpus; ++i)
1.144 + {
1.145 + SCpuData& cd = cp.iCpuData[i];
1.146 + memclr(&cd, sizeof(cd) - sizeof(cd.iIrqStack));
1.147 + memset(cd.iIrqStack, 0xab+i*2, sizeof(cd.iIrqStack));
1.148 +
1.149 + TUint32 esp = (TUint32)cd.iIrqStack + sizeof(cd.iIrqStack);
1.150 + cd.iTss.iCR3 = get_cr3();
1.151 + cd.iTss.iSs0 = KRing0DS;
1.152 + cd.iTss.iEsp0 = esp;
1.153 + SetTssDescriptor(&cp.iGdt[5+i], &cd.iTss);
1.154 +
1.155 + TSubScheduler& ss = TheSubSchedulers[i];
1.156 + ss.i_IrqNestCount = (TAny*)(-1);
1.157 + ss.i_IrqStackTop = (TAny*)esp;
1.158 + ss.i_Tss = &cd.iTss;
1.159 + }
1.160 +
1.161 + X86::DefaultCR0 = get_cr0();
1.162 + NIrq::HwInit1();
1.163 +
1.164 + __ltr(TSS_SELECTOR(0));
1.165 + __lidt(cp.iIdt, KIdtSize);
1.166 + __KTRACE_OPT(KBOOT,DEBUGPRINT("<X86::Init1Interrupts()"));
1.167 + }
1.168 +
1.169 +
1.170 +extern "C" void ExcFault(TAny*);
1.171 +void __X86ExcFault(TAny* aInfo)
1.172 + {
1.173 + ExcFault(aInfo);
1.174 + }
1.175 +