1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/nkernsmp/arm/ncutils.cia Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,1042 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\nkernsmp\arm\ncutils.cia
1.18 +//
1.19 +//
1.20 +
1.21 +#include <e32cia.h>
1.22 +#include <arm.h>
1.23 +#include <arm_gic.h>
1.24 +
1.25 +extern TSpinLock BTraceLock;
1.26 +
1.27 +extern "C" {
1.28 +extern TUint32 CrashStateOut;
1.29 +extern SFullArmRegSet DefaultRegSet;
1.30 +}
1.31 +
1.32 +//#define __DBG_MON_FAULT__
1.33 +//#define __RAM_LOADED_CODE__
1.34 +//#define __EARLY_DEBUG__
1.35 +
1.36 +#ifdef _DEBUG
1.37 +#define ASM_KILL_LINK(rp,rs) asm("mov "#rs", #0xdf ");\
1.38 + asm("orr "#rs", "#rs", "#rs", lsl #8 ");\
1.39 + asm("orr "#rs", "#rs", "#rs", lsl #16 ");\
1.40 + asm("str "#rs", ["#rp"] ");\
1.41 + asm("str "#rs", ["#rp", #4] ");
1.42 +#else
1.43 +#define ASM_KILL_LINK(rp,rs)
1.44 +#endif
1.45 +
1.46 +#ifdef __PRI_LIST_MACHINE_CODED__
1.47 +/** Return the priority of the highest priority item present on a priority list.
1.48 +
1.49 + @return The highest priority present or -1 if the list is empty.
1.50 + */
1.51 +EXPORT_C __NAKED__ TInt TPriListBase::HighestPriority()
1.52 + {
1.53 + asm("ldr r2, [r0, #4] "); // r2=iPresent MSW
1.54 + asm("ldr r1, [r0, #0] "); // r1=iPresent LSW
1.55 + CLZ(0,2); // r0=31-MSB(r2)
1.56 + asm("subs r0, r0, #32 "); // r0=-1-MSB(r2), 0 if r2=0
1.57 + CLZcc(CC_EQ,0,1); // if r2=0, r0=31-MSB(r1)
1.58 + asm("rsb r0, r0, #31 "); // r0=highest priority
1.59 + __JUMP(,lr);
1.60 + }
1.61 +
1.62 +/** Find the highest priority item present on a priority list.
1.63 + If multiple items at the same priority are present, return the first to be
1.64 + added in chronological order.
1.65 +
1.66 + @return a pointer to the item or NULL if the list is empty.
1.67 + */
1.68 +EXPORT_C __NAKED__ TPriListLink* TPriListBase::First()
1.69 + {
1.70 + asm("ldr r2, [r0, #4] "); // r2=iPresent MSW
1.71 + asm("ldr r1, [r0], #8 "); // r1=iPresent LSW, r0=&iQueue[0]
1.72 + CLZ(3,2); // r3=31-MSB(r2)
1.73 + asm("subs r3, r3, #32 "); // r3=-1-MSB(r2), 0 if r2=0
1.74 + CLZcc(CC_EQ,3,1); // if r2=0, r3=31-MSB(r1)
1.75 + asm("rsbs r3, r3, #31 "); // r3=highest priority
1.76 + asm("ldrpl r0, [r0, r3, lsl #2] "); // if r3>=0 list is nonempty, r0->first entry
1.77 + asm("movmi r0, #0 "); // if r3<0 list empty, return NULL
1.78 + __JUMP(,lr);
1.79 + }
1.80 +
1.81 +/** Add an item to a priority list.
1.82 +
1.83 + @param aLink = a pointer to the item - must not be NULL
1.84 + */
1.85 +EXPORT_C __NAKED__ void TPriListBase::Add(TPriListLink* /*aLink*/)
1.86 + {
1.87 + asm("ldrb r2, [r1, #8]" ); // r2=priority of aLink
1.88 + asm("add ip, r0, #8 "); // ip=&iQueue[0]
1.89 + asm("ldr r3, [ip, r2, lsl #2]! "); // r3->first entry at this priority
1.90 + asm("cmp r3, #0 "); // is this first entry at this priority?
1.91 + asm("bne pri_list_add_1 "); // branch if not
1.92 + asm("str r1, [ip] "); // if queue originally empty, iQueue[pri]=aThread
1.93 + asm("ldrb ip, [r0, r2, lsr #3]! "); // ip=relevant byte of present mask, r0->same
1.94 + asm("and r2, r2, #7 ");
1.95 + asm("mov r3, #1 ");
1.96 + asm("str r1, [r1, #0] "); // aThread->next=aThread
1.97 + asm("orr ip, ip, r3, lsl r2 "); // ip |= 1<<(pri&7)
1.98 + asm("str r1, [r1, #4] "); // aThread->iPrev=aThread
1.99 + asm("strb ip, [r0] "); // update relevant byte of present mask
1.100 + __JUMP(,lr);
1.101 + asm("pri_list_add_1: ");
1.102 + asm("ldr ip, [r3, #4] "); // if nonempty, ip=last
1.103 + asm("str r1, [r3, #4] "); // first->prev=aThread
1.104 + asm("stmia r1, {r3,ip} "); // aThread->next=r3=first, aThread->prev=ip=last
1.105 + asm("str r1, [ip, #0] "); // last->next=aThread
1.106 + __JUMP(,lr);
1.107 + }
1.108 +
1.109 +
1.110 +/** Removes an item from a priority list.
1.111 +
1.112 + @param aLink A pointer to the item - this must not be NULL.
1.113 + */
1.114 +EXPORT_C __NAKED__ void TPriListBase::Remove(TPriListLink* /*aLink*/)
1.115 + {
1.116 + asm("ldmia r1, {r2,r3} "); // r2=aLink->iNext, r3=aLink->iPrev
1.117 + ASM_KILL_LINK(r1,r12);
1.118 + asm("subs r12, r1, r2 "); // check if more threads at this priority, r12=0 if not
1.119 + asm("bne 1f "); // branch if there are more at same priority
1.120 + asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(NThread, iPriority)); // r2=thread priority
1.121 + asm("add r1, r0, #%a0" : : "i" _FOFF(TPriListBase, iQueue)); // r1->iQueue[0]
1.122 + asm("str r12, [r1, r2, lsl #2] "); // iQueue[priority]=NULL
1.123 + asm("ldrb r1, [r0, r2, lsr #3] "); // r1=relevant byte in present mask
1.124 + asm("and r3, r2, #7 "); // r3=priority & 7
1.125 + asm("mov r12, #1 ");
1.126 + asm("bic r1, r1, r12, lsl r3 "); // clear bit in present mask
1.127 + asm("strb r1, [r0, r2, lsr #3] "); // update relevant byte in present mask
1.128 + __JUMP(,lr);
1.129 + asm("1: "); // get here if there are other threads at same priority
1.130 + asm("ldrb r12, [r1, #%a0]" : : "i" _FOFF(NThread, iPriority)); // r12=thread priority
1.131 + asm("add r0, r0, #%a0" : : "i" _FOFF(TPriListBase, iQueue)); // r0=&iQueue[0]
1.132 + asm("str r3, [r2, #4] "); // next->prev=prev
1.133 + asm("ldr r12, [r0, r12, lsl #2]! "); // r12=iQueue[priority], r0=&iQueue[priority]
1.134 + asm("str r2, [r3, #0] "); // and prev->next=next
1.135 + asm("cmp r12, r1 "); // if aThread was first...
1.136 + asm("streq r2, [r0, #0] "); // iQueue[priority]=aThread->next
1.137 + __JUMP(,lr); // finished
1.138 + }
1.139 +
1.140 +
1.141 +/** Change the priority of an item on a priority list
1.142 +
1.143 + @param aLink = pointer to the item to act on - must not be NULL
1.144 + @param aNewPriority = new priority for the item
1.145 + */
1.146 +EXPORT_C __NAKED__ void TPriListBase::ChangePriority(TPriListLink* /*aLink*/, TInt /*aNewPriority*/)
1.147 + {
1.148 + asm("ldrb r3, [r1, #8] "); // r3=old priority
1.149 + asm("stmfd sp!, {r4-r6,lr} ");
1.150 + asm("cmp r3, r2 ");
1.151 + asm("ldmeqfd sp!, {r4-r6,pc} "); // if old priority=new, finished
1.152 + asm("ldmia r1, {r4,r12} "); // r4=next, r12=prev
1.153 + asm("ldmia r0!, {r6,lr} "); // lr:r6=present mask, r0=&iQueue[0]
1.154 + asm("subs r5, r4, r1 "); // check if aLink is only one at that priority, r5=0 if it is
1.155 + asm("beq change_pri_1 "); // branch if it is
1.156 + asm("ldr r5, [r0, r3, lsl #2] "); // r5=iQueue[old priority]
1.157 + asm("str r4, [r12, #0] "); // prev->next=next
1.158 + asm("str r12, [r4, #4] "); // next->prev=prev
1.159 + asm("cmp r5, r1 "); // was aLink first?
1.160 + asm("streq r4, [r0, r3, lsl #2] "); // if it was, iQueue[old priority]=aLink->next
1.161 + asm("b change_pri_2 ");
1.162 + asm("change_pri_1: ");
1.163 + asm("str r5, [r0, r3, lsl #2] "); // if empty, set iQueue[old priority]=NULL
1.164 + asm("mov r12, #0x80000000 ");
1.165 + asm("rsbs r3, r3, #31 "); // r3=31-priority
1.166 + asm("bicmi lr, lr, r12, ror r3 "); // if pri>31, clear bit is MS word
1.167 + asm("bicpl r6, r6, r12, ror r3 "); // if pri<=31, clear bit in LS word
1.168 + asm("change_pri_2: ");
1.169 + asm("ldr r4, [r0, r2, lsl #2] "); // r4=iQueue[new priority]
1.170 + asm("strb r2, [r1, #8] "); // store new priority
1.171 + asm("cmp r4, #0 "); // new priority queue empty?
1.172 + asm("bne change_pri_3 "); // branch if not
1.173 + asm("str r1, [r0, r2, lsl #2] "); // if new priority queue was empty, iQueue[new p]=aLink
1.174 + asm("mov r12, #0x80000000 ");
1.175 + asm("str r1, [r1, #0] "); // aLink->next=aLink
1.176 + asm("rsbs r2, r2, #31 "); // r2=31-priority
1.177 + asm("str r1, [r1, #4] "); // aLink->prev=aLink
1.178 + asm("orrmi lr, lr, r12, ror r2 "); // if pri>31, set bit is MS word
1.179 + asm("orrpl r6, r6, r12, ror r2 "); // if pri<=31, set bit in LS word
1.180 + asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0
1.181 + asm("ldmfd sp!, {r4-r6,pc} ");
1.182 + asm("change_pri_3: ");
1.183 + asm("ldr r12, [r4, #4] "); // r12->last link at this priority
1.184 + asm("str r1, [r4, #4] "); // first->prev=aLink
1.185 + asm("str r1, [r12, #0] "); // old last->next=aLink
1.186 + asm("stmia r1, {r4,r12} "); // aLink->next=r3=first, aLink->prev=r12=old last
1.187 + asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0
1.188 + asm("ldmfd sp!, {r4-r6,pc} ");
1.189 + }
1.190 +#endif
1.191 +
1.192 +__NAKED__ void initialiseState(TInt /*aCpu*/, TSubScheduler* /*aSS*/)
1.193 + {
1.194 + SET_RWNO_TID(,r1);
1.195 + __ASM_CLI_MODE(MODE_ABT);
1.196 + asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_AbtStackTop));
1.197 + asm("mvn r3, #0 ");
1.198 + asm("str r3, [sp, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.199 + asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_IrqNestCount));
1.200 + __ASM_CLI_MODE(MODE_UND);
1.201 + asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_UndStackTop));
1.202 + __ASM_CLI_MODE(MODE_FIQ);
1.203 + asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_FiqStackTop));
1.204 + __ASM_CLI_MODE(MODE_IRQ);
1.205 + asm("str sp, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_IrqStackTop));
1.206 + __ASM_CLI_MODE(MODE_SVC);
1.207 + asm("ldr r2, __TheScheduler ");
1.208 + asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_ScuAddr));
1.209 + asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_ScuAddr));
1.210 + asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_GicDistAddr));
1.211 + asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicDistAddr));
1.212 + asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_GicCpuIfcAddr));
1.213 + asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr));
1.214 + asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, i_LocalTimerAddr));
1.215 + asm("str r3, [r1, #%a0]" : : "i" _FOFF(TSubScheduler, i_LocalTimerAddr));
1.216 + asm("mov r3, #0 ");
1.217 + SET_RWRO_TID(,r3);
1.218 + SET_RWRW_TID(,r3);
1.219 +
1.220 + __JUMP(,lr);
1.221 +
1.222 + asm("__TheScheduler: ");
1.223 + asm(".word TheScheduler ");
1.224 + }
1.225 +
1.226 +__NAKED__ TUint32 __mpid()
1.227 + {
1.228 + asm("mrc p15, 0, r0, c0, c0, 5 ");
1.229 + __JUMP(,lr);
1.230 + }
1.231 +
1.232 +/** @internalTechnology
1.233 +
1.234 + Called to indicate that the system has crashed and all CPUs should be
1.235 + halted and should dump their registers.
1.236 +
1.237 +*/
1.238 +__NAKED__ void NKern::NotifyCrash(const TAny* /*a0*/, TInt /*a1*/)
1.239 + {
1.240 + asm("stmfd sp!, {r0-r1} "); // save parameters
1.241 + GET_RWNO_TID(,r0);
1.242 + asm("cmp r0, #0 ");
1.243 + asm("ldreq r0, __SS0 ");
1.244 + asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TSubScheduler,i_Regs));
1.245 + asm("cmp r0, #0 ");
1.246 + asm("ldreq r0, __DefaultRegs ");
1.247 + asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.248 + asm("cmp r1, #0 "); // context already saved?
1.249 + asm("bge state_already_saved "); // skip if so
1.250 + asm("mov r1, lr ");
1.251 + asm("bl " CSM_ZN3Arm9SaveStateER14SFullArmRegSet );
1.252 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iN.iR15));
1.253 + asm("ldmia sp!, {r2-r3} "); // original R0,R1
1.254 + asm("stmia r0, {r2-r3} "); // save original R0,R1
1.255 + asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.256 + asm("mov r4, r0 "); // save pointer to i_Regs
1.257 + asm("stmib r1, {r2-r3} "); // save a0, a1 in iCrashArgs
1.258 + asm("mov r1, #13 "); // r1 = regnum
1.259 + asm("mrs r2, cpsr "); // r2 = mode
1.260 + asm("bl " CSM_ZN3Arm3RegER14SFullArmRegSetim ); // r0 = pointer to exception mode R13
1.261 + asm("str sp, [r0] "); // save correct original value for exception mode R13
1.262 + asm("b state_save_complete ");
1.263 +
1.264 + asm("state_already_saved: ");
1.265 + asm("ldmia sp!, {r2-r3} "); // original R0,R1
1.266 + asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.267 + asm("ldr r4, [r1, #4]! ");
1.268 + asm("cmp r4, #0 ");
1.269 + asm("stmeqia r1, {r2-r3} "); // save a0, a1 in iCrashArgs, provided iCrashArgs not already set
1.270 + asm("mov r4, r0 "); // save pointer to i_Regs
1.271 + asm("state_save_complete: ");
1.272 +
1.273 + __ASM_CLI_MODE(MODE_FIQ); // mode_fiq, interrupts off
1.274 + GET_RWNO_TID(,r0);
1.275 + asm("ldr r1, __CrashState ");
1.276 + asm("cmp r0, #0 ");
1.277 + asm("moveq r2, #1 ");
1.278 + asm("streq r2, [r1] ");
1.279 + asm("beq skip_other_cores "); // If subscheduler not yet set, don't bother with other cores
1.280 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iCpuMask));
1.281 + asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr));
1.282 +// asm("ldr r4, [r0, #%a0]" : : "i" _FOFF(TSubScheduler,i_Regs));
1.283 + asm("bic sp, sp, #4 "); // align stack to multiple of 8
1.284 +
1.285 + __DATA_MEMORY_BARRIER_Z__(r6);
1.286 + asm("1: ");
1.287 + LDREX(3,1);
1.288 + asm("orr r5, r3, r2 ");
1.289 + STREX(12,5,1); // set bit in CrashState for this CPU
1.290 + asm("cmp r12, #0 ");
1.291 + asm("bne 1b ");
1.292 + __DATA_MEMORY_BARRIER__(r6);
1.293 + asm("cmp r3, #0 "); // were we first to crash?
1.294 + asm("beq first_to_crash "); // branch if so
1.295 +
1.296 + // we weren't first to crash, so wait here for a crash IPI
1.297 + // disable all interrupts except for CRASH_IPI
1.298 + GET_RWNO_TID(,r0);
1.299 + asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicCpuIfcAddr));
1.300 + asm("mov r1, #0 ");
1.301 + asm("1: ");
1.302 + asm("add r1, r1, #1 ");
1.303 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(GicCpuIfc, iPriMask));
1.304 + __DATA_SYNC_BARRIER__(r6);
1.305 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(GicCpuIfc, iPriMask));
1.306 + asm("cmp r2, #0 ");
1.307 + asm("beq 1b "); // loop until priority mask is nonzero
1.308 +
1.309 + asm("2: ");
1.310 + __ASM_STI_MODE(MODE_ABT);
1.311 + ARM_WFE;
1.312 + asm("b 2b "); // loop until we get a CRASH_IPI
1.313 +
1.314 + // This CPU was first to crash
1.315 + asm("first_to_crash: ");
1.316 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iScheduler));
1.317 + asm("ldr r7, __CrashStateOut ");
1.318 + asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(TScheduler, iActiveCpus1));
1.319 + asm("str r3, [r7] "); // mask of CPUs pending
1.320 + asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, i_GicDistAddr));
1.321 + asm("ldr r1, __CrashIPIWord ");
1.322 + __DATA_SYNC_BARRIER_Z__(r6);
1.323 + asm("str r1, [r5, #%a0]" : : "i" _FOFF(GicDistributor, iSoftIrq)); // send CRASH_IPI to all other CPUs
1.324 + __DATA_SYNC_BARRIER__(r6);
1.325 +
1.326 + asm("skip_other_cores: ");
1.327 + asm("mov r0, #0 ");
1.328 + asm("mov r1, #0 ");
1.329 + asm("mov r2, #0 ");
1.330 + asm("bl NKCrashHandler "); // call NKCrashHandler(0,0,0)
1.331 +
1.332 + __DATA_SYNC_BARRIER__(r6);
1.333 + GET_RWNO_TID(,r0);
1.334 + asm("cmp r0, #0 ");
1.335 + asm("beq skip_other_cores2 "); // If subscheduler not yet set, don't bother with other cores
1.336 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(TSubScheduler, iCpuMask));
1.337 + asm("7: ");
1.338 + LDREX(1,7);
1.339 + asm("bic r1, r1, r2 ");
1.340 + STREX(3,1,7); // atomic { CrashStateOut &= ~iCpuMask; }
1.341 + asm("cmp r3, #0 ");
1.342 + asm("bne 7b ");
1.343 + asm("1: ");
1.344 + asm("ldr r1, [r7] ");
1.345 + asm("cmp r1, #0 "); // wait for all CPUs to acknowledge
1.346 + asm("beq 2f ");
1.347 + asm("adds r6, r6, #1 ");
1.348 + asm("bne 1b "); // if not ACKed after 2^32 iterations give up waiting
1.349 + asm("2: ");
1.350 + __DATA_MEMORY_BARRIER_Z__(r0);
1.351 +
1.352 + asm("skip_other_cores2: ");
1.353 + asm("mov r0, #1 ");
1.354 + asm("ldr r1, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR0)); // original R0 = a0 parameter
1.355 + asm("ldr r2, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR1)); // original R1 = a1 parameter
1.356 + asm("bl NKCrashHandler "); // call NKCrashHandler(1,a0,a1) - shouldn't return
1.357 +
1.358 + // shouldn't get back here
1.359 + __ASM_CRASH();
1.360 +
1.361 + asm("__CrashState: ");
1.362 + asm(".word %a0" : : "i" ((TInt)&CrashState));
1.363 + asm("__CrashStateOut: ");
1.364 + asm(".word CrashStateOut ");
1.365 + asm("__CrashIPIWord: ");
1.366 + asm(".word %a0" : : "i" ( (TInt)GIC_IPI_OTHERS(CRASH_IPI_VECTOR) ));
1.367 + asm("__SS0: ");
1.368 + asm(".word %a0" : : "i" ((TInt)&TheSubSchedulers[0]));
1.369 + asm("__DefaultRegs: ");
1.370 + asm(".word %a0" : : "i" ((TInt)&DefaultRegSet));
1.371 + }
1.372 +
1.373 +
1.374 +#ifdef __USE_BTRACE_LOCK__
1.375 +#define __ASM_ACQUIRE_BTRACE_LOCK(regs) \
1.376 + asm("stmfd sp!, " regs); \
1.377 + asm("ldr r0, __BTraceLock "); \
1.378 + asm("bl " CSM_ZN9TSpinLock11LockIrqSaveEv ); \
1.379 + asm("mov r4, r0 "); \
1.380 + asm("ldmfd sp!, " regs)
1.381 +
1.382 +#define __ASM_RELEASE_BTRACE_LOCK() \
1.383 + asm("stmfd sp!, {r0-r1} "); \
1.384 + asm("ldr r0, __BTraceLock "); \
1.385 + asm("mov r1, r4 "); \
1.386 + asm("bl " CSM_ZN9TSpinLock16UnlockIrqRestoreEi ); \
1.387 + asm("ldmfd sp!, {r0-r1} ")
1.388 +
1.389 +#else
1.390 +#define __ASM_ACQUIRE_BTRACE_LOCK(regs)
1.391 +#define __ASM_RELEASE_BTRACE_LOCK()
1.392 +#endif
1.393 +
1.394 +
1.395 +__NAKED__ EXPORT_C TBool BTrace::Out(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.396 + {
1.397 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.398 + __ASM_ACQUIRE_BTRACE_LOCK("{r0-r1}");
1.399 + asm("ldr r12, __BTraceData");
1.400 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.401 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.402 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.403 + asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.404 + asm("adr lr, 9f");
1.405 + asm("cmp r2, #0");
1.406 + asm("moveq r0, #0");
1.407 + __JUMP(ne, r12);
1.408 + asm("9: ");
1.409 + __ASM_RELEASE_BTRACE_LOCK();
1.410 + __POPRET("r2,r3,r4,");
1.411 + }
1.412 +
1.413 +__NAKED__ EXPORT_C TBool BTrace::OutN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.414 + {
1.415 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.416 + __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3}");
1.417 + asm("ldr r12, __BTraceData");
1.418 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.419 + asm("ldr r14, [sp, #16]"); // r14 = aDataSize
1.420 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.421 + asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.422 + asm("cmp r2, #0");
1.423 + asm("moveq r0, #0");
1.424 + asm("beq 0f ");
1.425 +
1.426 + asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.427 + asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.428 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.429 + asm("add r0, r0, r14");
1.430 + asm("subs r14, r14, #1");
1.431 + asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0
1.432 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.433 + asm("cmp r14, #4");
1.434 + asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4
1.435 +
1.436 + asm("mov lr, pc");
1.437 + __JUMP(, r12);
1.438 + asm("0: ");
1.439 + __ASM_RELEASE_BTRACE_LOCK();
1.440 + __POPRET("r2,r3,r4,");
1.441 + }
1.442 +
1.443 +__NAKED__ EXPORT_C TBool BTrace::OutX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.444 + {
1.445 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.446 + __ASM_ACQUIRE_BTRACE_LOCK("{r0-r1}");
1.447 + asm("ldr r12, __BTraceData");
1.448 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.449 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.450 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.451 + asm("mrs r14, cpsr ");
1.452 + asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.453 + asm("cmp r2, #0"); // check category filter
1.454 + asm("moveq r0, #0");
1.455 + asm("beq 0f "); // if category disabled, exit now
1.456 + __ASM_CLI();
1.457 + asm("and r2, r14, #0x0f ");
1.458 + asm("cmp r2, #3 ");
1.459 + asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.460 + asm("bne 1f ");
1.461 + GET_RWNO_TID(,r1);
1.462 + asm("movs r2, r1 "); // r2 = context ID = 0 for early boot, no threads
1.463 + asm("beq 1f ");
1.464 + asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC));
1.465 + asm("cmp r2, #0 ");
1.466 + asm("ldreq r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
1.467 + asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread
1.468 + asm("1: ");
1.469 + asm("msr cpsr, r14 ");
1.470 + asm("mov lr, pc");
1.471 + __JUMP(, r12);
1.472 + asm("0: ");
1.473 + __ASM_RELEASE_BTRACE_LOCK();
1.474 + __POPRET("r2,r3,r4,");
1.475 + }
1.476 +
1.477 +__NAKED__ EXPORT_C TBool BTrace::OutNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.478 + {
1.479 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.480 + __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3}");
1.481 + asm("ldr r12, __BTraceData");
1.482 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.483 + asm("ldr r14, [sp, #16]"); // r14 = aDataSize
1.484 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.485 + asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.486 + asm("cmp r2, #0"); // check category filter
1.487 + asm("moveq r0, #0");
1.488 + asm("beq 0f "); // if category disabled, exit now
1.489 +
1.490 + asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.491 + asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.492 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.493 + asm("add r0, r0, r14");
1.494 + asm("subs r14, r14, #1");
1.495 + asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0
1.496 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.497 + asm("cmp r14, #4");
1.498 + asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4
1.499 +
1.500 + asm("mrs r14, cpsr ");
1.501 + __ASM_CLI();
1.502 + asm("and r2, r14, #0x0f ");
1.503 + asm("cmp r2, #3 ");
1.504 + asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.505 + asm("bne 1f ");
1.506 + GET_RWNO_TID(,r1);
1.507 + asm("movs r2, r1 "); // r2 = context ID = 0 for early boot, no threads
1.508 + asm("beq 1f ");
1.509 + asm("ldrb r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC));
1.510 + asm("cmp r2, #0 ");
1.511 + asm("ldreq r2, [r1, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
1.512 + asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread
1.513 + asm("1: ");
1.514 + asm("msr cpsr, r14 ");
1.515 +
1.516 + asm("mov lr, pc");
1.517 + __JUMP(, r12);
1.518 + asm("0: ");
1.519 + __ASM_RELEASE_BTRACE_LOCK();
1.520 + __POPRET("r2,r3,r4,");
1.521 + }
1.522 +
1.523 +__NAKED__ EXPORT_C TBool BTrace::OutBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
1.524 + {
1.525 + asm("stmdb sp!, {r4,lr}");
1.526 + asm("ldr r12, __BTraceData");
1.527 + asm("str lr, [sp, #-4]! "); // PC
1.528 + asm("and r14, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.529 + asm("ldrb r14, [r12, r14, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.530 + asm("cmp r14, #0"); // check category filter
1.531 + asm("addeq sp, sp, #4 ");
1.532 + asm("moveq r0, #0 ");
1.533 + asm("beq 0f "); // if category disabled, exit now
1.534 +
1.535 + asm("mrs r14, cpsr ");
1.536 + __ASM_CLI();
1.537 + asm("and r12, r14, #0x0f ");
1.538 + asm("cmp r12, #3 ");
1.539 + asm("movhi r12, #2 "); // r12 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.540 + asm("bne 1f ");
1.541 + GET_RWNO_TID(,r12);
1.542 + asm("cmp r12, #0 "); // r2 = context ID = 0 for early boot, no threads
1.543 + asm("beq 1f ");
1.544 + asm("ldrb r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC));
1.545 + asm("cmp r12, #0 ");
1.546 + GET_RWNO_TID(eq,r12);
1.547 + asm("ldreq r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
1.548 + asm("movne r12, #3 "); // r12 = context ID = 3 for IDFC = NThread pointer for thread
1.549 + asm("1: ");
1.550 + asm("msr cpsr, r14 ");
1.551 + asm("str r12, [sp, #-4]! "); // context ID
1.552 + asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
1.553 + asm("add sp, sp, #8");
1.554 + asm("0: ");
1.555 + __POPRET("r4,");
1.556 +
1.557 + asm("__BTraceLock: ");
1.558 + asm(".word %a0" : : "i" ((TInt)&BTraceLock));
1.559 + asm("__BTraceData: ");
1.560 + asm(".word BTraceData ");
1.561 + }
1.562 +
1.563 +
1.564 +__NAKED__ EXPORT_C TBool BTrace::OutFiltered(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.565 + {
1.566 + // fall through to OutFilteredX...
1.567 + }
1.568 +
1.569 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.570 + {
1.571 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.572 + asm("ldr r12, __BTraceData");
1.573 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.574 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.575 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.576 + asm("cmp r2, #0");
1.577 + asm("moveq r0, #0");
1.578 + asm("beq 9f ");
1.579 +
1.580 + // r0=header, r1=a1=secondary filter UID, r2=unused, r3=a1, r12->SBTraceData
1.581 + // if trace enabled return r0,r1,r3 unmodified, r2=context value r12->handler, Z=0
1.582 + // if trace disabled return r0=0 Z=1
1.583 + asm("bl btrace_check_filter2 ");
1.584 + asm("beq 9f ");
1.585 + __ASM_ACQUIRE_BTRACE_LOCK("{r0,r2,r3,r12}");
1.586 + asm("adr lr, 1f ");
1.587 + __JUMP(, r12);
1.588 + asm("1: ");
1.589 + __ASM_RELEASE_BTRACE_LOCK();
1.590 + asm("9: ");
1.591 + __POPRET("r2,r3,r4,");
1.592 +
1.593 + asm("btrace_check_filter2: ");
1.594 + asm("stmfd sp!, {r0,r1,r3,r4,r12,lr} ");
1.595 + asm("mov r0, r12 ");
1.596 + asm("bl CheckFilter2__11SBTraceDataUl ");
1.597 + asm("cmp r0, #0 ");
1.598 + asm("beq 0f ");
1.599 + asm("mrs r14, cpsr ");
1.600 + __ASM_CLI();
1.601 + asm("and r2, r14, #0x0f ");
1.602 + asm("cmp r2, #3 ");
1.603 + asm("movhi r2, #2 "); // r2 = context ID = 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.604 + asm("bne 1f ");
1.605 + GET_RWNO_TID(,r4);
1.606 + asm("movs r2, r4 "); // r2 = context ID = 0 for early boot, no threads
1.607 + asm("beq 1f ");
1.608 + asm("ldrb r2, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iInIDFC));
1.609 + asm("cmp r2, #0 ");
1.610 + asm("ldreq r2, [r4, #%a0]" : : "i" _FOFF(TSubScheduler,iCurrentThread));
1.611 + asm("movne r2, #3 "); // r2 = context ID = 3 for IDFC = NThread pointer for thread
1.612 + asm("1: ");
1.613 + asm("msr cpsr, r14 ");
1.614 + asm("0: ");
1.615 + asm("ldmfd sp!, {r0,r1,r3,r4,r12,lr} ");
1.616 + asm("moveq r0, #0 ");
1.617 + asm("ldrne r12, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.618 + __JUMP(,lr);
1.619 + }
1.620 +
1.621 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.622 + {
1.623 + // fall through to OutFilteredNX...
1.624 + }
1.625 +
1.626 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.627 + {
1.628 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.629 + asm("ldr r12, __BTraceData");
1.630 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.631 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.632 + asm("cmp r2, #0");
1.633 + asm("moveq r0, #0");
1.634 + asm("beq 9f ");
1.635 +
1.636 + // r0=header, r1=a1=secondary filter UID, r2=unused, r3=aData, r12->SBTraceData
1.637 + // if trace enabled return r0,r1,r3 unmodified, r2=context value r12->handler, Z=0
1.638 + // if trace disabled return r0=0 Z=1
1.639 + asm("bl btrace_check_filter2 ");
1.640 + asm("beq 9f ");
1.641 +
1.642 + __ASM_ACQUIRE_BTRACE_LOCK("{r0-r3,r11,r12}");
1.643 + asm("ldr r14, [sp, #16] "); // r14 = aDataSize
1.644 + asm("cmp r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.645 + asm("movhi r14, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.646 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.647 + asm("add r0, r0, r14 ");
1.648 + asm("subs r14, r14, #1 ");
1.649 + asm("ldrhs r3, [r3] "); // get first word of aData if aDataSize!=0
1.650 + asm("cmp r14, #4 ");
1.651 + asm("strlo r3, [sp, #4] "); // replace aData with first word if aDataSize is 1-4
1.652 + asm("mov r3, r1 "); // r3 = a1 (ready for call to handler)
1.653 + asm("adr lr, 1f ");
1.654 + __JUMP(, r12);
1.655 + asm("1: ");
1.656 + __ASM_RELEASE_BTRACE_LOCK();
1.657 + asm("9: ");
1.658 + __POPRET("r2,r3,r4,");
1.659 + }
1.660 +
1.661 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
1.662 + {
1.663 + asm("stmdb sp!, {r4,lr} ");
1.664 + asm("ldr r12, __BTraceData ");
1.665 + asm("stmfd sp!, {r2,lr} "); // save aData, PC
1.666 + asm("and r14, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.667 + asm("ldrb r14, [r12, r14, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.668 + asm("cmp r14, #0 "); // check category filter
1.669 + asm("blne btrace_check_filter2 "); // if enabled, check secondary filter
1.670 + asm("addeq sp, sp, #8 ");
1.671 + asm("moveq r0, #0 ");
1.672 + asm("beq 9f "); // if category or secondary filter disabled, exit now
1.673 + asm("mov r12, r2 ");
1.674 + asm("ldr r2, [sp, #0] "); // restore aData into r2
1.675 + asm("str r12, [sp, #0] "); // Context ID
1.676 + asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
1.677 + asm("add sp, sp, #8 ");
1.678 + asm("9: ");
1.679 + __POPRET("r4,");
1.680 + }
1.681 +
1.682 +
1.683 +/******************************************************************************/
1.684 +
1.685 +/** Save all the ARM registers
1.686 +
1.687 +@internalTechnology
1.688 +*/
1.689 +__NAKED__ void Arm::SaveState(SFullArmRegSet&)
1.690 + {
1.691 + asm("stmia r0, {r0-r14}^ "); // save R0-R7, R8_usr-R14_usr
1.692 + asm("str lr, [r0, #60]! "); // save R15
1.693 + asm("mrs r1, cpsr ");
1.694 + asm("str r1, [r0, #4]! "); // save CPSR
1.695 + asm("bic r2, r1, #0x1f ");
1.696 + asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off
1.697 + asm("msr cpsr, r2 ");
1.698 + asm("stmib r0!, {r13,r14} "); // save R13_svc, R14_svc
1.699 + asm("mrs r3, spsr ");
1.700 + asm("str r3, [r0, #4]! "); // save SPSR_svc
1.701 + asm("bic r2, r1, #0x1f ");
1.702 + asm("orr r2, r2, #0xd7 "); // mode_abt, all interrupts off
1.703 + asm("msr cpsr, r2 ");
1.704 + asm("stmib r0!, {r13,r14} "); // save R13_abt, R14_abt
1.705 + asm("mrs r3, spsr ");
1.706 + asm("str r3, [r0, #4]! "); // save SPSR_abt
1.707 + asm("bic r2, r1, #0x1f ");
1.708 + asm("orr r2, r2, #0xdb "); // mode_und, all interrupts off
1.709 + asm("msr cpsr, r2 ");
1.710 + asm("stmib r0!, {r13,r14} "); // save R13_und, R14_und
1.711 + asm("mrs r3, spsr ");
1.712 + asm("str r3, [r0, #4]! "); // save SPSR_und
1.713 + asm("bic r2, r1, #0x1f ");
1.714 + asm("orr r2, r2, #0xd2 "); // mode_irq, all interrupts off
1.715 + asm("msr cpsr, r2 ");
1.716 + asm("stmib r0!, {r13,r14} "); // save R13_irq, R14_irq
1.717 + asm("mrs r3, spsr ");
1.718 + asm("str r3, [r0, #4]! "); // save SPSR_irq
1.719 + asm("bic r2, r1, #0x1f ");
1.720 + asm("orr r2, r2, #0xd1 "); // mode_fiq, all interrupts off
1.721 + asm("msr cpsr, r2 ");
1.722 + asm("stmib r0!, {r8-r14} "); // save R8_fiq ... R14_fiq
1.723 + asm("mrs r3, spsr ");
1.724 + asm("str r3, [r0, #4]! "); // save SPSR_fiq
1.725 + asm("bic r2, r1, #0x1f ");
1.726 + asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off
1.727 + asm("msr cpsr, r2 ");
1.728 +
1.729 + asm("mov r4, #0 ");
1.730 + asm("mov r5, #0 ");
1.731 + asm("mov r6, #0 ");
1.732 + asm("mov r7, #0 ");
1.733 + asm("mov r8, #0 ");
1.734 + asm("mov r9, #0 ");
1.735 + asm("mov r10, #0 ");
1.736 + asm("mov r11, #0 ");
1.737 +
1.738 + // monitor mode - skip for now
1.739 + asm("mov r3, #0 ");
1.740 + asm("stmib r0!, {r4-r6} "); // R13_mon, R14_mon, SPSR_mon
1.741 +
1.742 + // zero spare words
1.743 + asm("mov r3, #0 ");
1.744 + asm("stmib r0!, {r4-r11} ");
1.745 + asm("add r0, r0, #4 "); // r0 = &a.iA
1.746 +
1.747 +#ifdef __CPU_ARMV7
1.748 + asm("mrc p14, 6, r3, c1, c0, 0 ");
1.749 +#else
1.750 + asm("mov r3, #0 ");
1.751 +#endif
1.752 + asm("str r3, [r0], #4 "); // TEEHBR
1.753 +#ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
1.754 + GET_CAR(,r3);
1.755 +#else
1.756 + asm("mov r3, #0 ");
1.757 +#endif
1.758 + asm("str r3, [r0], #4 "); // CPACR
1.759 +
1.760 + // skip SCR, SDER, NSACR, PMCR, MVBAR for now
1.761 + asm("mov r3, #0 ");
1.762 + asm("stmia r0!, {r4-r8} "); // SCR, SDER, NSACR, PMCR, MVBAR
1.763 +
1.764 + // zero spare words
1.765 + asm("mov r3, #0 ");
1.766 + asm("stmia r0!, {r3-r11} "); // r0 = &a.iB[0]
1.767 +
1.768 + // just fill in iB[0]
1.769 +#ifdef __CPU_HAS_MMU
1.770 + asm("mrc p15, 0, r3, c1, c0, 0 ");
1.771 + asm("str r3, [r0], #4 "); // SCTLR
1.772 +#ifdef __CPU_HAS_ACTLR
1.773 + asm("mrc p15, 0, r3, c1, c0, 1 ");
1.774 +#else
1.775 + asm("mov r3, #0 ");
1.776 +#endif
1.777 + asm("str r3, [r0], #4 "); // ACTLR
1.778 + asm("mrc p15, 0, r3, c2, c0, 0 ");
1.779 + asm("str r3, [r0], #4 "); // TTBR0
1.780 +#ifdef __CPU_HAS_TTBR1
1.781 + asm("mrc p15, 0, r2, c2, c0, 1 ");
1.782 + asm("mrc p15, 0, r3, c2, c0, 2 ");
1.783 +#else
1.784 + asm("mov r2, #0 ");
1.785 + asm("mov r3, #0 ");
1.786 +#endif
1.787 + asm("stmia r0!, {r2,r3} "); // TTBR1, TTBCR
1.788 + asm("mrc p15, 0, r3, c3, c0, 0 ");
1.789 + asm("str r3, [r0], #4 "); // DACR
1.790 +#ifdef __CPU_MEMORY_TYPE_REMAPPING
1.791 + asm("mrc p15, 0, r2, c10, c2, 0 ");
1.792 + asm("mrc p15, 0, r3, c10, c2, 1 ");
1.793 +#else
1.794 + asm("mov r2, #0 ");
1.795 + asm("mov r3, #0 ");
1.796 +#endif
1.797 + asm("stmia r0!, {r2,r3} "); // PRRR, NMRR
1.798 +#ifdef __CPU_ARMV7
1.799 + asm("mrc p15, 0, r3, c12, c0, 0 ");
1.800 +#else
1.801 + asm("mov r3, #0 ");
1.802 +#endif
1.803 + asm("str r3, [r0], #4 "); // VBAR
1.804 +#if defined(__CPU_SA1) || defined(__CPU_ARM920T) || defined(__CPU_ARM925T) || defined(__CPU_ARMV5T) || defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
1.805 + asm("mrc p15, 0, r3, c13, c0, 0 ");
1.806 +#else
1.807 + asm("mov r3, #0 ");
1.808 +#endif
1.809 + asm("str r3, [r0], #4 "); // FCSEIDR
1.810 +#if defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
1.811 + asm("mrc p15, 0, r3, c13, c0, 1 ");
1.812 +#else
1.813 + asm("mov r3, #0 ");
1.814 +#endif
1.815 + asm("str r3, [r0], #4 "); // CONTEXTIDR
1.816 +#ifdef __CPU_HAS_CP15_THREAD_ID_REG
1.817 + GET_RWRW_TID(,r2);
1.818 + GET_RWRO_TID(,r3);
1.819 + GET_RWNO_TID(,r12);
1.820 +#else
1.821 + asm("mov r2, #0 ");
1.822 + asm("mov r3, #0 ");
1.823 + asm("mov r12, #0 ");
1.824 +#endif
1.825 + asm("stmia r0!, {r2,r3,r12} "); // RWRWTID, RWROTID, RWNOTID
1.826 + asm("mrc p15, 0, r2, c5, c0, 0 "); // DFSR
1.827 +#ifdef __CPU_ARM_HAS_SPLIT_FSR
1.828 + asm("mrc p15, 0, r3, c5, c0, 1 "); // IFSR
1.829 +#else
1.830 + asm("mov r3, #0 ");
1.831 +#endif
1.832 + asm("stmia r0!, {r2,r3} "); // DFSR, IFSR
1.833 +#ifdef __CPU_ARMV7
1.834 + asm("mrc p15, 0, r2, c5, c1, 0 "); // ADFSR
1.835 + asm("mrc p15, 0, r3, c5, c1, 1 "); // AIFSR
1.836 +#else
1.837 + asm("mov r2, #0 ");
1.838 + asm("mov r3, #0 ");
1.839 +#endif
1.840 + asm("stmia r0!, {r2,r3} "); // ADFSR, AIFSR
1.841 + asm("mrc p15, 0, r2, c6, c0, 0 "); // DFAR
1.842 +#ifdef __CPU_ARM_HAS_CP15_IFAR
1.843 + asm("mrc p15, 0, r3, c6, c0, 2 "); // IFAR
1.844 +#else
1.845 + asm("mov r3, #0 ");
1.846 +#endif
1.847 + asm("stmia r0!, {r2,r3} "); // DFAR, IFAR
1.848 +
1.849 + // zero spare words
1.850 + asm("stmia r0!, {r4-r7} ");
1.851 + asm("stmia r0!, {r4-r11} ");
1.852 +#else // __CPU_HAS_MMU
1.853 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.854 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.855 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.856 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.857 +#endif // __CPU_HAS_MMU
1.858 +
1.859 + // zero iB[1]
1.860 + asm("stmia r0!, {r4-r11} ");
1.861 + asm("stmia r0!, {r4-r11} ");
1.862 + asm("stmia r0!, {r4-r11} ");
1.863 + asm("stmia r0!, {r4-r11} "); // r0 = &a.iMore[0]
1.864 + asm("add r1, r0, #62*8 "); // r1 = &a.iExcCode
1.865 +
1.866 + // Save VFP state
1.867 + // Save order:
1.868 + // FPEXC FPSCR
1.869 + // VFPv2 ONLY: FPINST FPINST2
1.870 + // D0-D3 D4-D7 D8-D11 D12-D15
1.871 + // VFPv3 ONLY: D16-D19 D20-D23 D24-D27 D28-D31
1.872 +#ifdef __CPU_HAS_VFP
1.873 + GET_CAR(,r2);
1.874 + asm("bic r2, r2, #0x00f00000 ");
1.875 +#ifdef __VFP_V3
1.876 + asm("bic r2, r2, #0xc0000000 "); // mask off ASEDIS, D32DIS
1.877 +#endif
1.878 + asm("orr r2, r2, #0x00500000 "); // enable privileged access to CP10, CP11
1.879 + SET_CAR(,r2);
1.880 + VFP_FMRX(,2,VFP_XREG_FPEXC); // r2=FPEXC
1.881 + asm("orr r3, r2, #%a0" : : "i" ((TInt)VFP_FPEXC_EN));
1.882 + asm("bic r3, r3, #%a0" : : "i" ((TInt)VFP_FPEXC_EX));
1.883 + VFP_FMXR(,VFP_XREG_FPEXC,3); // enable VFP
1.884 + __DATA_SYNC_BARRIER__(r4);
1.885 + __INST_SYNC_BARRIER__(r4);
1.886 + VFP_FMRX(,3,VFP_XREG_FPSCR); // r3=FPSCR
1.887 + asm("stmia r0!, {r2,r3} "); //
1.888 +#ifdef __VFP_V3
1.889 + VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15
1.890 + VFP_FMRX(,3,VFP_XREG_MVFR0);
1.891 + asm("tst r3, #%a0" : : "i" ((TInt)VFP_MVFR0_ASIMD32)); // check to see if all 32 Advanced SIMD registers are present
1.892 + VFP_FSTMIADW(CC_NE,0,16,16); // if so then save D15 - D31 (don't need to check CPACR.D32DIS as it is cleared above)
1.893 +#else
1.894 + VFP_FMRX(,2,VFP_XREG_FPINST);
1.895 + VFP_FMRX(,3,VFP_XREG_FPINST2);
1.896 + asm("stmia r0!, {r2,r3} "); // FPINST, FPINST2
1.897 + VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15
1.898 +#endif
1.899 +#endif // __CPU_HAS_VFP
1.900 + asm("1: ");
1.901 + asm("cmp r0, r1 ");
1.902 + asm("strlo r4, [r0], #4 "); // clear up to end of iMore[61]
1.903 + asm("blo 1b ");
1.904 + asm("mov r1, #%a0" : : "i" ((TInt)KMaxTInt));
1.905 + asm("stmia r0!, {r1,r5-r7} "); // iExcCode=KMaxTInt, iCrashArgs[0...2]=0
1.906 + asm("sub r0, r0, #1024 "); // r0 = &a
1.907 +#ifdef __CPU_HAS_VFP
1.908 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iMore[0]));
1.909 + VFP_FMXR(,VFP_XREG_FPEXC,2); // restore FPEXC
1.910 + __DATA_SYNC_BARRIER__(r4);
1.911 + __INST_SYNC_BARRIER__(r4);
1.912 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iA.iCPACR));
1.913 + SET_CAR(,r2); // restore CPACR
1.914 +#endif
1.915 + asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
1.916 + asm("orr r1, r1, #0xC0 "); // interrupts off
1.917 + asm("msr cpsr, r1 "); // restore CPSR with interrupts off
1.918 + asm("ldmia r0, {r0-r11} "); // restore R4-R11
1.919 + __JUMP(,lr);
1.920 + }
1.921 +
1.922 +
1.923 +/** Update the saved ARM registers with information from an exception
1.924 +
1.925 +@internalTechnology
1.926 +*/
1.927 +__NAKED__ void Arm::UpdateState(SFullArmRegSet&, TArmExcInfo&)
1.928 + {
1.929 + asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(TArmExcInfo, iExcCode));
1.930 + asm("cmp r2, #%a0 " : : "i" ((TInt)EArmExceptionPrefetchAbort));
1.931 + asm("ldmia r1!, {r2,r3,r12} ");
1.932 + asm("streq r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFAR));
1.933 + asm("strne r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFAR));
1.934 + asm("streq r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFSR));
1.935 + asm("strne r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFSR));
1.936 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iSpsrSvc));
1.937 + asm("add r1, r1, #4 ");
1.938 + asm("ldmia r1!, {r2,r3,r12} ");
1.939 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13Svc));
1.940 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14Svc));
1.941 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR0));
1.942 + asm("ldmia r1!, {r2,r3,r12} ");
1.943 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR1));
1.944 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR2));
1.945 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR3));
1.946 + asm("ldmia r1!, {r2,r3,r12} ");
1.947 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR4));
1.948 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR5));
1.949 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR6));
1.950 + asm("ldmia r1!, {r2,r3,r12} ");
1.951 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR7));
1.952 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR8));
1.953 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR9));
1.954 + asm("ldmia r1!, {r2,r3,r12} ");
1.955 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR10));
1.956 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR11));
1.957 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR12));
1.958 + asm("ldmia r1!, {r2,r3,r12} ");
1.959 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13));
1.960 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14));
1.961 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode));
1.962 + asm("ldmia r1!, {r2,r3} ");
1.963 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR15));
1.964 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
1.965 + __JUMP(,lr);
1.966 + }
1.967 +
1.968 +
1.969 +/** Get a pointer to a stored integer register, accounting for registers which
1.970 + are banked across modes.
1.971 +
1.972 +@param a Pointer to saved register block
1.973 +@param aRegNum Number of register required, 0-15 or -1 (indicates SPSR)
1.974 +@param aMode Bottom 5 bits indicate which processor mode
1.975 + Other bits of aMode are ignored
1.976 +@return Pointer to the required saved register value
1.977 +
1.978 +@internalTechnology
1.979 +*/
1.980 +__NAKED__ TArmReg* Arm::Reg(SFullArmRegSet& /*a*/, TInt /*aRegNum*/, TArmReg /*aMode*/)
1.981 + {
1.982 + asm("cmp r1, #8 "); // register number < 8 ?
1.983 + asm("addlo r0, r0, r1, lsl #2 "); // register R0-R7 are not banked
1.984 + asm("blo 0f ");
1.985 + asm("cmp r1, #15 "); // register number = 15 ?
1.986 + asm("addeq r0, r0, r1, lsl #2 "); // register R15 not banked
1.987 + asm("movgt r0, #0 "); // no registers > 15
1.988 + asm("bge 0f ");
1.989 + asm("cmn r1, #1 ");
1.990 + asm("movlt r0, #0 "); // no registers < -1
1.991 + asm("blt 0f ");
1.992 + asm("and r12, r2, #0x1F ");
1.993 + asm("cmp r12, #0x11 "); // mode_fiq?
1.994 + asm("beq 1f "); // skip if it is
1.995 + asm("cmp r1, #13 ");
1.996 + asm("addlo r0, r0, r1, lsl #2 "); // register R8-R12 are only banked in mode_fiq
1.997 + asm("blo 0f ");
1.998 + asm("cmp r12, #0x10 "); // mode_usr ?
1.999 + asm("cmpne r12, #0x1F "); // if not, mode_sys ?
1.1000 + asm("bne 2f "); // skip if neither
1.1001 + asm("cmp r1, #16 ");
1.1002 + asm("addlo r0, r0, r1, lsl #2 "); // handle R13_usr, R14_usr
1.1003 + asm("movhs r0, #0 "); // no SPSR in mode_usr or mode_sys
1.1004 + asm("blo 0f ");
1.1005 + asm("1: "); // mode_fiq, regnum = 8-12
1.1006 + asm("2: "); // exception mode, regnum not 0-12 or 15
1.1007 + asm("cmn r1, #1 "); // regnum = -1 ?
1.1008 + asm("moveq r1, #15 "); // if so, change to 15
1.1009 + asm("sub r1, r1, #13 ");
1.1010 + asm("add r0, r0, r1, lsl #2 "); // add 0 for R13, 4 for R14, 8 for SPSR
1.1011 + asm("cmp r12, #0x16 ");
1.1012 + asm("addeq r0, r0, #12 "); // if mon, add offset from R13Fiq to R13Mon
1.1013 + asm("cmpne r12, #0x11 ");
1.1014 + asm("addeq r0, r0, #32 "); // if valid but not svc/abt/und/irq, add offset from R13Irq to R13Fiq
1.1015 + asm("cmpne r12, #0x12 ");
1.1016 + asm("addeq r0, r0, #12 "); // if valid but not svc/abt/und, add offset from R13Und to R13Irq
1.1017 + asm("cmpne r12, #0x1b ");
1.1018 + asm("addeq r0, r0, #12 "); // if valid but not svc/abt, add offset from R13Abt to R13Und
1.1019 + asm("cmpne r12, #0x17 ");
1.1020 + asm("addeq r0, r0, #12 "); // if valid but not svc, add offset from R13Svc to R13Abt
1.1021 + asm("cmpne r12, #0x13 ");
1.1022 + asm("addeq r0, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iN.iR13Svc)); // if valid mode add offset to R13Svc
1.1023 + asm("movne r0, #0 ");
1.1024 + asm("0: ");
1.1025 + __JUMP(,lr);
1.1026 + }
1.1027 +
1.1028 +
1.1029 +/** Restore all the ARM registers
1.1030 +
1.1031 +@internalTechnology
1.1032 +*/
1.1033 +__NAKED__ void Arm::RestoreState(SFullArmRegSet&)
1.1034 + {
1.1035 + }
1.1036 +
1.1037 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredPcFormatBig(TUint32 a0, TUint32 aModuleUid, TUint32 aPc, TUint16 aFormatId, const TAny* aData, TInt aDataSize)
1.1038 + {
1.1039 + asm("mov r0, #0"); //Kernel side not implemented yet
1.1040 + }
1.1041 +
1.1042 +
1.1043 +
1.1044 +
1.1045 +