1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/nkern/arm/ncutils.cia Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,987 @@
1.4 +// Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\nkern\arm\ncutils.cia
1.18 +//
1.19 +//
1.20 +
1.21 +#include <e32cia.h>
1.22 +#include <arm.h>
1.23 +
1.24 +//#define __DBG_MON_FAULT__
1.25 +//#define __RAM_LOADED_CODE__
1.26 +//#define __EARLY_DEBUG__
1.27 +
1.28 +#ifdef _DEBUG
1.29 +#define ASM_KILL_LINK(rp,rs) asm("mov "#rs", #0xdf ");\
1.30 + asm("orr "#rs", "#rs", "#rs", lsl #8 ");\
1.31 + asm("orr "#rs", "#rs", "#rs", lsl #16 ");\
1.32 + asm("str "#rs", ["#rp"] ");\
1.33 + asm("str "#rs", ["#rp", #4] ");
1.34 +#else
1.35 +#define ASM_KILL_LINK(rp,rs)
1.36 +#endif
1.37 +
1.38 +
1.39 +#ifdef __PRI_LIST_MACHINE_CODED__
1.40 +/** Return the priority of the highest priority item present on a priority list.
1.41 +
1.42 + @return The highest priority present or -1 if the list is empty.
1.43 + */
1.44 +EXPORT_C __NAKED__ TInt TPriListBase::HighestPriority()
1.45 + {
1.46 +#ifdef __CPU_ARM_HAS_CLZ
1.47 + asm("ldr r2, [r0, #4] "); // r2=iPresent MSW
1.48 + asm("ldr r1, [r0, #0] "); // r1=iPresent LSW
1.49 + CLZ(0,2); // r0=31-MSB(r2)
1.50 + asm("subs r0, r0, #32 "); // r0=-1-MSB(r2), 0 if r2=0
1.51 + CLZcc(CC_EQ,0,1); // if r2=0, r0=31-MSB(r1)
1.52 + asm("rsb r0, r0, #31 "); // r0=highest priority
1.53 +#else
1.54 + asm("ldmia r0, {r1,r2} "); // r2:r1=iPresent
1.55 + asm("mov r0, #31 "); // start at 31
1.56 + asm("cmp r2, #0 "); // high word non-zero?
1.57 + asm("movne r0, #63 "); // if so, start at 63
1.58 + asm("movne r1, r2 "); // and set r1=high word
1.59 + asm("cmp r1, #0 ");
1.60 + asm("beq highest_pri_0 ");
1.61 + asm("cmp r1, #0x00010000 ");
1.62 + asm("movcc r1, r1, lsl #16 ");
1.63 + asm("subcc r0, r0, #16 ");
1.64 + asm("cmp r1, #0x01000000 ");
1.65 + asm("movcc r1, r1, lsl #8 ");
1.66 + asm("subcc r0, r0, #8 ");
1.67 + asm("cmp r1, #0x10000000 ");
1.68 + asm("movcc r1, r1, lsl #4 ");
1.69 + asm("subcc r0, r0, #4 ");
1.70 + asm("cmp r1, #0x40000000 ");
1.71 + asm("movcc r1, r1, lsl #2 ");
1.72 + asm("subcc r0, r0, #2 ");
1.73 + asm("cmp r1, #0x80000000 ");
1.74 + asm("subcc r0, r0, #1 ");
1.75 + __JUMP(,lr);
1.76 + asm("highest_pri_0: ");
1.77 + asm("mvn r0, #0 "); // if list empty, return -1
1.78 +#endif
1.79 + __JUMP(,lr);
1.80 + }
1.81 +
1.82 +/** Find the highest priority item present on a priority list.
1.83 + If multiple items at the same priority are present, return the first to be
1.84 + added in chronological order.
1.85 +
1.86 + @return a pointer to the item or NULL if the list is empty.
1.87 + */
1.88 +EXPORT_C __NAKED__ TPriListLink* TPriListBase::First()
1.89 + {
1.90 +#ifdef __CPU_ARM_HAS_CLZ
1.91 + asm("ldr r2, [r0, #4] "); // r2=iPresent MSW
1.92 + asm("ldr r1, [r0], #8 "); // r1=iPresent LSW, r0=&iQueue[0]
1.93 + CLZ(3,2); // r3=31-MSB(r2)
1.94 + asm("subs r3, r3, #32 "); // r3=-1-MSB(r2), 0 if r2=0
1.95 + CLZcc(CC_EQ,3,1); // if r2=0, r3=31-MSB(r1)
1.96 + asm("rsbs r3, r3, #31 "); // r3=highest priority
1.97 + asm("ldrpl r0, [r0, r3, lsl #2] "); // if r3>=0 list is nonempty, r0->first entry
1.98 + asm("movmi r0, #0 "); // if r3<0 list empty, return NULL
1.99 +#else
1.100 + asm("ldmia r0!, {r1,r2} "); // r2:r1=iPresent, r0=&iQueue[0]
1.101 + asm("cmp r2, #0 "); // high word non-zero?
1.102 + asm("addne r0, r0, #128 "); // if so, r0=&iQueue[32]
1.103 + asm("movne r1, r2 "); // and set r1=high word
1.104 + asm("cmp r1, #0x00010000 ");
1.105 + asm("movcc r1, r1, lsl #16 ");
1.106 + asm("addcs r0, r0, #0x40 "); // if iPresent>=0x00010000, step r0 on by 16 words
1.107 + asm("cmp r1, #0x01000000 ");
1.108 + asm("movcc r1, r1, lsl #8 ");
1.109 + asm("addcs r0, r0, #0x20 "); // if iPresent>=0x01000000, step r0 on by 8 words
1.110 + asm("cmp r1, #0x10000000 ");
1.111 + asm("movcc r1, r1, lsl #4 ");
1.112 + asm("addcs r0, r0, #0x10 "); // if iPresent>=0x10000000, step r0 on by 4 words
1.113 + asm("cmp r1, #0x40000000 ");
1.114 + asm("movcc r1, r1, lsl #2 ");
1.115 + asm("addcs r0, r0, #0x08 "); // if iPresent>=0x40000000, step r0 on by 2 words
1.116 + asm("cmp r1, #0 ");
1.117 + asm("addmi r0, r0, #4 "); // if iPresent>=0x80000000, step r0 on by 1 word
1.118 + asm("ldrne r0, [r0] "); // if iPresent was not zero, r0 points to first entry
1.119 + asm("moveq r0, #0 "); // else r0=NULL
1.120 +#endif
1.121 + __JUMP(,lr);
1.122 + }
1.123 +
1.124 +/** Add an item to a priority list.
1.125 +
1.126 + @param aLink = a pointer to the item - must not be NULL
1.127 + */
1.128 +EXPORT_C __NAKED__ void TPriListBase::Add(TPriListLink* /*aLink*/)
1.129 + {
1.130 + asm("ldrb r2, [r1, #8]" ); // r2=priority of aLink
1.131 + asm("add ip, r0, #8 "); // ip=&iQueue[0]
1.132 + asm("ldr r3, [ip, r2, lsl #2]! "); // r3->first entry at this priority
1.133 + asm("cmp r3, #0 "); // is this first entry at this priority?
1.134 + asm("bne pri_list_add_1 "); // branch if not
1.135 + asm("str r1, [ip] "); // if queue originally empty, iQueue[pri]=aThread
1.136 + asm("ldrb ip, [r0, r2, lsr #3]! "); // ip=relevant byte of present mask, r0->same
1.137 + asm("and r2, r2, #7 ");
1.138 + asm("mov r3, #1 ");
1.139 + asm("str r1, [r1, #0] "); // aThread->next=aThread
1.140 + asm("orr ip, ip, r3, lsl r2 "); // ip |= 1<<(pri&7)
1.141 + asm("str r1, [r1, #4] "); // aThread->iPrev=aThread
1.142 + asm("strb ip, [r0] "); // update relevant byte of present mask
1.143 + __JUMP(,lr);
1.144 + asm("pri_list_add_1: ");
1.145 + asm("ldr ip, [r3, #4] "); // if nonempty, ip=last
1.146 + asm("str r1, [r3, #4] "); // first->prev=aThread
1.147 + asm("stmia r1, {r3,ip} "); // aThread->next=r3=first, aThread->prev=ip=last
1.148 + asm("str r1, [ip, #0] "); // last->next=aThread
1.149 + __JUMP(,lr);
1.150 + }
1.151 +
1.152 +/** Change the priority of an item on a priority list
1.153 +
1.154 + @param aLink = pointer to the item to act on - must not be NULL
1.155 + @param aNewPriority = new priority for the item
1.156 + */
1.157 +EXPORT_C __NAKED__ void TPriListBase::ChangePriority(TPriListLink* /*aLink*/, TInt /*aNewPriority*/)
1.158 + {
1.159 + asm("ldrb r3, [r1, #8] "); // r3=old priority
1.160 + asm("stmfd sp!, {r4-r6,lr} ");
1.161 + asm("cmp r3, r2 ");
1.162 + asm("ldmeqfd sp!, {r4-r6,pc} "); // if old priority=new, finished
1.163 + asm("ldmia r1, {r4,r12} "); // r4=next, r12=prev
1.164 + asm("ldmia r0!, {r6,lr} "); // lr:r6=present mask, r0=&iQueue[0]
1.165 + asm("subs r5, r4, r1 "); // check if aLink is only one at that priority, r5=0 if it is
1.166 + asm("beq change_pri_1 "); // branch if it is
1.167 + asm("ldr r5, [r0, r3, lsl #2] "); // r5=iQueue[old priority]
1.168 + asm("str r4, [r12, #0] "); // prev->next=next
1.169 + asm("str r12, [r4, #4] "); // next->prev=prev
1.170 + asm("cmp r5, r1 "); // was aLink first?
1.171 + asm("streq r4, [r0, r3, lsl #2] "); // if it was, iQueue[old priority]=aLink->next
1.172 + asm("b change_pri_2 ");
1.173 + asm("change_pri_1: ");
1.174 + asm("str r5, [r0, r3, lsl #2] "); // if empty, set iQueue[old priority]=NULL
1.175 + asm("mov r12, #0x80000000 ");
1.176 + asm("rsbs r3, r3, #31 "); // r3=31-priority
1.177 + asm("bicmi lr, lr, r12, ror r3 "); // if pri>31, clear bit is MS word
1.178 + asm("bicpl r6, r6, r12, ror r3 "); // if pri<=31, clear bit in LS word
1.179 + asm("change_pri_2: ");
1.180 + asm("ldr r4, [r0, r2, lsl #2] "); // r4=iQueue[new priority]
1.181 + asm("strb r2, [r1, #8] "); // store new priority
1.182 + asm("cmp r4, #0 "); // new priority queue empty?
1.183 + asm("bne change_pri_3 "); // branch if not
1.184 + asm("str r1, [r0, r2, lsl #2] "); // if new priority queue was empty, iQueue[new p]=aLink
1.185 + asm("mov r12, #0x80000000 ");
1.186 + asm("str r1, [r1, #0] "); // aLink->next=aLink
1.187 + asm("rsbs r2, r2, #31 "); // r2=31-priority
1.188 + asm("str r1, [r1, #4] "); // aLink->prev=aLink
1.189 + asm("orrmi lr, lr, r12, ror r2 "); // if pri>31, set bit is MS word
1.190 + asm("orrpl r6, r6, r12, ror r2 "); // if pri<=31, set bit in LS word
1.191 + asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0
1.192 + asm("ldmfd sp!, {r4-r6,pc} ");
1.193 + asm("change_pri_3: ");
1.194 + asm("ldr r12, [r4, #4] "); // r12->last link at this priority
1.195 + asm("str r1, [r4, #4] "); // first->prev=aLink
1.196 + asm("str r1, [r12, #0] "); // old last->next=aLink
1.197 + asm("stmia r1, {r4,r12} "); // aLink->next=r3=first, aLink->prev=r12=old last
1.198 + asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0
1.199 + asm("ldmfd sp!, {r4-r6,pc} ");
1.200 + }
1.201 +#endif
1.202 +
1.203 +__NAKED__ void initialiseState()
1.204 + {
1.205 + // entry in mode_svc with irqs and fiqs off
1.206 + asm("mrs r0, cpsr ");
1.207 + asm("bic r1, r0, #0x1f ");
1.208 + asm("orr r1, r1, #0xd3 "); // mode_svc
1.209 + asm("msr cpsr, r1 ");
1.210 + __JUMP(,lr);
1.211 + }
1.212 +
1.213 +// Called by a thread when it first runs
1.214 +__NAKED__ void __StartThread()
1.215 + {
1.216 + // On entry r4->current thread, r5->entry point, r6->parameter block
1.217 + asm("mov r0, r6 ");
1.218 + USER_MEMORY_GUARD_OFF_IF_MODE_USR(r6);
1.219 + ERRATUM_353494_MODE_CHANGE(,r6);
1.220 + asm("mov lr, pc ");
1.221 + asm("movs pc, r5 ");
1.222 + asm("b " CSM_ZN5NKern4ExitEv);
1.223 + }
1.224 +
1.225 +// Called by a thread which has been forced to exit
1.226 +// Interrupts off here, kernel unlocked
1.227 +__NAKED__ void __DoForcedExit()
1.228 + {
1.229 + asm("mov r0, #0x13 ");
1.230 + asm("msr cpsr, r0 "); // interrupts back on
1.231 + asm("bic sp, sp, #4 "); // align stack since it may be misaligned on return from scheduler
1.232 + asm("bl " CSM_ZN5NKern4LockEv); // lock the kernel (must do this before setting iCsCount=0)
1.233 + asm("ldr r0, __TheScheduler "); // r0 points to scheduler data
1.234 + asm("mov r1, #0 ");
1.235 + asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r0=iCurrentThread
1.236 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount)); // set iCsCount=0
1.237 + asm("b " CSM_ZN11NThreadBase4ExitEv); // exit
1.238 +
1.239 + asm("__TheScheduler: ");
1.240 + asm(".word TheScheduler ");
1.241 + asm("__BTraceData: ");
1.242 + asm(".word BTraceData ");
1.243 + asm("__DBTraceFilter2_iCleanupHead:");
1.244 +#ifdef __EABI__
1.245 + asm(".word _ZN14DBTraceFilter212iCleanupHeadE");
1.246 +#else
1.247 + asm(".word _14DBTraceFilter2.iCleanupHead");
1.248 +#endif
1.249 + }
1.250 +
1.251 +
1.252 +/** @internalTechnology
1.253 +
1.254 + Called to indicate that the system has crashed and all CPUs should be
1.255 + halted and should dump their registers.
1.256 +
1.257 +*/
1.258 +__NAKED__ void NKern::NotifyCrash(const TAny* /*a0*/, TInt /*a1*/)
1.259 + {
1.260 + asm("stmfd sp!, {r0-r1} "); // save parameters
1.261 + asm("ldr r0, __CrashState ");
1.262 + asm("mov r1, #1 ");
1.263 + asm("str r1, [r0] "); // CrashState = ETrue
1.264 + asm("ldr r0, __TheScheduler ");
1.265 + asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,i_Regs));
1.266 + asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.267 + asm("cmp r1, #0 "); // context already saved?
1.268 + asm("bge state_already_saved "); // skip if so
1.269 + asm("mov r1, lr ");
1.270 + asm("bl " CSM_ZN3Arm9SaveStateER14SFullArmRegSet );
1.271 + asm("str r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iN.iR15));
1.272 + asm("ldmia sp!, {r2-r3} "); // original R0,R1
1.273 + asm("stmia r0, {r2-r3} "); // save original R0,R1
1.274 + asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.275 + asm("stmib r1, {r2-r3} "); // save a0, a1 in iCrashArgs
1.276 + asm("mov r1, #13 "); // r1 = regnum
1.277 + asm("mrs r2, cpsr "); // r2 = mode
1.278 + asm("bl " CSM_ZN3Arm3RegER14SFullArmRegSetim ); // r0 = pointer to exception mode R13
1.279 + asm("str sp, [r0] "); // save correct original value for exception mode R13
1.280 + asm("b state_save_complete ");
1.281 +
1.282 + asm("state_already_saved: ");
1.283 + asm("ldmia sp!, {r2-r3} "); // original R0,R1
1.284 + asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode));
1.285 + asm("ldr r4, [r1, #4]! ");
1.286 + asm("cmp r4, #0 ");
1.287 + asm("stmeqia r1, {r2-r3} "); // save a0, a1 in iCrashArgs, provided iCrashArgs not already set
1.288 + asm("state_save_complete: ");
1.289 +
1.290 + asm("mov r2, #0xd1 ");
1.291 + asm("msr cpsr, r2 "); // mode_fiq, interrupts off
1.292 + asm("mov r4, r0 ");
1.293 + asm("bic sp, sp, #4 "); // align stack to multiple of 8
1.294 +
1.295 + asm("mov r0, #0 ");
1.296 + asm("mov r1, #0 ");
1.297 + asm("mov r2, #0 ");
1.298 + asm("bl NKCrashHandler ");
1.299 +
1.300 + asm("mov r0, #1 ");
1.301 + asm("ldr r1, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR0)); // original R0 = a0 parameter
1.302 + asm("ldr r2, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR1)); // original R1 = a1 parameter
1.303 + asm("bl NKCrashHandler ");
1.304 +
1.305 + // shouldn't get back here
1.306 + __ASM_CRASH();
1.307 +
1.308 + asm("__CrashState: ");
1.309 + asm(".word %a0" : : "i" ((TInt)&CrashState));
1.310 + }
1.311 +
1.312 +
1.313 +
1.314 +__NAKED__ EXPORT_C TBool BTrace::Out(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.315 + {
1.316 + asm("ldr r12, __BTraceData");
1.317 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.318 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.319 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.320 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.321 + asm("adr lr, 9f");
1.322 + asm("cmp r2, #0");
1.323 + asm("moveq r0, #0");
1.324 + asm("ldrne pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.325 + asm("9:");
1.326 + __POPRET("r2,r3,r4,");
1.327 + }
1.328 +
1.329 +__NAKED__ EXPORT_C TBool BTrace::OutN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.330 + {
1.331 + asm("ldr r12, __BTraceData");
1.332 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.333 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.334 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.335 + asm("ldr r4, [sp, #16]"); // r2 = aDataSize
1.336 + asm("cmp r2, #0");
1.337 + asm("moveq r0, #0");
1.338 + __CPOPRET(eq,"r2,r3,r4,");
1.339 +
1.340 + asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.341 + asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.342 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.343 + asm("add r0, r0, r4");
1.344 + asm("subs r4, r4, #1");
1.345 + asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0
1.346 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.347 + asm("cmp r4, #4");
1.348 + asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4
1.349 +
1.350 + asm("mov lr, pc");
1.351 + asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.352 + __POPRET("r2,r3,r4,");
1.353 + }
1.354 +
1.355 +__NAKED__ EXPORT_C TBool BTrace::OutX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.356 + {
1.357 + asm("ldr r12, __BTraceData");
1.358 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.359 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.360 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.361 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.362 + asm("ldr lr, __TheScheduler");
1.363 + asm("cmp r2, #0");
1.364 + asm("moveq r0, #0");
1.365 + __CPOPRET(eq,"r2,r3,r4,");
1.366 +
1.367 + // set r2 = context id
1.368 + asm("ldrb r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
1.369 + asm("mrs r2, cpsr");
1.370 + asm("and r2, r2, #0x0f");
1.371 + asm("cmp r2, #3");
1.372 + asm("movhi r2, #2"); // r2 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.373 + asm("cmpeq r4, #0");
1.374 + asm("ldreq r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
1.375 +
1.376 + asm("mov lr, pc");
1.377 + asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.378 + __POPRET("r2,r3,r4,");
1.379 + }
1.380 +
1.381 +__NAKED__ EXPORT_C TBool BTrace::OutNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.382 + {
1.383 + asm("ldr r12, __BTraceData");
1.384 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.385 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.386 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.387 + asm("ldr r4, [sp, #16]"); // r2 = aDataSize
1.388 + asm("ldr lr, __TheScheduler");
1.389 + asm("cmp r2, #0");
1.390 + asm("moveq r0, #0");
1.391 + __CPOPRET(eq,"r2,r3,r4,");
1.392 +
1.393 + asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.394 + asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.395 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.396 + asm("add r0, r0, r4");
1.397 + asm("subs r4, r4, #1");
1.398 + asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0
1.399 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.400 + asm("cmp r4, #4");
1.401 + asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4
1.402 +
1.403 + // set r2 = context id
1.404 + asm("ldrb r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
1.405 + asm("mrs r2, cpsr");
1.406 + asm("and r2, r2, #0x0f");
1.407 + asm("cmp r2, #3");
1.408 + asm("movhi r2, #2"); // r2 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.409 + asm("cmpeq r4, #0");
1.410 + asm("ldreq r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
1.411 +
1.412 + asm("mov lr, pc");
1.413 + asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.414 + __POPRET("r2,r3,r4,");
1.415 + }
1.416 +
1.417 +__NAKED__ EXPORT_C TBool BTrace::OutBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
1.418 + {
1.419 + asm("ldr r12, __BTraceData");
1.420 + asm("stmdb sp!, {r4,lr}");
1.421 + asm("and r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.422 + asm("ldrb r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.423 + asm("cmp r4, #0");
1.424 + asm("moveq r0, #0");
1.425 + __CPOPRET(eq,"r4,");
1.426 +
1.427 + asm("ldr r12, __TheScheduler");
1.428 + asm("stmdb sp!, {lr}");
1.429 + asm("ldrb lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
1.430 + asm("mrs r4, cpsr");
1.431 + asm("and r4, r4, #0x0f");
1.432 + asm("cmp r4, #3");
1.433 + asm("movhi r4, #2"); // r4 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.434 + asm("cmpeq lr, #0");
1.435 + asm("ldreq r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
1.436 + asm("stmdb sp!, {r4}");
1.437 + asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
1.438 + asm("add sp, sp, #8");
1.439 + __POPRET("r4,");
1.440 + }
1.441 +
1.442 +
1.443 +__NAKED__ TBool DBTraceFilter2::Check(TUint32 aUid)
1.444 + {
1.445 + asm("stmdb sp!, {lr}");
1.446 + asm("ldr r3, [r0,#%a0]" : : "i" _FOFF(DBTraceFilter2,iNumUids));
1.447 + asm("add r0, r0, #%a0" : : "i" _FOFF(DBTraceFilter2,iUids));
1.448 + asm("mov r2, #0");
1.449 + asm("0:");
1.450 + asm("cmp r3, r2");
1.451 + asm("bls 9f");
1.452 + asm("add r12, r2, r3");
1.453 + asm("mov r12, r12, asr #1");
1.454 + asm("ldr lr, [r0, r12, lsl #2]");
1.455 + asm("cmp r1, lr");
1.456 + asm("addhi r2, r12, #1");
1.457 + asm("movlo r3, r12");
1.458 + asm("bne 0b");
1.459 + asm("movs r0, #1");
1.460 + __POPRET("");
1.461 + asm("9:");
1.462 + asm("movs r0, #0");
1.463 + __POPRET("");
1.464 + }
1.465 +
1.466 +
1.467 +__NAKED__ TBool SBTraceData::CheckFilter2(TUint32 aUid)
1.468 + {
1.469 + asm("btrace_check_filter2:");
1.470 + // returns r0 = 0 or 1 indicating if trace passed the filter check
1.471 + // returns r2 = trace context id
1.472 +
1.473 + asm("ldr r12, __TheScheduler");
1.474 + asm("stmdb sp!, {r4-r6,lr}");
1.475 + asm("mrs r2, cpsr");
1.476 + // r2 = cpsr
1.477 + asm("ldrb lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC));
1.478 + asm("and r4, r2, #0x0f");
1.479 + asm("cmp r4, #3");
1.480 + asm("movhi r4, #2"); // r4 = context ID => 1 for FIQ, 2 for IRQ/ABT/UND/SYS
1.481 + asm("cmpeq lr, #0");
1.482 + asm("ldreq lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iKernCSLocked));
1.483 + asm("ldreq r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread));
1.484 + asm("cmpeq lr, #0");
1.485 + // r4 = context value for trace
1.486 + // zero flag set if we need to enter a critical section
1.487 +
1.488 + // NKern::ThreadEnterCS()
1.489 + asm("ldreq r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount));
1.490 + asm("movne r5, #0");
1.491 + asm("addeq r5, r5, #1");
1.492 + asm("streq r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount));
1.493 + // r5 = true if we entered a critical section
1.494 +
1.495 + // DBTraceFilter2::Open()
1.496 + INTS_OFF(r12, r2, INTS_ALL_OFF);
1.497 + asm("ldr r0, [r0, #%a0]" : : "i" (_FOFF(SBTraceData,iFilter2)));
1.498 + asm("cmp r0, #1");
1.499 + asm("ldrhi r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
1.500 + asm("addhi r12, r12, #1");
1.501 + asm("strhi r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
1.502 + asm("msr cpsr_c, r2");
1.503 + asm("bls 8f");
1.504 +
1.505 +
1.506 + asm("mov r6, r0");
1.507 + asm("bl Check__14DBTraceFilter2Ul");
1.508 + // r0 = result
1.509 +
1.510 +
1.511 + // DBTraceFilter2::Close()
1.512 + asm("mrs r2, cpsr");
1.513 + INTS_OFF(r12, r2, INTS_ALL_OFF);
1.514 + asm("ldr r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
1.515 + asm("ldr r1, __DBTraceFilter2_iCleanupHead");
1.516 + asm("subs r12, r12, #1");
1.517 + asm("str r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount));
1.518 + asm("ldreq r12, [r1]");
1.519 + asm("streq r6, [r1]");
1.520 + asm("streq r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iCleanupLink));
1.521 + asm("msr cpsr_c, r2");
1.522 +
1.523 + // NKern::ThreadLeaveCS()
1.524 + asm("8:");
1.525 + asm("cmp r5, #0");
1.526 + asm("beq 9f");
1.527 + asm("mov r5, r0");
1.528 + asm("bl " CSM_ZN5NKern13ThreadLeaveCSEv);
1.529 + asm("mov r0, r5");
1.530 + asm("9:");
1.531 + asm("mov r2, r4"); // r2 = context id
1.532 + __POPRET("r4-r6,");
1.533 + }
1.534 +
1.535 +__NAKED__ EXPORT_C TBool BTrace::OutFiltered(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.536 + {
1.537 + // fall through to OutFilteredX...
1.538 + }
1.539 +
1.540 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3)
1.541 + {
1.542 + asm("ldr r12, __BTraceData");
1.543 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.544 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.545 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.546 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.547 + asm("cmp r2, #0");
1.548 + asm("moveq r0, #0");
1.549 + __CPOPRET(eq,"r2,r3,r4,");
1.550 +
1.551 + asm("stmdb sp!, {r0,r3,r12}");
1.552 + asm("mov r0, r12");
1.553 + asm("bl btrace_check_filter2");
1.554 + asm("cmp r0, #0");
1.555 + asm("ldmia sp!, {r0,r3,r12}");
1.556 + asm("moveq r0, #0");
1.557 + __CPOPRET(eq,"r2,r3,r4,");
1.558 +
1.559 + asm("adr lr, 9f");
1.560 + asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.561 + asm("9:");
1.562 + __POPRET("r2,r3,r4,");
1.563 + }
1.564 +
1.565 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.566 + {
1.567 + // fall through to OutFilteredNX...
1.568 + }
1.569 +
1.570 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize)
1.571 + {
1.572 + asm("ldr r12, __BTraceData");
1.573 + asm("stmdb sp!, {r2,r3,r4,lr}");
1.574 + asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.575 + asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.576 + asm("cmp r2, #0");
1.577 + asm("moveq r0, #0");
1.578 + __CPOPRET(eq,"r2,r3,r4,");
1.579 +
1.580 + asm("stmdb sp!, {r0,r1,r3,r12}");
1.581 + asm("mov r0, r12");
1.582 + asm("bl btrace_check_filter2");
1.583 + asm("cmp r0, #0");
1.584 + asm("ldmia sp!, {r0,r1,r3,r12}");
1.585 + asm("moveq r0, #0");
1.586 + __CPOPRET(eq,"r2,r3,r4,");
1.587 +
1.588 + asm("ldr r4, [sp, #16]"); // r4 = aDataSize
1.589 + asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.590 + asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray));
1.591 + asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8))));
1.592 + asm("add r0, r0, r4");
1.593 + asm("subs r4, r4, #1");
1.594 + asm("ldrhs lr, [r3]"); // get first word of aData is aDataSize!=0
1.595 + asm("mov r3, r1"); // r3 = a1 (ready for call to handler)
1.596 + asm("cmp r4, #4");
1.597 + asm("strlo lr, [sp, #4]"); // replace aData with first word if aDataSize is 1-4
1.598 +
1.599 + asm("mov lr, pc");
1.600 + asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler));
1.601 + __POPRET("r2,r3,r4,");
1.602 + }
1.603 +
1.604 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize)
1.605 + {
1.606 + asm("ldr r12, __BTraceData");
1.607 + asm("stmdb sp!, {r4,lr}");
1.608 + asm("and r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8))));
1.609 + asm("ldrb r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8)));
1.610 + asm("cmp r4, #0");
1.611 + asm("moveq r0, #0");
1.612 + __CPOPRET(eq,"r4,");
1.613 +
1.614 + asm("stmdb sp!, {r0-r3,r4,lr}");
1.615 + asm("mov r0, r12");
1.616 + asm("bl btrace_check_filter2");
1.617 + asm("cmp r0, #0");
1.618 + asm("mov r12, r2");
1.619 + asm("ldmia sp!, {r0-r3,r4,lr}");
1.620 + asm("moveq r0, #0");
1.621 + __CPOPRET(eq,"r4,");
1.622 +
1.623 + asm("stmdb sp!, {r12,lr}");
1.624 + asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm);
1.625 + asm("add sp, sp, #8");
1.626 + __POPRET("r4,");
1.627 + }
1.628 +
1.629 +
1.630 +__NAKED__ EXPORT_C TBool BTrace::OutFilteredPcFormatBig(TUint32 a0, TUint32 aModuleUid, TUint32 aPc, TUint16 aFormatId, const TAny* aData, TInt aDataSize)
1.631 + {
1.632 + asm("mov r0, #0"); //kernel side not implemented yet
1.633 + }
1.634 +
1.635 +/******************************************************************************/
1.636 +
1.637 +/** Save all the ARM registers
1.638 +
1.639 +@internalTechnology
1.640 +*/
1.641 +__NAKED__ void Arm::SaveState(SFullArmRegSet&)
1.642 + {
1.643 + asm("stmia r0, {r0-r14}^ "); // save R0-R7, R8_usr-R14_usr
1.644 + asm("str lr, [r0, #60]! "); // save R15
1.645 + asm("mrs r1, cpsr ");
1.646 + asm("str r1, [r0, #4]! "); // save CPSR
1.647 + asm("bic r2, r1, #0x1f ");
1.648 + asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off
1.649 + asm("msr cpsr, r2 ");
1.650 + asm("stmib r0!, {r13,r14} "); // save R13_svc, R14_svc
1.651 + asm("mrs r3, spsr ");
1.652 + asm("str r3, [r0, #4]! "); // save SPSR_svc
1.653 + asm("bic r2, r1, #0x1f ");
1.654 + asm("orr r2, r2, #0xd7 "); // mode_abt, all interrupts off
1.655 + asm("msr cpsr, r2 ");
1.656 + asm("stmib r0!, {r13,r14} "); // save R13_abt, R14_abt
1.657 + asm("mrs r3, spsr ");
1.658 + asm("str r3, [r0, #4]! "); // save SPSR_abt
1.659 + asm("bic r2, r1, #0x1f ");
1.660 + asm("orr r2, r2, #0xdb "); // mode_und, all interrupts off
1.661 + asm("msr cpsr, r2 ");
1.662 + asm("stmib r0!, {r13,r14} "); // save R13_und, R14_und
1.663 + asm("mrs r3, spsr ");
1.664 + asm("str r3, [r0, #4]! "); // save SPSR_und
1.665 + asm("bic r2, r1, #0x1f ");
1.666 + asm("orr r2, r2, #0xd2 "); // mode_irq, all interrupts off
1.667 + asm("msr cpsr, r2 ");
1.668 + asm("stmib r0!, {r13,r14} "); // save R13_irq, R14_irq
1.669 + asm("mrs r3, spsr ");
1.670 + asm("str r3, [r0, #4]! "); // save SPSR_irq
1.671 + asm("bic r2, r1, #0x1f ");
1.672 + asm("orr r2, r2, #0xd1 "); // mode_fiq, all interrupts off
1.673 + asm("msr cpsr, r2 ");
1.674 + asm("stmib r0!, {r8-r14} "); // save R8_fiq ... R14_fiq
1.675 + asm("mrs r3, spsr ");
1.676 + asm("str r3, [r0, #4]! "); // save SPSR_fiq
1.677 + asm("bic r2, r1, #0x1f ");
1.678 + asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off
1.679 + asm("msr cpsr, r2 ");
1.680 +
1.681 + asm("mov r4, #0 ");
1.682 + asm("mov r5, #0 ");
1.683 + asm("mov r6, #0 ");
1.684 + asm("mov r7, #0 ");
1.685 + asm("mov r8, #0 ");
1.686 + asm("mov r9, #0 ");
1.687 + asm("mov r10, #0 ");
1.688 + asm("mov r11, #0 ");
1.689 +
1.690 + // monitor mode - skip for now
1.691 + asm("mov r3, #0 ");
1.692 + asm("stmib r0!, {r4-r6} "); // R13_mon, R14_mon, SPSR_mon
1.693 +
1.694 + // zero spare words
1.695 + asm("mov r3, #0 ");
1.696 + asm("stmib r0!, {r4-r11} ");
1.697 + asm("add r0, r0, #4 "); // r0 = &a.iA
1.698 +
1.699 +#ifdef __CPU_ARMV7
1.700 + asm("mrc p14, 6, r3, c1, c0, 0 ");
1.701 +#else
1.702 + asm("mov r3, #0 ");
1.703 +#endif
1.704 + asm("str r3, [r0], #4 "); // TEEHBR
1.705 +#ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
1.706 + GET_CAR(,r3);
1.707 +#else
1.708 + asm("mov r3, #0 ");
1.709 +#endif
1.710 + asm("str r3, [r0], #4 "); // CPACR
1.711 +
1.712 + // skip SCR, SDER, NSACR, PMCR, MVBAR for now
1.713 + asm("mov r3, #0 ");
1.714 + asm("stmia r0!, {r4-r8} "); // SCR, SDER, NSACR, PMCR, MVBAR
1.715 +
1.716 + // zero spare words
1.717 + asm("mov r3, #0 ");
1.718 + asm("stmia r0!, {r3-r11} "); // r0 = &a.iB[0]
1.719 +
1.720 + // just fill in iB[0]
1.721 +#ifdef __CPU_HAS_MMU
1.722 + asm("mrc p15, 0, r3, c1, c0, 0 ");
1.723 + asm("str r3, [r0], #4 "); // SCTLR
1.724 +#ifdef __CPU_HAS_ACTLR
1.725 + asm("mrc p15, 0, r3, c1, c0, 1 ");
1.726 +#else
1.727 + asm("mov r3, #0 ");
1.728 +#endif
1.729 + asm("str r3, [r0], #4 "); // ACTLR
1.730 + asm("mrc p15, 0, r3, c2, c0, 0 ");
1.731 + asm("str r3, [r0], #4 "); // TTBR0
1.732 +#ifdef __CPU_HAS_TTBR1
1.733 + asm("mrc p15, 0, r2, c2, c0, 1 ");
1.734 + asm("mrc p15, 0, r3, c2, c0, 2 ");
1.735 +#else
1.736 + asm("mov r2, #0 ");
1.737 + asm("mov r3, #0 ");
1.738 +#endif
1.739 + asm("stmia r0!, {r2,r3} "); // TTBR1, TTBCR
1.740 + asm("mrc p15, 0, r3, c3, c0, 0 ");
1.741 + asm("str r3, [r0], #4 "); // DACR
1.742 +#ifdef __CPU_MEMORY_TYPE_REMAPPING
1.743 + asm("mrc p15, 0, r2, c10, c2, 0 ");
1.744 + asm("mrc p15, 0, r3, c10, c2, 1 ");
1.745 +#else
1.746 + asm("mov r2, #0 ");
1.747 + asm("mov r3, #0 ");
1.748 +#endif
1.749 + asm("stmia r0!, {r2,r3} "); // PRRR, NMRR
1.750 +#ifdef __CPU_ARMV7
1.751 + asm("mrc p15, 0, r3, c12, c0, 0 ");
1.752 +#else
1.753 + asm("mov r3, #0 ");
1.754 +#endif
1.755 + asm("str r3, [r0], #4 "); // VBAR
1.756 +#if defined(__CPU_SA1) || defined(__CPU_ARM920T) || defined(__CPU_ARM925T) || defined(__CPU_ARMV5T) || defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
1.757 + asm("mrc p15, 0, r3, c13, c0, 0 ");
1.758 +#else
1.759 + asm("mov r3, #0 ");
1.760 +#endif
1.761 + asm("str r3, [r0], #4 "); // FCSEIDR
1.762 +#if defined(__CPU_ARMV6) || defined(__CPU_ARMV7)
1.763 + asm("mrc p15, 0, r3, c13, c0, 1 ");
1.764 +#else
1.765 + asm("mov r3, #0 ");
1.766 +#endif
1.767 + asm("str r3, [r0], #4 "); // CONTEXTIDR
1.768 +#ifdef __CPU_HAS_CP15_THREAD_ID_REG
1.769 + GET_RWRW_TID(,r2);
1.770 + GET_RWRO_TID(,r3);
1.771 + GET_RWNO_TID(,r12);
1.772 +#else
1.773 + asm("mov r2, #0 ");
1.774 + asm("mov r3, #0 ");
1.775 + asm("mov r12, #0 ");
1.776 +#endif
1.777 + asm("stmia r0!, {r2,r3,r12} "); // RWRWTID, RWROTID, RWNOTID
1.778 + asm("mrc p15, 0, r2, c5, c0, 0 "); // DFSR
1.779 +#ifdef __CPU_ARM_HAS_SPLIT_FSR
1.780 + asm("mrc p15, 0, r3, c5, c0, 1 "); // IFSR
1.781 +#else
1.782 + asm("mov r3, #0 ");
1.783 +#endif
1.784 + asm("stmia r0!, {r2,r3} "); // DFSR, IFSR
1.785 +#ifdef __CPU_ARMV7
1.786 + asm("mrc p15, 0, r2, c5, c1, 0 "); // ADFSR
1.787 + asm("mrc p15, 0, r3, c5, c1, 1 "); // AIFSR
1.788 +#else
1.789 + asm("mov r2, #0 ");
1.790 + asm("mov r3, #0 ");
1.791 +#endif
1.792 + asm("stmia r0!, {r2,r3} "); // ADFSR, AIFSR
1.793 + asm("mrc p15, 0, r2, c6, c0, 0 "); // DFAR
1.794 +#ifdef __CPU_ARM_HAS_CP15_IFAR
1.795 + asm("mrc p15, 0, r3, c6, c0, 2 "); // IFAR
1.796 +#else
1.797 + asm("mov r3, #0 ");
1.798 +#endif
1.799 + asm("stmia r0!, {r2,r3} "); // DFAR, IFAR
1.800 +
1.801 + // zero spare words
1.802 + asm("stmia r0!, {r4-r7} ");
1.803 + asm("stmia r0!, {r4-r11} ");
1.804 +#else // __CPU_HAS_MMU
1.805 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.806 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.807 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.808 + asm("stmia r0!, {r4-r11} "); // no MMU so zero fill
1.809 +#endif // __CPU_HAS_MMU
1.810 +
1.811 + // zero iB[1]
1.812 + asm("stmia r0!, {r4-r11} ");
1.813 + asm("stmia r0!, {r4-r11} ");
1.814 + asm("stmia r0!, {r4-r11} ");
1.815 + asm("stmia r0!, {r4-r11} "); // r0 = &a.iMore[0]
1.816 + asm("add r1, r0, #62*8 "); // r1 = &a.iExcCode
1.817 +
1.818 + // Save VFP state
1.819 + // Save order:
1.820 + // FPEXC FPSCR
1.821 + // VFPv2 ONLY: FPINST FPINST2
1.822 + // D0-D3 D4-D7 D8-D11 D12-D15
1.823 + // VFPv3 ONLY: D16-D19 D20-D23 D24-D27 D28-D31
1.824 +#ifdef __CPU_HAS_VFP
1.825 + GET_CAR(,r2);
1.826 + asm("bic r2, r2, #0x00f00000 ");
1.827 +#ifdef __VFP_V3
1.828 + asm("bic r2, r2, #0xc0000000 "); // mask off ASEDIS, D32DIS
1.829 +#endif
1.830 + asm("orr r2, r2, #0x00500000 "); // enable privileged access to CP10, CP11
1.831 + SET_CAR(,r2);
1.832 + VFP_FMRX(,2,VFP_XREG_FPEXC); // r2=FPEXC
1.833 + asm("orr r3, r2, #%a0" : : "i" ((TInt)VFP_FPEXC_EN));
1.834 + VFP_FMXR(,VFP_XREG_FPEXC,3); // enable VFP
1.835 + __DATA_SYNC_BARRIER__(r4);
1.836 + __INST_SYNC_BARRIER__(r4);
1.837 + VFP_FMRX(,3,VFP_XREG_FPSCR); // r3=FPSCR
1.838 + asm("stmia r0!, {r2,r3} "); //
1.839 +#ifdef __VFP_V3
1.840 + VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15
1.841 + VFP_FMRX(,3,VFP_XREG_MVFR0);
1.842 + asm("tst r3, #%a0" : : "i" ((TInt)VFP_MVFR0_ASIMD32)); // Check to see if all 32 Advanced SIMD registers are present
1.843 + VFP_FSTMIADW(CC_NE,0,16,16); // if so then save D16 - D31 (don't need to check CPACR.D32DIS as it is cleared above)
1.844 +#else
1.845 + VFP_FMRX(,2,VFP_XREG_FPINST);
1.846 + VFP_FMRX(,3,VFP_XREG_FPINST2);
1.847 + asm("stmia r0!, {r2,r3} "); // FPINST, FPINST2
1.848 + VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15
1.849 +#endif
1.850 +#endif // __CPU_HAS_VFP
1.851 + asm("1: ");
1.852 + asm("cmp r0, r1 ");
1.853 + asm("strlo r4, [r0], #4 "); // clear up to end of iMore[61]
1.854 + asm("blo 1b ");
1.855 + asm("mov r1, #%a0" : : "i" ((TInt)KMaxTInt));
1.856 + asm("stmia r0!, {r1,r5-r7} "); // iExcCode=KMaxTInt, iCrashArgs[0...2]=0
1.857 + asm("sub r0, r0, #1024 "); // r0 = &a
1.858 +#ifdef __CPU_HAS_VFP
1.859 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iMore[0]));
1.860 + VFP_FMXR(,VFP_XREG_FPEXC,2); // restore FPEXC
1.861 + __DATA_SYNC_BARRIER__(r4);
1.862 + __INST_SYNC_BARRIER__(r4);
1.863 + asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iA.iCPACR));
1.864 + SET_CAR(,r2); // restore CPACR
1.865 +#endif
1.866 + asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
1.867 + asm("orr r1, r1, #0xC0 "); // interrupts off
1.868 + asm("msr cpsr, r1 "); // restore CPSR with interrupts off
1.869 + asm("ldmia r0, {r0-r11} "); // restore R4-R11
1.870 + __JUMP(,lr);
1.871 + }
1.872 +
1.873 +
1.874 +/** Update the saved ARM registers with information from an exception
1.875 +
1.876 +@internalTechnology
1.877 +*/
1.878 +__NAKED__ void Arm::UpdateState(SFullArmRegSet&, TArmExcInfo&)
1.879 + {
1.880 + asm("ldmia r1!, {r2,r3,r12} ");
1.881 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags));
1.882 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode));
1.883 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13Svc));
1.884 + asm("ldmia r1!, {r2,r3,r12} ");
1.885 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR4));
1.886 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR5));
1.887 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR6));
1.888 + asm("ldmia r1!, {r2,r3,r12} ");
1.889 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR7));
1.890 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR8));
1.891 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR9));
1.892 + asm("ldmia r1!, {r2,r3,r12} ");
1.893 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR10));
1.894 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR11));
1.895 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14Svc));
1.896 + asm("ldr r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode));
1.897 + asm("ldmia r1!, {r2,r3} "); // r2=iFaultAddress, r3=iFaultStatus
1.898 + asm("cmp r12, #%a0 " : : "i" ((TInt)EArmExceptionPrefetchAbort));
1.899 + asm("streq r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFAR));
1.900 + asm("strne r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFAR));
1.901 + asm("streq r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFSR));
1.902 + asm("strne r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFSR));
1.903 + asm("ldmia r1!, {r2,r3,r12} ");
1.904 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iSpsrSvc));
1.905 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13));
1.906 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14));
1.907 + asm("ldmia r1!, {r2,r3,r12} ");
1.908 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR0));
1.909 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR1));
1.910 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR2));
1.911 + asm("ldmia r1!, {r2,r3,r12} ");
1.912 + asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR3));
1.913 + asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR12));
1.914 + asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR15));
1.915 + __JUMP(,lr);
1.916 + }
1.917 +
1.918 +
1.919 +/** Get a pointer to a stored integer register, accounting for registers which
1.920 + are banked across modes.
1.921 +
1.922 +@param a Pointer to saved register block
1.923 +@param aRegNum Number of register required, 0-15 or -1 (indicates SPSR)
1.924 +@param aMode Bottom 5 bits indicate which processor mode
1.925 + Other bits of aMode are ignored
1.926 +@return Pointer to the required saved register value
1.927 +
1.928 +@internalTechnology
1.929 +*/
1.930 +__NAKED__ TArmReg* Arm::Reg(SFullArmRegSet& /*a*/, TInt /*aRegNum*/, TArmReg /*aMode*/)
1.931 + {
1.932 + asm("cmp r1, #8 "); // register number < 8 ?
1.933 + asm("addlo r0, r0, r1, lsl #2 "); // register R0-R7 are not banked
1.934 + asm("blo 0f ");
1.935 + asm("cmp r1, #15 "); // register number = 15 ?
1.936 + asm("addeq r0, r0, r1, lsl #2 "); // register R15 not banked
1.937 + asm("movgt r0, #0 "); // no registers > 15
1.938 + asm("bge 0f ");
1.939 + asm("cmn r1, #1 ");
1.940 + asm("movlt r0, #0 "); // no registers < -1
1.941 + asm("blt 0f ");
1.942 + asm("and r12, r2, #0x1F ");
1.943 + asm("cmp r12, #0x11 "); // mode_fiq?
1.944 + asm("beq 1f "); // skip if it is
1.945 + asm("cmp r1, #13 ");
1.946 + asm("addlo r0, r0, r1, lsl #2 "); // register R8-R12 are only banked in mode_fiq
1.947 + asm("blo 0f ");
1.948 + asm("cmp r12, #0x10 "); // mode_usr ?
1.949 + asm("cmpne r12, #0x1F "); // if not, mode_sys ?
1.950 + asm("bne 2f "); // skip if neither
1.951 + asm("cmp r1, #16 ");
1.952 + asm("addlo r0, r0, r1, lsl #2 "); // handle R13_usr, R14_usr
1.953 + asm("movhs r0, #0 "); // no SPSR in mode_usr or mode_sys
1.954 + asm("blo 0f ");
1.955 + asm("1: "); // mode_fiq, regnum = 8-12
1.956 + asm("2: "); // exception mode, regnum not 0-12 or 15
1.957 + asm("cmn r1, #1 "); // regnum = -1 ?
1.958 + asm("moveq r1, #15 "); // if so, change to 15
1.959 + asm("sub r1, r1, #13 ");
1.960 + asm("add r0, r0, r1, lsl #2 "); // add 0 for R13, 4 for R14, 8 for SPSR
1.961 + asm("cmp r12, #0x16 ");
1.962 + asm("addeq r0, r0, #12 "); // if mon, add offset from R13Fiq to R13Mon
1.963 + asm("cmpne r12, #0x11 ");
1.964 + asm("addeq r0, r0, #32 "); // if valid but not svc/abt/und/irq, add offset from R13Irq to R13Fiq
1.965 + asm("cmpne r12, #0x12 ");
1.966 + asm("addeq r0, r0, #12 "); // if valid but not svc/abt/und, add offset from R13Und to R13Irq
1.967 + asm("cmpne r12, #0x1b ");
1.968 + asm("addeq r0, r0, #12 "); // if valid but not svc/abt, add offset from R13Abt to R13Und
1.969 + asm("cmpne r12, #0x17 ");
1.970 + asm("addeq r0, r0, #12 "); // if valid but not svc, add offset from R13Svc to R13Abt
1.971 + asm("cmpne r12, #0x13 ");
1.972 + asm("addeq r0, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iN.iR13Svc)); // if valid mode add offset to R13Svc
1.973 + asm("movne r0, #0 ");
1.974 + asm("0: ");
1.975 + __JUMP(,lr);
1.976 + }
1.977 +
1.978 +
1.979 +/** Restore all the ARM registers
1.980 +
1.981 +@internalTechnology
1.982 +*/
1.983 +__NAKED__ void Arm::RestoreState(SFullArmRegSet&)
1.984 + {
1.985 + }
1.986 +
1.987 +
1.988 +
1.989 +
1.990 +