1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kernel/eka/memmodel/epoc/multiple/arm/xmonitor.cia	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,43 @@
     1.4 +// Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +// e32\memmodel\epoc\multiple\arm\xmonitor.cia
    1.18 +// Kernel crash debugger - ARM specific portion
    1.19 +// 
    1.20 +//
    1.21 +
    1.22 +#include <kernel/monitor.h>
    1.23 +#include "memmodel.h"
    1.24 +#include <mmboot.h>
    1.25 +
    1.26 +__NAKED__ TInt MapProcess(DMemModelProcess* aProcess, TBool)
    1.27 +	{	
    1.28 +	asm("mrc p15, 0, r3, c2, c0, 0 ");		// get TTBR0
    1.29 +	asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess, iLocalPageDir));
    1.30 +	asm("and r3, r3, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask));	// r3 = page table cache attributes
    1.31 +	asm("mcr p15, 0, r2, c7, c10, 4 ");	// drain write buffer before changing MMU registers (see ARMv6 specs)
    1.32 +	asm("orr r2, r2, r3 ");					// r2 = new TTBR0 value
    1.33 +	UPDATE_PW_CACHING_ATTRIBUTES(,r2);		// ERRATUM 1136_317041
    1.34 +	asm("mcr p15, 0, r2, c2, c0, 0 ");		// set TTBR0 - no TLB flush required due to ASID
    1.35 +
    1.36 +	asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess, iOsAsid));
    1.37 +	asm("mcr p15, 0, r0, c13, c0, 1 ");		// set ASID
    1.38 +
    1.39 +#if defined(__CPU_ARM11MP__)
    1.40 +	// On other platforms, tha ASID change above has already flushed the branch prediction buffers 
    1.41 +	asm("mcr p15, 0, r0, c7, c5, 6 ");	// flush BTAC
    1.42 +#endif
    1.43 +	
    1.44 +	asm("mov r0, #0");
    1.45 +	__JUMP(,lr);
    1.46 +	}