1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkernsmp/x86/nk_plat.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,192 @@
1.4 +// Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\nkernsmp\x86\nk_plat.h
1.18 +//
1.19 +// WARNING: This file contains some APIs which are internal and are subject
1.20 +// to change without notice. Such APIs should therefore not be used
1.21 +// outside the Kernel and Hardware Services package.
1.22 +//
1.23 +
1.24 +/**
1.25 + @file
1.26 + @internalComponent
1.27 +*/
1.28 +
1.29 +#ifndef __NK_X86_H__
1.30 +#define __NK_X86_H__
1.31 +#include <nk_cpu.h>
1.32 +
1.33 +// TSubScheduler member data
1.34 +#define i_IrqCount iExtras[9] // count of interrupts handled
1.35 +#define i_ExcInfo iExtras[10] // pointer to exception info for crash debugger
1.36 +#define i_CrashState iExtras[11] // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted
1.37 +#define i_APICID iExtras[12] // Local APIC ID for this CPU (starts at -1)
1.38 +#define i_IrqNestCount iExtras[13] // IRQ nest count for this CPU (starts at -1)
1.39 +#define i_IrqStackTop iExtras[14] // Top of IRQ stack for this CPU
1.40 +#define i_Tss iExtras[15] // Address of TSS for this CPU
1.41 +#define i_TimerMultF iExtras[16] // Timer frequency / Max Timer frequency * 2^32
1.42 +#define i_TimerMultI iExtras[17] // Max Timer frequency / Timer frequency * 2^24
1.43 +#define i_CpuMult iExtras[18] // CPU frequency / Max CPU frequency * 2^32
1.44 +#define i_TimestampOffset iExtras[20] // 64 bit value to add to CPU TSC to give NKern::Timestamp()
1.45 +#define i_TimestampOffsetL iExtras[20] //
1.46 +#define i_TimestampOffsetH iExtras[21] //
1.47 +
1.48 +// TScheduler member data
1.49 +#define i_TimerMax iExtras[16] // Maximum per-CPU timer frequency (after prescaling)
1.50 +
1.51 +#define CRASH_IPI_VECTOR 0x27
1.52 +#define RESCHED_IPI_VECTOR 0x28
1.53 +#define TIMESLICE_VECTOR 0x29
1.54 +#define GENERIC_IPI_VECTOR 0x2A
1.55 +#define TRANSFERRED_IRQ_VECTOR 0x2E
1.56 +#define SPURIOUS_INTERRUPT_VECTOR 0x2F
1.57 +
1.58 +extern "C" TSubScheduler* SubSchedulerLookupTable[256]; // look up subscheduler from APIC ID
1.59 +
1.60 +#define IRQ_STACK_SIZE 1024
1.61 +
1.62 +//#define __SCHEDULER_MACHINE_CODED__
1.63 +//#define __DFC_MACHINE_CODED__
1.64 +//#define __MSTIM_MACHINE_CODED__
1.65 +//#define __PRI_LIST_MACHINE_CODED__
1.66 +//#define __FAST_SEM_MACHINE_CODED__
1.67 +//#define __FAST_MUTEX_MACHINE_CODED__
1.68 +
1.69 +class TX86RegSet;
1.70 +class NThread : public NThreadBase
1.71 + {
1.72 +public:
1.73 + TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial);
1.74 + inline void Stillborn()
1.75 + {}
1.76 + void GetUserContext(TX86RegSet& aContext, TUint32& aAvailRegMask);
1.77 + void SetUserContext(const TX86RegSet& aContext, TUint32& aRegMask);
1.78 + void GetSystemContext(TX86RegSet& aContext, TUint32& aAvailRegMask);
1.79 + void CompleteContextSave();
1.80 +public:
1.81 + TUint64 iCoprocessorState[64]; // state of FPU, SSE, SSE2
1.82 + };
1.83 +
1.84 +__ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7));
1.85 +
1.86 +
1.87 +// Positions of registers on stack, relative to saved SP
1.88 +struct SThreadReschedStack
1.89 + {
1.90 + TUint32 iCR0;
1.91 + TUint32 iReschedFlag;
1.92 + TUint32 iEip;
1.93 + TUint32 iReason;
1.94 + };
1.95 +
1.96 +// Registers pushed on stack for all exceptions other than slow exec
1.97 +struct SThreadExcStack
1.98 + {
1.99 + TUint32 iEcx;
1.100 + TUint32 iEdx;
1.101 + TUint32 iEbx;
1.102 + TUint32 iEsi;
1.103 + TUint32 iEdi;
1.104 + TUint32 iEbp;
1.105 + TUint32 iEax;
1.106 + TUint32 iDs;
1.107 + TUint32 iEs;
1.108 + TUint32 iFs;
1.109 + TUint32 iGs;
1.110 + TUint32 iVector;
1.111 + TUint32 iError;
1.112 + TUint32 iEip;
1.113 + TUint32 iCs;
1.114 + TUint32 iEflags;
1.115 + TUint32 iEsp3; // only if iCs does not indicate CPL=0
1.116 + TUint32 iSs3; // only if iCs does not indicate CPL=0
1.117 + };
1.118 +
1.119 +// Registers pushed on stack for slow exec
1.120 +struct SThreadSlowExecStack
1.121 + {
1.122 + TUint32 iEcx;
1.123 + TUint32 iEdx;
1.124 + TUint32 iEbx;
1.125 + TUint32 iEsi;
1.126 + TUint32 iEdi;
1.127 + TUint32 iEbp;
1.128 + TUint32 iEax;
1.129 + TUint32 iDs;
1.130 + TUint32 iEs;
1.131 + TUint32 iFs;
1.132 + TUint32 iGs;
1.133 + TUint32 iArgs[8]; // space for extra arguments copied from user side
1.134 + TUint32 iVector;
1.135 + TUint32 iError;
1.136 + TUint32 iEip;
1.137 + TUint32 iCs;
1.138 + TUint32 iEflags;
1.139 + TUint32 iEsp3; // only if iCs does not indicate CPL=0
1.140 + TUint32 iSs3; // only if iCs does not indicate CPL=0
1.141 + };
1.142 +
1.143 +// Top of stack after thread creation for threads with parameter block passed
1.144 +// by value.
1.145 +struct SThreadStackStub
1.146 + {
1.147 + enum {EVector=0xffffffffu};
1.148 + TLinAddr iPBlock; // pointer to parameter block
1.149 + TUint32 iVector;
1.150 + TUint32 iError;
1.151 + TUint32 iEip;
1.152 + TUint32 iCs;
1.153 + TUint32 iEflags;
1.154 + };
1.155 +
1.156 +// Stack structure at thread creation either at top of stack (if parameter block
1.157 +// passed by reference) or below parameter block if passed by value.
1.158 +struct SThreadInitStack
1.159 + {
1.160 + enum {EVector=0xfffffffeu};
1.161 + SThreadReschedStack iR;
1.162 + SThreadExcStack iX;
1.163 + };
1.164 +
1.165 +
1.166 +extern "C" {
1.167 +GLREF_D TLinAddr X86_IrqHandler;
1.168 +GLREF_D SCpuIdleHandler CpuIdleHandler;
1.169 +GLREF_D TUint32 X86_CPUID;
1.170 +GLREF_D TBool X86_UseGlobalPTEs;
1.171 +GLREF_D TUint64 DefaultCoprocessorState[64];
1.172 +}
1.173 +
1.174 +/** Ensure the ordering of explicit memory writes
1.175 +
1.176 + On x86 this is a no-op
1.177 +*/
1.178 +#define wmb()
1.179 +#define smp_wmb() wmb()
1.180 +
1.181 +/** Ensure the ordering of explicit memory accesses
1.182 +
1.183 + On x86 any instruction with the LOCK prefix does this
1.184 +*/
1.185 +#ifdef __GCC32__
1.186 +#define mb() __asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory")
1.187 +#else
1.188 +#define mb() do { _asm lock add dword ptr [esp], 0 } while (0)
1.189 +#endif
1.190 +#define smp_mb() mb()
1.191 +
1.192 +
1.193 +
1.194 +// End of file
1.195 +#endif