1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkernsmp/arm/arm_tmr.h	Fri Jun 15 03:10:57 2012 +0200
     1.3 @@ -0,0 +1,84 @@
     1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
     1.5 +// All rights reserved.
     1.6 +// This component and the accompanying materials are made available
     1.7 +// under the terms of the License "Eclipse Public License v1.0"
     1.8 +// which accompanies this distribution, and is available
     1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
    1.10 +//
    1.11 +// Initial Contributors:
    1.12 +// Nokia Corporation - initial contribution.
    1.13 +//
    1.14 +// Contributors:
    1.15 +//
    1.16 +// Description:
    1.17 +// e32\include\nkernsmp\arm\arm_tmr.h
    1.18 +// 
    1.19 +// WARNING: This file contains some APIs which are internal and are subject
    1.20 +//          to change without notice. Such APIs should therefore not be used
    1.21 +//          outside the Kernel and Hardware Services package.
    1.22 +//
    1.23 +
    1.24 +#ifndef	__ARM_TMR_H__
    1.25 +#define	__ARM_TMR_H__
    1.26 +#include <e32def.h>
    1.27 +
    1.28 +#ifdef	__STANDALONE_NANOKERNEL__
    1.29 +#undef	__IN_KERNEL__
    1.30 +#define	__IN_KERNEL__
    1.31 +#endif
    1.32 +
    1.33 +#if !defined(__CPU_ARM11MP__) && !defined(__CPU_CORTEX_A9__)
    1.34 +#error	Unknown local timer
    1.35 +#endif
    1.36 +
    1.37 +// Local timer looks the same on ARM11MP and Cortex A9
    1.38 +struct ArmLocalTimer
    1.39 +	{
    1.40 +	volatile TUint32	iTimerLoad;				// 00 Timer reload value (write also writes counter)
    1.41 +	volatile TUint32	iTimerCount;			// 04 Timer instantaneous count value
    1.42 +	volatile TUint32	iTimerCtrl;				// 08 Timer control register
    1.43 +	volatile TUint32	iTimerIntStatus;		// 0C Timer interrupt status register
    1.44 +	volatile TUint32	i_Spare1[4];			// 10 unused
    1.45 +	volatile TUint32	iWatchdogLoad;			// 20 Watchdog reload value (write also writes counter)
    1.46 +	volatile TUint32	iWatchdogCount;			// 24 Watchdog instantaneous count value
    1.47 +	volatile TUint32	iWatchdogCtrl;			// 28 Watchdog control register
    1.48 +	volatile TUint32	iWatchdogIntStatus;		// 2C Watchdog interrupt status register
    1.49 +	volatile TUint32	iWatchdogResetSent;		// 30 Watchdog reset sent register
    1.50 +	volatile TUint32	iWatchdogDisable;		// 34 Watchdog disable register
    1.51 +	volatile TUint32	i_Spare2[50];			// 38 unused
    1.52 +	};
    1.53 +
    1.54 +__ASSERT_COMPILE(sizeof(ArmLocalTimer)==0x100);
    1.55 +
    1.56 +// These bits apply to both timer and watchdog control registers
    1.57 +enum TArmTimerCtrl
    1.58 +	{
    1.59 +	E_ArmTmrCtrl_Enable			=1u,		// when set, timer counts down
    1.60 +	E_ArmTmrCtrl_Reload			=2u,		// when set, timer reloads on reaching zero
    1.61 +	E_ArmTmrCtrl_IntEn			=4u,		// when set enables timer interrupt
    1.62 +	E_ArmTmrCtrl_WD				=8u,		// set when in watchdog mode (watchdog only, can write to 1 but not 0)
    1.63 +	E_ArmTmrCtrl_PrescaleShift	=8u,
    1.64 +	E_ArmTmrCtrl_PrescaleMask	=0xff00u,	// bits 8-15 = prescale value - divides by (P+1)
    1.65 +											// input to prescaler is PERIPHCLK (=CPUCLK/2 on NE1, CPUCLK/N in general, N>=2)
    1.66 +	E_ArmTmrCtrl_Prescale64		=0x3f00u,	// value to prescale by 64 (matches cycle counter prescaler)
    1.67 +	};
    1.68 +
    1.69 +enum TArmTimerIntStatus
    1.70 +	{
    1.71 +	E_ArmTmrIntStatus_Event		=1u			// set when timer counter reaches zero, write 1 to clear
    1.72 +	};
    1.73 +
    1.74 +enum TArmTimerWRS
    1.75 +	{
    1.76 +	E_ArmTmrWRS_ResetSent		=1u			// set if the watchdog caused a reset, write 1 to clear
    1.77 +	};
    1.78 +
    1.79 +enum TArmTimerWDDisable
    1.80 +	{
    1.81 +	E_ArmTmrWDD_1				=0x12345678u,	// to disable watchdog, write this ...
    1.82 +	E_ArmTmrWDD_2				=0x87654321u,	// ... then this with no intervening writes
    1.83 +	};
    1.84 +
    1.85 +
    1.86 +
    1.87 +#endif	// 	__ARM_TMR_H__