1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkernsmp/arm/arm_scu.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,155 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\nkernsmp\arm\arm_scu.h
1.18 +// Register definitions for ARM Snoop Control Unit
1.19 +//
1.20 +// WARNING: This file contains some APIs which are internal and are subject
1.21 +// to change without notice. Such APIs should therefore not be used
1.22 +// outside the Kernel and Hardware Services package.
1.23 +//
1.24 +
1.25 +#ifndef __ARM_SCU_H__
1.26 +#define __ARM_SCU_H__
1.27 +#include <e32def.h>
1.28 +
1.29 +#ifdef __STANDALONE_NANOKERNEL__
1.30 +#undef __IN_KERNEL__
1.31 +#define __IN_KERNEL__
1.32 +#endif
1.33 +
1.34 +#if defined(__CPU_ARM11MP__)
1.35 +struct ArmScu
1.36 + {
1.37 + volatile TUint32 iCtrl; // 00 Control register
1.38 + volatile TUint32 iConfig; // 04 Configuration register (RO)
1.39 + volatile TUint32 iCpuStatus; // 08 SCU CPU Status register
1.40 + volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO)
1.41 + volatile TUint32 iPMCtrl; // 10 Performance Monitor Control register
1.42 + volatile TUint32 iMonitorEvents0; // 14 Monitor Counter Events 0
1.43 + volatile TUint32 iMonitorEvents1; // 18 Monitor Counter Events 1
1.44 + volatile TUint32 iMonitorCount0; // 1C Monitor Counter 0
1.45 + volatile TUint32 iMonitorCount1; // 20 Monitor Counter 1
1.46 + volatile TUint32 iMonitorCount2; // 24 Monitor Counter 2
1.47 + volatile TUint32 iMonitorCount3; // 28 Monitor Counter 3
1.48 + volatile TUint32 iMonitorCount4; // 2C Monitor Counter 4
1.49 + volatile TUint32 iMonitorCount5; // 30 Monitor Counter 5
1.50 + volatile TUint32 iMonitorCount6; // 34 Monitor Counter 6
1.51 + volatile TUint32 iMonitorCount7; // 38 Monitor Counter 7
1.52 + volatile TUint32 i_Skip_1[49]; // 3C unused
1.53 + };
1.54 +
1.55 +__ASSERT_COMPILE(sizeof(ArmScu)==0x100);
1.56 +
1.57 +enum TArmScuCtrl
1.58 + {
1.59 + E_ArmScuCtrl_Enable =1u, // SCU Enable
1.60 + E_ArmScuCtrl_AccessShift =1u,
1.61 + E_ArmScuCtrl_AccessMask =0x1eu, // bits 1-4 = SCU access control for CPU0-3
1.62 + E_ArmScuCtrl_IIAliasShift =5u,
1.63 + E_ArmScuCtrl_IIAliasMask =0x1e0u, // bits 5-8 = Interrupt Interface Alias enable for CPU0-3
1.64 + E_ArmScuCtrl_PIAliasShift =9u,
1.65 + E_ArmScuCtrl_PIAliasMask =0x1e00u, // bits 9-12 = Peripheral Interface Alias enable for CPU0-3
1.66 + };
1.67 +
1.68 +enum TArmScuPMCR
1.69 + {
1.70 + E_ArmScuPMCR_Enable =1u, // 0=all counters disabled
1.71 + E_ArmScuPMCR_ResetAll =2u, // write 1 resets all counters
1.72 + E_ArmScuPMCR_IntEn0 =0x100u, // Interrupt Enable for MN0
1.73 + E_ArmScuPMCR_IntEn1 =0x200u, // Interrupt Enable for MN1
1.74 + E_ArmScuPMCR_IntEn2 =0x400u, // Interrupt Enable for MN2
1.75 + E_ArmScuPMCR_IntEn3 =0x800u, // Interrupt Enable for MN3
1.76 + E_ArmScuPMCR_IntEn4 =0x1000u, // Interrupt Enable for MN4
1.77 + E_ArmScuPMCR_IntEn5 =0x2000u, // Interrupt Enable for MN5
1.78 + E_ArmScuPMCR_IntEn6 =0x4000u, // Interrupt Enable for MN6
1.79 + E_ArmScuPMCR_IntEn7 =0x8000u, // Interrupt Enable for MN7
1.80 + E_ArmScuPMCR_Ovfw0 =0x10000u, // Overflow Flag for MN0 (write 1 to clear)
1.81 + E_ArmScuPMCR_Ovfw1 =0x20000u, // Overflow Flag for MN1
1.82 + E_ArmScuPMCR_Ovfw2 =0x40000u, // Overflow Flag for MN2
1.83 + E_ArmScuPMCR_Ovfw3 =0x80000u, // Overflow Flag for MN3
1.84 + E_ArmScuPMCR_Ovfw4 =0x100000u, // Overflow Flag for MN4
1.85 + E_ArmScuPMCR_Ovfw5 =0x200000u, // Overflow Flag for MN5
1.86 + E_ArmScuPMCR_Ovfw6 =0x400000u, // Overflow Flag for MN6
1.87 + E_ArmScuPMCR_Ovfw7 =0x800000u, // Overflow Flag for MN7
1.88 + };
1.89 +
1.90 +
1.91 +#elif defined(__CPU_CORTEX_A9__)
1.92 +struct ArmScu
1.93 + {
1.94 + volatile TUint32 iCtrl; // 00 Control register
1.95 + volatile TUint32 iConfig; // 04 Configuration register (RO)
1.96 + volatile TUint32 iCpuStatus; // 08 SCU CPU Power Status register
1.97 + volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO)
1.98 + volatile TUint32 i_Skip_1[12]; // 10-3F unused
1.99 + volatile TUint32 i_FSAR; // 40 Filtering Start Address Register
1.100 + volatile TUint32 i_FEAR; // 44 Filtering End Address Register
1.101 + volatile TUint32 i_Skip_2[2]; // 48-4F unused
1.102 + volatile TUint32 i_SAC; // 50 SCU Access Control Register
1.103 + volatile TUint32 i_SSAC; // 54 SCU Secure Access Control Register
1.104 + volatile TUint32 i_Skip_3[42]; // 58-FF unused
1.105 + };
1.106 +
1.107 +__ASSERT_COMPILE(sizeof(ArmScu)==0x100);
1.108 +
1.109 +enum TArmScuCtrl
1.110 + {
1.111 + E_ArmScuCtrl_Enable =1u, // SCU Enable
1.112 + E_ArmScuCtrl_AFEnable =2u, // SCU Address Filtering Enable
1.113 + E_ArmScuCtrl_ParityEnable =4u, // SCU Parity Enable
1.114 + };
1.115 +
1.116 +enum TArmScuSAC
1.117 + {
1.118 + E_ArmScuSAC_CPU0 =1u, // If set, CPU0 can access SCU registers
1.119 + E_ArmScuSAC_CPU1 =2u, // If set, CPU1 can access SCU registers
1.120 + E_ArmScuSAC_CPU2 =4u, // If set, CPU2 can access SCU registers
1.121 + E_ArmScuSAC_CPU3 =8u, // If set, CPU3 can access SCU registers
1.122 + };
1.123 +
1.124 +enum TArmScuSSAC
1.125 + {
1.126 + E_ArmScuSSAC_CPU0 =1u, // If set, CPU0 can access SCU registers in nonsecure state
1.127 + E_ArmScuSSAC_CPU1 =2u, // If set, CPU1 can access SCU registers in nonsecure state
1.128 + E_ArmScuSSAC_CPU2 =4u, // If set, CPU2 can access SCU registers in nonsecure state
1.129 + E_ArmScuSSAC_CPU3 =8u, // If set, CPU3 can access SCU registers in nonsecure state
1.130 + E_ArmScuSSAC_Timer0 =16u, // If set, CPU0 private timer is accessible in nonsecure state
1.131 + E_ArmScuSSAC_Timer1 =32u, // If set, CPU1 private timer is accessible in nonsecure state
1.132 + E_ArmScuSSAC_Timer2 =64u, // If set, CPU2 private timer is accessible in nonsecure state
1.133 + E_ArmScuSSAC_Timer3 =128u, // If set, CPU3 private timer is accessible in nonsecure state
1.134 + };
1.135 +
1.136 +#else
1.137 +#error Unknown SCU
1.138 +#endif
1.139 +
1.140 +enum TArmScuConfig
1.141 + {
1.142 + E_ArmScuCfg_NCpusMask =3u, // bits0,1 = number of CPUs - 1
1.143 + E_ArmScuCfg_CpuSMPShift =4u,
1.144 + E_ArmScuCfg_CpuSMPMask =0xf0u, // bits4-7 = CPU0-3 SMP mode indicator
1.145 + E_ArmScuCfg_TagShift =8u,
1.146 + E_ArmScuCfg_TagMask =0xff00u, // two bits per CPU, tag RAM size = 16KB<<n (n=0,1,2 n=3 reserved)
1.147 + };
1.148 +
1.149 +// Bits 2n,2n+1 of CPU status refer to CPU n
1.150 +enum TArmScuCPUStatus
1.151 + {
1.152 + E_ArmScuCpuStat_Normal =0u, // normal mode
1.153 + // 1 reserved
1.154 + E_ArmScuCpuStat_Dormant =2u, // dormant mode
1.155 + E_ArmScuCpuStat_PowerDown =3u, // power down mode
1.156 + };
1.157 +
1.158 +#endif // __ARM_SCU_H__