1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkernsmp/arm/arm_gic.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,161 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\nkernsmp\arm\arm_gic.h
1.18 +// Register definitions for ARM Generic Interrupt Controller
1.19 +//
1.20 +// WARNING: This file contains some APIs which are internal and are subject
1.21 +// to change without notice. Such APIs should therefore not be used
1.22 +// outside the Kernel and Hardware Services package.
1.23 +//
1.24 +
1.25 +#ifndef __ARM_GIC_H__
1.26 +#define __ARM_GIC_H__
1.27 +#include <e32def.h>
1.28 +
1.29 +#ifdef __STANDALONE_NANOKERNEL__
1.30 +#undef __IN_KERNEL__
1.31 +#define __IN_KERNEL__
1.32 +#endif
1.33 +
1.34 +enum TGicIntId
1.35 + {
1.36 + E_GicIntId_Soft0 =0, // IDs 0-15 are for software triggered IPIs
1.37 + E_GicIntId_Soft1 =1,
1.38 + E_GicIntId_Soft2 =2,
1.39 + E_GicIntId_Soft3 =3,
1.40 + E_GicIntId_Soft4 =4,
1.41 + E_GicIntId_Soft5 =5,
1.42 + E_GicIntId_Soft6 =6,
1.43 + E_GicIntId_Soft7 =7,
1.44 + E_GicIntId_Soft8 =8,
1.45 + E_GicIntId_Soft9 =9,
1.46 + E_GicIntId_Soft10 =10,
1.47 + E_GicIntId_Soft11 =11,
1.48 + E_GicIntId_Soft12 =12,
1.49 + E_GicIntId_Soft13 =13,
1.50 + E_GicIntId_Soft14 =14,
1.51 + E_GicIntId_Soft15 =15,
1.52 +
1.53 + E_GicIntId_Private0 =16, // IDs 16-31 are for private peripherals
1.54 + E_GicIntId_Private1 =17,
1.55 + E_GicIntId_Private2 =18,
1.56 + E_GicIntId_Private3 =19,
1.57 + E_GicIntId_Private4 =20,
1.58 + E_GicIntId_Private5 =21,
1.59 + E_GicIntId_Private6 =22,
1.60 + E_GicIntId_Private7 =23,
1.61 + E_GicIntId_Private8 =24,
1.62 + E_GicIntId_Private9 =25,
1.63 + E_GicIntId_Private10 =26,
1.64 + E_GicIntId_Private11 =27,
1.65 + E_GicIntId_Private12 =28,
1.66 + E_GicIntId_Private13 =29,
1.67 + E_GicIntId_Private14 =30,
1.68 + E_GicIntId_Private15 =31,
1.69 +
1.70 + E_GicIntId_Normal0 =32, // first normal interrupt ID
1.71 +
1.72 + E_GicIntId_NormalLast =1019, // last possible normal interrupt ID
1.73 + E_GicIntId_Reserved0 =1020, // reserved interrupt ID
1.74 + E_GicIntId_Reserved1 =1021, // reserved interrupt ID
1.75 + E_GicIntId_NS =1022, // only nonsecure interrupts are serviceable
1.76 + E_GicIntId_Spurious =1023 // no interrupts are serviceable
1.77 + };
1.78 +
1.79 +struct GicDistributor
1.80 + {
1.81 + volatile TUint32 iCtrl; // 000 Control register
1.82 + volatile TUint32 iType; // 004 Type register
1.83 + volatile TUint32 iImpId; // 008 Implementor Identification register (not on MPCore)
1.84 + volatile TUint32 i_Skip_1[29]; // 00C unused
1.85 + volatile TUint32 iIntSec[32]; // 080 Interrupt Security register (not on MPCore) (1 bit per interrupt)
1.86 + volatile TUint32 iEnableSet[32]; // 100 Enable set register (1 bit per interrupt)
1.87 + volatile TUint32 iEnableClear[32]; // 180 Enable clear register (1 bit per interrupt)
1.88 + volatile TUint32 iPendingSet[32]; // 200 Pending set register (1 bit per interrupt)
1.89 + volatile TUint32 iPendingClear[32]; // 280 Pending clear register (1 bit per interrupt)
1.90 + volatile TUint32 iActive[32]; // 300 Active status register (1 bit per interrupt)
1.91 + volatile TUint32 i_Skip_2[32]; // 380 unused
1.92 + volatile TUint32 iPriority[256]; // 400 Interrupt priority register (8 bits per interrupt)
1.93 + volatile TUint32 iTarget[256]; // 800 Interrupt target CPUs register (8 bits per interrupt)
1.94 + volatile TUint32 iConfig[64]; // C00 Interrupt configuration register (2 bits per interrupt)
1.95 + volatile TUint32 iImpDef[64]; // D00 Implementation defined registers
1.96 + // = Interrupt line level on MPCore
1.97 + volatile TUint32 i_Skip_3[64]; // E00 unused
1.98 + volatile TUint32 iSoftIrq; // F00 Software triggered interrupt register
1.99 + volatile TUint32 i_Skip_4[51]; // F04 unused
1.100 + volatile TUint32 iIdent[12]; // FD0 Identification registers
1.101 + };
1.102 +
1.103 +__ASSERT_COMPILE(sizeof(GicDistributor)==0x1000);
1.104 +
1.105 +struct GicCpuIfc
1.106 + {
1.107 + volatile TUint32 iCtrl; // 00 Control register
1.108 + volatile TUint32 iPriMask; // 04 Priority mask register
1.109 + volatile TUint32 iBinaryPoint; // 08 Binary point register
1.110 + volatile TUint32 iAck; // 0C Interrupt acknowledge register
1.111 + volatile TUint32 iEoi; // 10 End of interrupt register
1.112 + volatile TUint32 iRunningPri; // 14 Running priority register
1.113 + volatile TUint32 iHighestPending; // 18 Highest pending interrupt register
1.114 + volatile TUint32 iNSBinaryPoint; // 1C Aliased nonsecure binary point register (not on MPCore)
1.115 + volatile TUint32 i_Skip_1[8]; // 20 unused
1.116 + volatile TUint32 iImpDef[36]; // 40 Implementation defined (not present on MPCore)
1.117 + volatile TUint32 i_Skip_2[11]; // D0 unused
1.118 + volatile TUint32 iImpId; // FC Implementor Identification register (not on MPCore)
1.119 + };
1.120 +
1.121 +__ASSERT_COMPILE(sizeof(GicCpuIfc)==0x100);
1.122 +
1.123 +enum TGicDistCtrl
1.124 + {
1.125 + E_GicDistCtrl_Enable =1, // Enable interrupt distributor
1.126 + };
1.127 +
1.128 +enum TGicDistType
1.129 + {
1.130 + E_GicDistType_ITShift =0u, // bits 0-4 = number of sets of 32 interrupts supported
1.131 + E_GicDistType_ITMask =0x1fu,
1.132 + E_GicDistType_CPUNShift =5u, // bits 5-7 = number of CPUs supported - 1
1.133 + E_GicDistType_CPUNMask =0xe0u,
1.134 + E_GicDistType_Domains =0x400u, // set if two security domains supported
1.135 + E_GicDistType_LSPIShift =11u, // bits 11-15 = number of lockable shared peripheral interrupts
1.136 + E_GicDistType_LSPIMask =0xf800u,
1.137 + };
1.138 +
1.139 +enum TGicDistIntConfig
1.140 + {
1.141 + E_GicDistICfg1N =1u, // if set use 1-N model else use N-N model
1.142 + // peripheral interrupts support only 1-N model, s/w interrupts N-N
1.143 + // 1-N means the interrupt is cleared by the first CPU to accept it
1.144 + E_GicDistICfgEdge =2u, // if set, rising edge triggered, else active high level triggered
1.145 + };
1.146 +
1.147 +enum TGicDistSoftIrqDestType
1.148 + {
1.149 + E_GicDestTypeList =0u, // send to all CPUs in list (bit mask)
1.150 + E_GicDestTypeOthers =1u, // send to all CPUs other than self
1.151 + E_GicDestTypeSelf =2u, // send to self only
1.152 + E_GicDestTypeRsvd =3u
1.153 + };
1.154 +
1.155 +// Compile word to generate IPI
1.156 +// dt = destination type, dl = bit mask of destination CPUs, id = interrupt ID (0-15)
1.157 +#define GIC_SOFT_IRQ_WORD(dt,dl,id) ((TUint32(dt)<<24)|(TUint32(dl)<<16)|(TUint32(id)))
1.158 +
1.159 +#define GIC_IPI_SELF(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeSelf, 0, id)
1.160 +#define GIC_IPI_OTHERS(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeOthers, 0, id)
1.161 +#define GIC_IPI(dl,id) GIC_SOFT_IRQ_WORD(E_GicDestTypeList, dl, id)
1.162 +
1.163 +
1.164 +#endif // __ARM_GIC_H__