1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkern/arm/nk_plat.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,185 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\nkern\arm\nk_plat.h
1.18 +//
1.19 +// WARNING: This file contains some APIs which are internal and are subject
1.20 +// to change without notice. Such APIs should therefore not be used
1.21 +// outside the Kernel and Hardware Services package.
1.22 +//
1.23 +
1.24 +/**
1.25 + @file
1.26 + @internalComponent
1.27 +*/
1.28 +
1.29 +#ifndef __NK_ARM_H__
1.30 +#define __NK_ARM_H__
1.31 +#include <nk_cpu.h>
1.32 +
1.33 +// These macros are intended for Symbian use only.
1.34 +// It may not be possible to build the kernel if any of these macros are undefined
1.35 +#define __SCHEDULER_MACHINE_CODED__
1.36 +#define __DFC_MACHINE_CODED__
1.37 +#define __MSTIM_MACHINE_CODED__
1.38 +#define __PRI_LIST_MACHINE_CODED__
1.39 +#define __FAST_SEM_MACHINE_CODED__
1.40 +#define __FAST_MUTEX_MACHINE_CODED__
1.41 +#define __USER_CONTEXT_TYPE_MACHINE_CODED__
1.42 +#define __CLIENT_REQUEST_MACHINE_CODED__
1.43 +
1.44 +// TScheduler member data
1.45 +#define i_Regs iExtras[14]
1.46 +#define i_ExcInfo iExtras[15] // pointer to exception info for crash debugger
1.47 +
1.48 +const TUint32 KNThreadContextFlagThumbBit0=1;
1.49 +
1.50 +#ifdef __CPU_ARM_USE_DOMAINS
1.51 +#define DOMAIN_STACK_SPACE 4
1.52 +#else
1.53 +#define DOMAIN_STACK_SPACE 0
1.54 +#endif
1.55 +#ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
1.56 +#define CAR_STACK_SPACE 4
1.57 +#else
1.58 +#define CAR_STACK_SPACE 0
1.59 +#endif
1.60 +#ifdef __CPU_HAS_VFP
1.61 +#define VFP_STACK_SPACE 4
1.62 +#else
1.63 +#define VFP_STACK_SPACE 0
1.64 +#endif
1.65 +#ifdef __CPU_HAS_CP15_THREAD_ID_REG
1.66 +#define TID_STACK_SPACE 4
1.67 +#else
1.68 +#define TID_STACK_SPACE 0
1.69 +#endif
1.70 +#ifdef __CPU_SUPPORT_THUMB2EE
1.71 +#define THUMB2EE_STACK_SPACE 4
1.72 +#else
1.73 +#define THUMB2EE_STACK_SPACE 0
1.74 +#endif
1.75 +
1.76 +#define EXTRA_STACK_SPACE (DOMAIN_STACK_SPACE+CAR_STACK_SPACE+VFP_STACK_SPACE+TID_STACK_SPACE+THUMB2EE_STACK_SPACE)
1.77 +
1.78 +#ifdef __INCLUDE_REG_OFFSETS__
1.79 +// Positions of registers on stack, relative to saved SP
1.80 +#define EXTRA_WORDS (EXTRA_STACK_SPACE/4)
1.81 +
1.82 +#ifdef __CPU_HAS_VFP
1.83 +#define SP_FPEXC ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE)/4)
1.84 +#endif
1.85 +#ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
1.86 +#define SP_CAR ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE)/4)
1.87 +#endif
1.88 +#ifdef __CPU_ARM_USE_DOMAINS
1.89 +#define SP_DACR ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE+CAR_STACK_SPACE)/4)
1.90 +#endif
1.91 +
1.92 +#define SP_R13U EXTRA_WORDS
1.93 +#define SP_R14U (SP_R13U+1)
1.94 +#define SP_SPSR (SP_R13U+2)
1.95 +#define SP_R4 (SP_R13U+3)
1.96 +#define SP_R5 (SP_R13U+4)
1.97 +#define SP_R6 (SP_R13U+5)
1.98 +#define SP_R7 (SP_R13U+6)
1.99 +#define SP_R8 (SP_R13U+7)
1.100 +#define SP_R9 (SP_R13U+8)
1.101 +#define SP_R10 (SP_R13U+9)
1.102 +#define SP_R11 (SP_R13U+10)
1.103 +#define SP_PC (SP_R13U+11)
1.104 +
1.105 +#define SP_NEXT (SP_PC+1) // first word on stack before reschedule
1.106 +#endif // __INCLUDE_REG_OFFSETS__
1.107 +
1.108 +class TArmContextElement;
1.109 +class TArmRegSet;
1.110 +
1.111 +/** ARM-specific part of the nano-thread abstraction.
1.112 + @internalComponent
1.113 + */
1.114 +class NThread : public NThreadBase
1.115 + {
1.116 +public:
1.117 + TInt Create(SNThreadCreateInfo& aInfo, TBool aInitial);
1.118 + inline void Stillborn()
1.119 + {}
1.120 +
1.121 + /** Value indicating what event caused thread to enter privileged mode.
1.122 + @publishedPartner
1.123 + @released
1.124 + */
1.125 + enum TUserContextType
1.126 + {
1.127 + EContextNone=0, /**< Thread has no user context */
1.128 + EContextException=1, /**< Hardware exception while in user mode */
1.129 + EContextUndefined,
1.130 + EContextUserInterrupt, /**< Preempted by interrupt taken in user mode */
1.131 + EContextUserInterruptDied, /**< Killed while preempted by interrupt taken in user mode */
1.132 + EContextSvsrInterrupt1, /**< Preempted by interrupt taken in executive call handler */
1.133 + EContextSvsrInterrupt1Died, /**< Killed while preempted by interrupt taken in executive call handler */
1.134 + EContextSvsrInterrupt2, /**< Preempted by interrupt taken in executive call handler */
1.135 + EContextSvsrInterrupt2Died, /**< Killed while preempted by interrupt taken in executive call handler */
1.136 + EContextWFAR, /**< Blocked on User::WaitForAnyRequest() */
1.137 + EContextWFARDied, /**< Killed while blocked on User::WaitForAnyRequest() */
1.138 + EContextExec, /**< Slow executive call */
1.139 + EContextKernel, /**< Kernel side context (for kernel threads) */
1.140 + EContextUserIntrCallback, /**< Blocked/preempted in a user callback on the way back from interrupt */
1.141 + EContextWFARCallback, /**< Blocked/preempted in a user callback on the way back from User::WFAR */
1.142 + };
1.143 +
1.144 + IMPORT_C static const TArmContextElement* const* UserContextTables();
1.145 + IMPORT_C TUserContextType UserContextType();
1.146 + inline TInt SetUserContextType()
1.147 + { return iSpare3=UserContextType(); }
1.148 + inline void ResetUserContextType()
1.149 + { if(iSpare3>EContextUndefined && iSpare3<EContextUserIntrCallback) iSpare3=EContextUndefined; }
1.150 + void GetContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask, const TArmContextElement* aContextTable);
1.151 + void GetUserContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask);
1.152 + void SetUserContext(const TArmRegSet& aContext);
1.153 + void GetSystemContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask);
1.154 +
1.155 + void ModifyUsp(TLinAddr aUsp);
1.156 +
1.157 +#ifdef __CPU_ARM_USE_DOMAINS
1.158 + TUint32 Dacr();
1.159 + void SetDacr(TUint32 aDacr);
1.160 + TUint32 ModifyDacr(TUint32 aClearMask, TUint32 aSetMask);
1.161 +#endif
1.162 +
1.163 +#ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG
1.164 + void SetCar(TUint32 aDacr);
1.165 +#endif
1.166 + IMPORT_C TUint32 Car();
1.167 + IMPORT_C TUint32 ModifyCar(TUint32 aClearMask, TUint32 aSetMask);
1.168 +
1.169 +#ifdef __CPU_HAS_VFP
1.170 + void SetFpExc(TUint32 aDacr);
1.171 +#endif
1.172 + IMPORT_C TUint32 FpExc();
1.173 + IMPORT_C TUint32 ModifyFpExc(TUint32 aClearMask, TUint32 aSetMask);
1.174 + };
1.175 +
1.176 +
1.177 +struct SArmInterruptInfo
1.178 + {
1.179 + TLinAddr iIrqHandler;
1.180 + TLinAddr iFiqHandler;
1.181 + TUint8 iCpuUsageFilter;
1.182 + BTrace::THandler iBTraceHandler;
1.183 + SCpuIdleHandler iCpuIdleHandler;
1.184 + };
1.185 +
1.186 +extern "C" SArmInterruptInfo ArmInterruptInfo;
1.187 +
1.188 +#endif