1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/nkern/arm/entry.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,129 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32/include/nkern/arm/entry.h
1.18 +//
1.19 +//
1.20 +
1.21 +extern "C" {
1.22 +
1.23 +extern void __ArmVectorReset();
1.24 +extern void __ArmVectorUndef();
1.25 +extern void __ArmVectorSwi();
1.26 +extern void __ArmVectorAbortPrefetch();
1.27 +extern void __ArmVectorAbortData();
1.28 +extern void __ArmVectorReserved();
1.29 +extern void __ArmVectorIrq();
1.30 +extern void __ArmVectorFiq();
1.31 +
1.32 +#define __DECLARE_UNDEFINED_INSTRUCTION_HANDLER asm(".word __ArmVectorUndef ")
1.33 +#define __DECLARE_PREFETCH_ABORT_HANDLER asm(".word __ArmVectorAbortPrefetch ")
1.34 +#define __DECLARE_DATA_ABORT_HANDLER asm(".word __ArmVectorAbortData ")
1.35 +
1.36 +/* NOTE: We must ensure that this code goes at the beginning of the kernel image.
1.37 +*/
1.38 +__NAKED__ void __this_must_go_at_the_beginning_of_the_kernel_image()
1.39 + {
1.40 + asm("ldr pc, __reset_vector "); // 00 = Reset vector
1.41 + asm("ldr pc, __undef_vector "); // 04 = Undefined instruction vector
1.42 + asm("ldr pc, __swi_vector "); // 08 = SWI vector
1.43 + asm("ldr pc, __pabt_vector "); // 0C = Prefetch abort vector
1.44 + asm("ldr pc, __dabt_vector "); // 10 = Data abort vector
1.45 + asm("ldr pc, __unused_vector "); // 14 = unused
1.46 + asm("b HandleIrq "); // 18 = IRQ vector
1.47 + // 1C = FIQ vector, code in situ
1.48 + asm("ldr r12, __ArmInterrupt "); // THIS MUST BE AN IDEMPOTENT INSTRUCTION TO AVOID A PROBLEM WITH XSCALE PXA255
1.49 + asm("sub lr, lr, #4 ");
1.50 + asm("str lr, [sp, #-4]! ");
1.51 + // we assume FIQ handler preserves r0-r7 but not r8-r12
1.52 + // hence must be assembler, so stack misalignment OK
1.53 +#if defined(__CPU_ARM_HAS_WORKING_CLREX)
1.54 + CLREX
1.55 +#elif defined(__CPU_ARM_HAS_LDREX_STREX)
1.56 + STREX(8,14, 13); // dummy STREX to reset exclusivity monitor
1.57 +#endif
1.58 +#ifdef __USER_MEMORY_GUARDS_ENABLED__
1.59 + USER_MEMORY_GUARD_ON(,lr,r8);
1.60 + asm("str lr, [sp, #-4]! ");
1.61 +#endif
1.62 +#ifdef BTRACE_CPU_USAGE
1.63 + asm("ldrb r8, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter));
1.64 + asm("ldr lr, _ArmVectorFiq ");
1.65 + asm("mov r10, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EFiqStart<<BTrace::ESubCategoryIndex*8)) );
1.66 + asm("cmp r8,#0");
1.67 + asm("bne btrace_fiq");
1.68 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq
1.69 +
1.70 + asm("btrace_fiq:"); // call trace handler before fiq handler...
1.71 + asm("stmdb sp!, {r0-r3} ");
1.72 + asm("add r0, r10, #%a0" : : "i" ((TInt)4) ); // add size of trace into header
1.73 + asm("mov lr, pc");
1.74 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler));
1.75 + asm("ldr r12, __ArmInterrupt ");
1.76 + asm("ldmia sp!, {r0-r3} ");
1.77 +#endif
1.78 + asm("ldr lr, _ArmVectorFiq ");
1.79 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq
1.80 +
1.81 + asm("HandleIrq: ");
1.82 + asm("sub lr, lr, #4 ");
1.83 + asm("stmfd sp!, {r0-r3,r12,lr} ");
1.84 +#if defined(__CPU_ARM_HAS_WORKING_CLREX)
1.85 + CLREX
1.86 +#elif defined(__CPU_ARM_HAS_LDREX_STREX)
1.87 + STREX(12, 0, 13); // dummy STREX to reset exclusivity monitor
1.88 +#endif
1.89 +#ifdef __USER_MEMORY_GUARDS_ENABLED__
1.90 + USER_MEMORY_GUARD_ON(,lr,r12);
1.91 + asm("str lr, [sp, #-8]! ");
1.92 +#endif
1.93 + asm("ldr r12, __ArmInterrupt ");
1.94 +#ifdef BTRACE_CPU_USAGE
1.95 + asm("mov r0, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EIrqStart<<BTrace::ESubCategoryIndex*8)) );
1.96 + asm("add r0, r0, #%a0" : : "i" ((TInt)4) ); // add size of trace into header
1.97 + asm("ldrb r1, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter));
1.98 + asm("ldr lr, _ArmVectorIrq ");
1.99 + asm("cmp r1,#0");
1.100 + asm("bne btrace_irq");
1.101 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler)); // call IRQ handler, return to ArmVectorIrq
1.102 +
1.103 + asm("btrace_irq:"); // call trace handler before irq handler...
1.104 + asm("mov lr, pc");
1.105 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler));
1.106 + asm("ldr r12, __ArmInterrupt ");
1.107 +#endif
1.108 + asm("ldr lr, _ArmVectorIrq ");
1.109 + asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler)); // call IRQ handler, return to ArmVectorIrq
1.110 +
1.111 + asm("__reset_vector:");
1.112 + asm(".word __ArmVectorReset ");
1.113 + asm("__undef_vector:");
1.114 + __DECLARE_UNDEFINED_INSTRUCTION_HANDLER;
1.115 + asm("__swi_vector:");
1.116 + asm(".word __ArmVectorSwi ");
1.117 + asm("__pabt_vector:");
1.118 + __DECLARE_PREFETCH_ABORT_HANDLER;
1.119 + asm("__dabt_vector:");
1.120 + __DECLARE_DATA_ABORT_HANDLER;
1.121 + asm("__unused_vector:");
1.122 + asm(".word __ArmVectorReserved ");
1.123 +
1.124 + asm("__ArmInterrupt: ");
1.125 + asm(".word ArmInterruptInfo ");
1.126 + asm("_ArmVectorIrq:");
1.127 + asm(".word __ArmVectorIrq");
1.128 + asm("_ArmVectorFiq:");
1.129 + asm(".word __ArmVectorFiq ");
1.130 + }
1.131 +}
1.132 +