1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/memmodel/epoc/platform.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,579 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\memmodel\epoc\platform.h
1.18 +// Public header file for device drivers
1.19 +//
1.20 +// WARNING: This file contains some APIs which are internal and are subject
1.21 +// to change without notice. Such APIs should therefore not be used
1.22 +// outside the Kernel and Hardware Services package.
1.23 +//
1.24 +
1.25 +#ifndef __M32STD_H__
1.26 +#define __M32STD_H__
1.27 +#include <kernel/kernel.h>
1.28 +#include <kernel/kernboot.h>
1.29 +#ifdef __EPOC32__
1.30 +#include <e32rom.h>
1.31 +#else
1.32 +class TRomHeader;
1.33 +class TRomImageHeader;
1.34 +class TRomEntry;
1.35 +#endif
1.36 +//
1.37 +
1.38 +/********************************************
1.39 + * Hardware chunk abstraction
1.40 + ********************************************/
1.41 +
1.42 +/**
1.43 +The list of memory types (aka cache attributes) in Kernel on ARMv6K, ARMv7 and later platforms.
1.44 +Types 0-3 can be used on all platforms. Types 4-7 can be used only on the platforms with memory type remapping.
1.45 +@see TMappingAttributes2
1.46 +@publishedPartner
1.47 +@released
1.48 +*/
1.49 +enum TMemoryType
1.50 + {
1.51 + EMemAttStronglyOrdered = 0, /**< Strongly Ordered memory.*/
1.52 + EMemAttDevice = 1, /**< Device memory.*/
1.53 + EMemAttNormalUncached = 2, /**< Uncached Normal memory. Writes may combine.*/
1.54 + EMemAttNormalCached = 3, /**< Fully cached (Write-Back, Read/Write Allocate, Normal memory).*/
1.55 + EMemAttKernelInternal4 = 4, /**< @internalComponent. Not to be used by device drivers.*/
1.56 + EMemAttPlatformSpecific5= 5, /**< Defined by Baseport - H/W independent.*/
1.57 + EMemAttPlatformSpecific6= 6, /**< Defined by Baseport - H/W specific - see ARM core's document for the details.*/
1.58 + EMemAttPlatformSpecific7= 7 /**< Defined by Baseport - H/W independent.*/
1.59 +};
1.60 +
1.61 +const TUint KMemoryTypeShift = 3; /**< @internalComponent. The number of bits in a TMemoryType value.*/
1.62 +const TUint KMemoryTypeMask = (1<<KMemoryTypeShift)-1; /**< @internalComponent. Mask value for extracting a TMemoryType value from a bitfield.*/
1.63 +
1.64 +/**
1.65 +Memory mapping permissions and attributes.
1.66 +
1.67 +@see TChunkCreateInfo
1.68 +@see Kern::ChunkCreate
1.69 +@see DSharedIoBuffer::New
1.70 +@see DPlatChunkHw::New
1.71 +@see Kern::ChunkPhysicalAddress
1.72 +@see Cache::SyncMemoryBeforeDmaWrite
1.73 +@see Cache::SyncMemoryBeforeDmaRead
1.74 +@see Cache::SyncMemoryBeforeDmaWrite
1.75 +
1.76 +@publishedPartner
1.77 +@released
1.78 +*/
1.79 +enum TMappingAttributes
1.80 + {
1.81 + // access permissions for read
1.82 + EMapAttrReadNoone=0x0, /**< Sets the memory as not readable in any mode */
1.83 + EMapAttrReadSup=0x1, /**< Sets the memory as readable only from Kernel (Supervisor) mode */
1.84 + EMapAttrReadUser=0x4, /**< Sets the memory as readable for user, hence it can be read in both user and supervisor mode*/
1.85 + EMapAttrReadMask=0xF, /**< Used for masking read attributes*/
1.86 +
1.87 + // access permissions for write
1.88 + EMapAttrWriteNoone=0x00, /**< Sets the memory as not writable in any mode */
1.89 + EMapAttrWriteSup=0x10, /**< Sets the memory as writable only from Kernel (Supervisor) mode */
1.90 + EMapAttrWriteUser=0x40, /**< Sets the memory as writable for user, hence it can be written in both user and supervisor mode*/
1.91 + EMapAttrWriteMask=0xF0, /**< Used for masking write attributes*/
1.92 +
1.93 + // access permissions for execute
1.94 + EMapAttrExecNoone=0x000, /**< Sets the memory as not executable in any mode */
1.95 + EMapAttrExecSup=0x100, /**< Sets the memory as executable only from Kernel (Supervisor) mode */
1.96 + EMapAttrExecUser=0x400, /**< Sets the memory as executable for user, hence it can be executed in both user and supervisor mode*/
1.97 + EMapAttrExecMask=0xF00, /**< Used for masking execute attributes*/
1.98 +
1.99 + // access permissions - popular combinations
1.100 + EMapAttrSupRo=0x01, /**< Supervisor has read only and user has no access permissions*/
1.101 + EMapAttrSupRw=0x11, /**< Supervisor has read/write and user has no access permissions*/
1.102 + EMapAttrSupRwx=0x111, /**< Supervisor has read/write/execute and user has no access permissions*/
1.103 + EMapAttrUserRo=0x14, /**< Supervisor has read/write and user has read only permissions*/
1.104 + EMapAttrUserRw=0x44, /**< Supervisor and user both have read/write permissions*/
1.105 + EMapAttrUserRwx=0x444, /**< Supervisor and user both have read/write/execute permissions*/
1.106 + EMapAttrAccessMask=0xFFF, /**< Used for masking access permissions attribute for popular combination */
1.107 +
1.108 + // Level 1 cache/buffer attributes
1.109 + EMapAttrFullyBlocking=0x0000, /**< Level 1 cache/buffer attributes sets the memory as uncached, unbuffered (may not be L2 cached)*/
1.110 + EMapAttrBufferedNC=0x1000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes do not coalesce (may not be L2 cached)*/
1.111 + EMapAttrBufferedC=0x2000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may not be L2 cached)*/
1.112 + EMapAttrL1Uncached=0x3000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may be L2 cached)*/
1.113 + EMapAttrCachedWTRA=0x4000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read allocate*/
1.114 + EMapAttrCachedWTWA=0x5000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read/write allocate*/
1.115 + EMapAttrCachedWBRA=0x6000, /**< Level 1 cache/buffer attributes sets the memory as write-back cached, read allocate*/
1.116 + EMapAttrCachedWBWA=0x7000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read/write allocate*/
1.117 + EMapAttrAltCacheWTRA=0x8000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read allocate, use alternate cache*/
1.118 + EMapAttrAltCacheWTWA=0x9000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read/write allocate, use alternate cache*/
1.119 + EMapAttrAltCacheWBRA=0xA000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read allocate, use alternate cache*/
1.120 + EMapAttrAltCacheWBWA=0xB000, /**< Level 1 cache/buffer attributes write-back cached, read/write allocate, use alternate cache*/
1.121 + EMapAttrL1CachedMax=0xF000, /**< Used to make memory maximally cached in L1 cache*/
1.122 + EMapAttrL1CacheMask=0xF000, /**< Used for masking L1 cache attributes*/
1.123 +
1.124 + // Level 2 cache attributes
1.125 + EMapAttrL2Uncached=0x00000, /**< Level 2 cache attributes used to set memory as uncached at level 2 */
1.126 + EMapAttrL2CachedWTRA=0x40000, /**< Level 2 cache attributes sets memory as write-through cached, read allocate*/
1.127 + EMapAttrL2CachedWTWA=0x50000, /**< Level 2 cache attributes sets memory as write-through cached, read/write allocate*/
1.128 + EMapAttrL2CachedWBRA=0x60000, /**< Level 2 cache attributes sets memory as write-back cached, read allocate*/
1.129 + EMapAttrL2CachedWBWA=0x70000, /**< Level 2 cache attributes sets memory as write-back cached, read/write allocate*/
1.130 + EMapAttrL2CachedMax=0xF0000, /**< Used to make memory maximally cached in L2 cache*/
1.131 + EMapAttrL2CacheMask=0xF0000, /**< Used for masking L2 cache attributes*/
1.132 +
1.133 + // Others
1.134 + EMapAttrCachedMax=0xFF000, /**< Used to set memory as maximally cached for system (fully cached in L1&L2 cache)*/
1.135 + EMapAttrShared=0x100000, /**< Used to set the memory as shared with other processors*/
1.136 + EMapAttrUseECC=0x200000, /**< Used for error correcting code*/
1.137 + };
1.138 +
1.139 +/**
1.140 +Container class for memory region's attributes.
1.141 +It is intended for ARM platforms with memory type and access permission remapping
1.142 +(arm11mpcore, arm1176, cortex_a8 and later), but could be used on any previous platform as well.
1.143 +
1.144 +The object of this type can replace TMappingAttributes bit mask whereever it is in use. For example:
1.145 +@code
1.146 + TChunkCreateInfo chunkInfo;
1.147 + ...
1.148 + new (&chunkInfo.iMapAttr) TMappingAttributes2(EMemAttStronglyOrdered,EFalse,ETrue);
1.149 + r = Kern::ChunkCreate(chunkInfo, ...);
1.150 +@endcode
1.151 +
1.152 +@see TMemoryType
1.153 +@see TMappingAttributes
1.154 +@see TChunkCreateInfo
1.155 +@see Kern::ChunkCreate
1.156 +@see DSharedIoBuffer::New
1.157 +@see DPlatChunkHw::New
1.158 +@see Kern::ChunkPhysicalAddress
1.159 +@see Cache::SyncMemoryBeforeDmaWrite
1.160 +@see Cache::SyncMemoryBeforeDmaRead
1.161 +@see Cache::SyncMemoryBeforeDmaWrite
1.162 +
1.163 +@publishedPartner
1.164 +@released
1.165 +*/
1.166 +class TMappingAttributes2
1.167 + {
1.168 +public:
1.169 +/**
1.170 +Constructor.
1.171 +Memory is always readable by Kernel. Other attributes are defined by input parameters, as follows:
1.172 +@param aType Type (aka cache attributes) of the memory.
1.173 +@param aUserAccess True if memory is also accessed from user code, false if it is only accessible from kernel.
1.174 +@param aWritable True if memory is writable, false if this is read only memory.
1.175 +@param aExecutable True if memory contains code or data, false if it only contains data.
1.176 + Default argument value is false.
1.177 +@param aShared Shared attribute of the mapping:
1.178 + <0 Default value for the platform, e.g. Shareable for SMP, Unshareable for uni-processor.
1.179 + ==0 Unshareable memory
1.180 + >0 Shareable memory
1.181 + To ensure future compatibility, use the value <0 except when absolutely neccessary.
1.182 + Default argument value is -1.
1.183 +@param aParity Parity error attribute of the mapping:
1.184 + <0 Default value for the platform (which is off on all platforms so far).
1.185 + ==0 Parity error doesn't generate external abort.
1.186 + >0 Parity error generates external abort.
1.187 + To ensure future compatibility, use the value <0 except when absolutely neccessary.
1.188 + Default argument value is -1.
1.189 +
1.190 +@see TMemoryType
1.191 +*/
1.192 + IMPORT_C TMappingAttributes2(TMemoryType aType ,
1.193 + TBool aUserAccess ,
1.194 + TBool aWritable ,
1.195 + TBool aExecutable = EFalse,
1.196 + TInt aShared = -1,
1.197 + TInt aParity = -1);
1.198 +
1.199 + TMappingAttributes2(TUint aMapAttr);/**< @internalComponent*/
1.200 + TMemoryType Type(); /**< @internalComponent @return Type of the memory (aka cache attributes).*/
1.201 + TBool UserAccess(); /**< @internalComponent @return True if memory can be accessed from user code.*/
1.202 + TBool Writable(); /**< @internalComponent @return True if memory can be written into, false if this is reaad only memory.*/
1.203 + TBool Executable(); /**< @internalComponent @return True if memory can contain code and data, false if it can only contain data.*/
1.204 + TBool Shared(); /**< @internalComponent @return True if memory is shared, false if not.*/
1.205 + TBool Parity(); /**< @internalComponent @return True if parity error generates external abort, false if not.*/
1.206 + TBool ObjectType2();/**< @internalComponent @return True if the object is TMappingAttributes2, false if it is TMappingAttributes bitmask.*/
1.207 +private:
1.208 + static void Panic(TInt aPanic); /**< @internalComponent*/
1.209 +private:
1.210 + TUint32 iAttributes; /**< @internalComponent*/
1.211 + };
1.212 +
1.213 +/**
1.214 +@internalComponent
1.215 +*/
1.216 +inline TBool ComparePermissions(TInt aActual, TInt aRequired)
1.217 + {
1.218 + return ((aActual&EMapAttrReadMask)>=(aRequired&EMapAttrReadMask)) &&
1.219 + ((aActual&EMapAttrWriteMask)>=(aRequired&EMapAttrWriteMask)) &&
1.220 + ((aActual&EMapAttrExecMask)>=(aRequired&EMapAttrExecMask));
1.221 + }
1.222 +
1.223 +
1.224 +/** Hardware Chunk class
1.225 + Class representing a global mapping of I/O or global memory buffers
1.226 +
1.227 +@publishedPartner
1.228 +@released
1.229 +*/
1.230 +class DPlatChunkHw : public DObject
1.231 + {
1.232 +public:
1.233 + IMPORT_C static TInt New(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs);
1.234 + inline TLinAddr LinearAddress() {return iLinAddr;}
1.235 + inline TPhysAddr PhysicalAddress() {return iPhysAddr;}
1.236 +public:
1.237 + /** @internalComponent */
1.238 + static TInt DoNew(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs);
1.239 +public:
1.240 + TPhysAddr iPhysAddr; /**< @internalComponent */
1.241 + TLinAddr iLinAddr; /**< @internalComponent */
1.242 + TInt iSize; /**< @internalComponent */
1.243 + TUint iAttribs; /**< @internalComponent */ // mapping attributes
1.244 + };
1.245 +
1.246 +/********************************************
1.247 + * Exports from layer 2 or below of the kernel
1.248 + * which are not available to layer 1
1.249 + ********************************************/
1.250 +
1.251 +/**
1.252 +Specifies the operation performed by the TRamZoneCallback function.
1.253 +@see TRamZoneCallback
1.254 +@publishedPartner
1.255 +@released
1.256 +*/
1.257 +enum TRamZoneOp
1.258 + {
1.259 + /** Informs the variant that a specified RAM zone is not currently
1.260 + being used and therefore it may be possible to save power by not refreshing
1.261 + this zone or, if the rest of the its RAM IC's zones are also empty, powering
1.262 + down the RAM IC.
1.263 +
1.264 + The TRamZoneCallback parameter aParam1 is the ID of the zone.
1.265 + The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
1.266 + that are the bit masks of the zones' power status.
1.267 + */
1.268 + ERamZoneOp_PowerDown=0,
1.269 +
1.270 + /** Informs the variant that a specified RAM zone is now required for use
1.271 + and therefore it must be ready.
1.272 + The variant should ensure the zone is refreshed, if required, and that the
1.273 + RAM IC is powered and fully initialised.
1.274 +
1.275 + The TRamZoneCallback parameter aParam1 is the ID of the zone.
1.276 + The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
1.277 + that are the bit masks of the zones' power status.
1.278 + */
1.279 + ERamZoneOp_PowerUp=1,
1.280 +
1.281 + /** Operation that informs the variant of the RAM zones that have been used
1.282 + during the initial stages of the boot process. Any RAM zones that are not
1.283 + in use may be powered down or not refreshed to save power.
1.284 + This will be the first operation requested of the variant and it is only
1.285 + issued once.
1.286 +
1.287 + The TRamZoneCallback parameter aParam1 is unused by this operation.
1.288 + The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
1.289 + that are the bit masks of the zones' power status.
1.290 + */
1.291 + ERamZoneOp_Init=2,
1.292 + };
1.293 +
1.294 +
1.295 +/**
1.296 +Call back function that is invoked by the kernel when its RAM allocator determines
1.297 +that an operation can be performed on a particular RAM zone.
1.298 +
1.299 +@publishedPartner
1.300 +@released
1.301 +
1.302 +@param aOp Type of operation to perform; a value of TRamZoneOp
1.303 +@param aParam1 A value whose use is defined by the TRamZoneOp to be performed
1.304 +@param aParam2 A value whose use is defined by the TRamZoneOp to be performed
1.305 +The data pointed to by aParam2 is const and therefore should not be modified
1.306 +
1.307 +@return KErrNone if successful, otherwise one of the system wide error codes
1.308 +
1.309 +@see TRamZoneOp
1.310 +*/
1.311 +typedef TInt (*TRamZoneCallback) (TRamZoneOp aOp, TAny* aParam1, const TAny* aParam2);
1.312 +
1.313 +/**
1.314 +Holds the number of each page type within a RAM zone.
1.315 +
1.316 +@see Epoc::GetRamZonePageCount()
1.317 +
1.318 +@publishedPartner
1.319 +@released
1.320 +*/
1.321 +struct SRamZonePageCount
1.322 + {
1.323 + TUint iFreePages; /**< The number of free pages in the RAM zone*/
1.324 + TUint iUnknownPages; /**< The number of unknown pages in the RAM zone*/
1.325 + TUint iFixedPages; /**< The number of fixed pages in the RAM zone*/
1.326 + TUint iMovablePages; /**< The number of movable pages in the RAM zone*/
1.327 + TUint iDiscardablePages;/**< The number of discardable pages in the RAM zone*/
1.328 + TUint iReserved[4]; /**<@internalComponent reserved for internal use only*/
1.329 + };
1.330 +
1.331 +/**
1.332 +@publishedPartner
1.333 +@released
1.334 +*/
1.335 +class Epoc
1.336 + {
1.337 +public:
1.338 + /**
1.339 + The types of RAM defragmentation operations.
1.340 + @internalComponent
1.341 + */
1.342 + enum TRamDefragOp
1.343 + {
1.344 + ERamDefrag_DefragRam,
1.345 + ERamDefrag_EmptyRamZone,
1.346 + ERamDefrag_ClaimRamZone,
1.347 + };
1.348 +
1.349 + /**
1.350 + The type of page to move with Epoc::MovePhysicalPage().
1.351 + @internalComponent
1.352 + */
1.353 + enum TRamDefragPageToMove
1.354 + {
1.355 + /**
1.356 + Move the physical page aOld.
1.357 + */
1.358 + ERamDefragPage_Physical,
1.359 + /**
1.360 + Move the page table page that maps the linear address in the
1.361 + current thread at aOld.
1.362 + */
1.363 + ERamDefragPage_PageTable,
1.364 + /**
1.365 + Move the page table info page of the page table that maps the linear
1.366 + address in the current thread at aOld.
1.367 + */
1.368 + ERamDefragPage_PageTableInfo,
1.369 + };
1.370 +
1.371 +
1.372 + IMPORT_C static void SetMonitorEntryPoint(TDfcFn aFunction); /**< @internalComponent */
1.373 + IMPORT_C static void SetMonitorExceptionHandler(TLinAddr aHandler); /**< @internalComponent */
1.374 + IMPORT_C static TAny* ExceptionInfo(); /**< @internalComponent */
1.375 + IMPORT_C static const TRomHeader& RomHeader();
1.376 + IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr);
1.377 + IMPORT_C static TInt CopyToShadowMemory(TLinAddr aDest, TLinAddr aSrc, TUint32 aLength);
1.378 + IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr);
1.379 + IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr);
1.380 + IMPORT_C static TInt AllocPhysicalRam(TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
1.381 + IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
1.382 + IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
1.383 + IMPORT_C static TInt AllocPhysicalRam(TInt aNumPages, TPhysAddr* aPageList);
1.384 + IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aNumPages, TPhysAddr* aPageList);
1.385 + IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList);
1.386 + IMPORT_C static TInt FreePhysicalRam(TPhysAddr aPhysAddr, TInt aSize);
1.387 + IMPORT_C static TInt FreePhysicalRam(TInt aNumPages, TPhysAddr* aPageList);
1.388 + IMPORT_C static TInt ClaimPhysicalRam(TPhysAddr aPhysAddr, TInt aSize);
1.389 + IMPORT_C static TPhysAddr LinearToPhysical(TLinAddr aLinAddr);
1.390 + IMPORT_C static void RomProcessInfo(TProcessCreateInfo& aInfo, const TRomImageHeader& aRomImageHeader); /**< @internalComponent */
1.391 +#ifdef BTRACE_KERNEL_MEMORY
1.392 + static TInt DriverAllocdPhysRam; // the number of bytes allocated by Epoc::AllocPhysicalRam and Epoc::FreePhysicalRam
1.393 + static TInt KernelMiscPages; // the number of bytes of 'miscelaneous' kernel memory allocated
1.394 +#endif
1.395 + IMPORT_C static TInt MovePhysicalPage(TPhysAddr aOld, TPhysAddr& aNew, TRamDefragPageToMove aPageToMove=ERamDefragPage_Physical); /**< @internalComponent */
1.396 + IMPORT_C static TInt SetRamZoneConfig(const SRamZone* aZones, TRamZoneCallback aCallback);
1.397 + IMPORT_C static TInt GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData);
1.398 + IMPORT_C static TInt ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask);
1.399 + };
1.400 +
1.401 +/**
1.402 +@publishedPartner
1.403 +@released
1.404 +*/
1.405 +class DebugSupport
1.406 + {
1.407 +public:
1.408 +
1.409 + /** Bitmask values representing different breakpoint types. */
1.410 + enum TType
1.411 + {
1.412 + EBreakpointGlobal = 1<<0, /**< Breakpoint appears in all processes */
1.413 + EBreakpointLocal = 1<<1, /**< Breakpoint appears in the specified process only. */
1.414 + };
1.415 +
1.416 + IMPORT_C static TInt InitialiseCodeModifier(TUint& aCapabilities, TInt aMinBreakpoints);
1.417 + IMPORT_C static void CloseCodeModifier();
1.418 + IMPORT_C static TInt ModifyCode(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue, TUint aType);
1.419 + IMPORT_C static TInt RestoreCode(DThread* aThread, TLinAddr aAddress);
1.420 +
1.421 +/**
1.422 +@internalTechnology
1.423 +@prototype
1.424 +*/
1.425 + IMPORT_C static void TerminateProcess(DProcess* aProcess, const TInt aReason);
1.426 +
1.427 + };
1.428 +
1.429 +#ifdef __DEBUGGER_SUPPORT__
1.430 +/**
1.431 +@internalComponent
1.432 +*/
1.433 +class CodeModifier : public DBase
1.434 + {
1.435 +public:
1.436 +
1.437 + /** Values for panic values in category 'CodeModifier'. */
1.438 + enum TPanic
1.439 + {
1.440 + EPanicNotInitialised = 0,
1.441 + EPanicInvalidSizeOrAlignment = 1,
1.442 + };
1.443 +
1.444 + /** Defines the type/size of the breakpoint - see TBreakpoint::iSize*/
1.445 + enum TBrkType
1.446 + {
1.447 + EEmpty =0, //The slot is unused
1.448 + EByte =1, //Jazelle breakpoint
1.449 + EHalfword =2, //Thumb breakpoint
1.450 + EWord =4 //ARM breakpoint
1.451 + };
1.452 +
1.453 + TInt static CreateAndInitialise(TInt aMinBreakpoints);
1.454 + ~CodeModifier();
1.455 + void Close();
1.456 + TInt Modify(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue);
1.457 + TInt Restore(DThread* aThread, TLinAddr aAddress);
1.458 + static void CodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess);
1.459 + static DMutex& Mutex() {return *Kern::CodeSegLock();}
1.460 + static void Fault(TPanic aPanic);
1.461 +
1.462 +private:
1.463 +
1.464 + /**Desribes a breakpoint slot in the pool*/
1.465 + struct TBreakpoint
1.466 + {
1.467 + TUint iProcessId; //Id of the process associated to this breakpoint.
1.468 + TUint iAddress; //The virtual address of the breakpoint
1.469 + TUint32 iOldValue; //Will hold the original content of iAddress
1.470 + TInt16 iSize; //Could be one of TBrkType. 0 means empty/unused, otherwise it indicates the size of the breakpoint in bytes.
1.471 + TInt16 iPageIndex; //If iSize!=0 identifies corresponding shadowed page, or -1 if it is non-XIP page.
1.472 + };
1.473 +
1.474 + /** Desribes a page slot in the pool. Used for pages that are shadowed or need to be locked (for demand paging). */
1.475 + struct TPageInfo
1.476 + {
1.477 + TLinAddr iAddress; //Base address of the page.
1.478 + TInt32 iCounter; //The number of breakpoints associated with this page. 0 indicates empty slot.
1.479 + TBool iWasShadowed; //True if the page had been already shadowed before the first breakpoint was applied,
1.480 + //false otherwise. If true, it won't be un-shadowed after all breakpoints are removed.
1.481 +#ifdef __DEMAND_PAGING__
1.482 + /// If set, points to the deamnd paging lock object used to lock this page. Only applies to
1.483 + /// RAM-loaded code.
1.484 + DDemandPagingLock* iPagingLock;
1.485 +#endif
1.486 + };
1.487 +private:
1.488 + TBreakpoint* FindBreakpoint(DThread* aThread, TLinAddr aAddress, TInt aSize, TBool& aOverlap);
1.489 + TBreakpoint* FindEmptyBrk();
1.490 + TInt FindEmptyPageInfo();
1.491 + TInt FindPageInfo(TLinAddr aAddress);
1.492 + TInt IsRom(TLinAddr aAddress);
1.493 + TInt WriteCode(TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue);
1.494 + DProcess* Process(TUint aProcessId);
1.495 + TInt SafeWriteCode(DProcess* aProcess, TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue);
1.496 + void RestorePage(TInt aPageIndex);
1.497 + void DoCodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess);
1.498 +
1.499 +private:
1.500 + TInt iPoolSize;
1.501 + TBreakpoint* iBreakpoints; //Breakpoint pool with iPoolSize slots
1.502 + TPageInfo* iPages; //The pool of the shadowed/locked pages with iPoolSize slots
1.503 + TUint iPageSize;
1.504 + TUint iPageMask;
1.505 + };
1.506 +
1.507 +GLREF_D CodeModifier* TheCodeModifier;
1.508 +#endif //__DEBUGGER_SUPPORT__
1.509 +
1.510 +
1.511 +/**
1.512 +@internalComponent
1.513 +*/
1.514 +inline const TRomEntry &RomEntry(TLinAddr anAddr)
1.515 + {return(*((const TRomEntry *)anAddr));}
1.516 +
1.517 +/**
1.518 +@internalComponent
1.519 +*/
1.520 +inline const TRomImageHeader& RomImageHeader(TLinAddr anAddr)
1.521 + {return(*((const TRomImageHeader*)anAddr));}
1.522 +
1.523 +/**
1.524 +TRamDefragRequest is intended to be used by device drivers to request that RAM defragmentation
1.525 +operations are performed.
1.526 +
1.527 +All RAM defragmentation operations can be invoked synchronously or asynchronously.
1.528 +The asynchronous RAM defragmentation operations can use either a TDfc or a NFastSemaphore
1.529 +to signal to the caller that the operation has completed.
1.530 +
1.531 +@see TDfc
1.532 +@see NFastSemaphore
1.533 +@publishedPartner
1.534 +@released
1.535 +*/
1.536 +class TRamDefragRequest : protected TAsyncRequest
1.537 + {
1.538 +public:
1.539 + IMPORT_C TRamDefragRequest();
1.540 + IMPORT_C TInt DefragRam(TInt aPriority, TInt aMaxPages=0);
1.541 + IMPORT_C TInt DefragRam(NFastSemaphore* aSem, TInt aPriority, TInt aMaxPages=0);
1.542 + IMPORT_C TInt DefragRam(TDfc* aDfc, TInt aPriority, TInt aMaxPages=0);
1.543 + IMPORT_C TInt EmptyRamZone(TUint aId, TInt aPriority);
1.544 + IMPORT_C TInt EmptyRamZone(TUint aId, NFastSemaphore* aSem, TInt aPriority);
1.545 + IMPORT_C TInt EmptyRamZone(TUint aId, TDfc* aDfc, TInt aPriority);
1.546 + IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TInt aPriority);
1.547 + IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, NFastSemaphore* aSem, TInt aPriority);
1.548 + IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TDfc* aDfc, TInt aPriority);
1.549 + IMPORT_C TInt Result();
1.550 + IMPORT_C void Cancel();
1.551 +
1.552 + /**
1.553 + Values that can be specified to control which thread priority
1.554 + the RAM defragmentation operations are run with.
1.555 + */
1.556 + enum TPrioritySpecial
1.557 + {
1.558 + /**
1.559 + The RAM defragmentation operation will use the same thread priority as
1.560 + that of the caller.
1.561 + */
1.562 + KInheritPriority = -1,
1.563 + };
1.564 +
1.565 +private:
1.566 + void SetupPriority(TInt aPriority);
1.567 +
1.568 +private:
1.569 + Epoc::TRamDefragOp iOp;
1.570 + TUint iId;
1.571 + TUint iMaxPages;
1.572 + TInt iThreadPriority;
1.573 + TPhysAddr* iPhysAddr;
1.574 + TInt iSpare[6];
1.575 +
1.576 +public:
1.577 + friend class Defrag;
1.578 + };
1.579 +
1.580 +
1.581 +#endif
1.582 +