1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/memmodel/epoc/multiple/arm/mmboot.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,254 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\memmodel\epoc\multiple\arm\mmboot.h
1.18 +//
1.19 +// WARNING: This file contains some APIs which are internal and are subject
1.20 +// to change without notice. Such APIs should therefore not be used
1.21 +// outside the Kernel and Hardware Services package.
1.22 +//
1.23 +
1.24 +/**
1.25 + @file
1.26 + @publishedPartner
1.27 + @released
1.28 +*/
1.29 +
1.30 +#ifndef __MMBOOT_H__
1.31 +#define __MMBOOT_H__
1.32 +#include <arm.h>
1.33 +#include <memmodel.h>
1.34 +#include <kernel/cache.h>
1.35 +
1.36 +//
1.37 +// Linear address map (1Gb configuration) :
1.38 +// 00000000-001FFFFF Unmapped
1.39 +// 00200000-002FFFFF IPC Alias region
1.40 +// 00300000-003FFFFF Unmapped
1.41 +// 00400000-1FFFFFFF Local data
1.42 +// 20000000-3BFFFFFF Shared data
1.43 +// 3C000000-3DFFFFFF RAM loaded code (=phys ram size up to 256M)
1.44 +// 3E000000-3FFFFFFF DLL static data (=phys ram size/2 up to 128M)
1.45 +// 40000000-7FFFFFFF Unused
1.46 +// 80000000-8FFFFFFF ROM
1.47 +// 90000000-9FFFFFFF User Global Area
1.48 +// A0000000-BFFFFFFF RAM drive
1.49 +// C0000000-C0001FFF Super page/CPU page
1.50 +// C0030000-C0030FFF KPageInfoMap
1.51 +// C0038000-C003FFFF IRQ, FIQ, UND, ABT stacks (4*4K for stacks + 4*4K for guard pages)
1.52 +// C0040000-C00403FF ASID info (256 ASIDs)
1.53 +// C0080000-C00FFFFF Page table info
1.54 +// C1000000-C13FFFFF Page directories (up to 256 * 16KB)
1.55 +// C2000000-C5FFFFFF Page tables
1.56 +// C6000000-C6FFFFFF Primary I/O mappings
1.57 +// C7000000-C7FFFFFF
1.58 +// C8000000-C8FFFFFF Kernel .data/.bss, initial stack, kernel heap
1.59 +// C9000000-C91FFFFF Kernel stacks
1.60 +// C9200000-FBFFFFFF Extra kernel mappings (I/O, RAM loaded device drivers)
1.61 +// FC000000-FDFFFFFF Page Info array
1.62 +// FFF00000-FFFFFFFF Exception vectors
1.63 +//
1.64 +//
1.65 +// Linear address map (2Gb configuration) :
1.66 +// 00000000-001FFFFF Unmapped
1.67 +// 00200000-002FFFFF IPC Alias region
1.68 +// 00300000-003FFFFF Unmapped
1.69 +// 00400000-37FFFFFF Local data
1.70 +// 38000000-3FFFFFFF DLL static data (=phys ram size/2 up to 128M)
1.71 +// 40000000-6FFFFFFF Shared data
1.72 +// 70000000-7FFFFFFF RAM loaded code (=phys ram size up to 256M)
1.73 +// 80000000-8FFFFFFF ROM
1.74 +// 90000000-9FFFFFFF User Global Area
1.75 +// A0000000-BFFFFFFF RAM drive
1.76 +// C0000000-C0001FFF Super page/CPU page
1.77 +// C0030000-C0030FFF KPageInfoMap
1.78 +// C0038000-C003FFFF IRQ, FIQ, UND, ABT stacks (4*4K for stacks + 4*4K for guard pages)
1.79 +// C0040000-C00403FF ASID info (256 ASIDs)
1.80 +// C0080000-C00FFFFF Page table info
1.81 +// C1000000-C13FFFFF Page directories (up to 256 * 16KB)
1.82 +// C2000000-C5FFFFFF Page tables
1.83 +// C6000000-C6FFFFFF Primary I/O mappings
1.84 +// C7000000-C7FFFFFF
1.85 +// C8000000-C8FFFFFF Kernel .data/.bss, initial stack, kernel heap
1.86 +// C9000000-C91FFFFF Kernel stacks
1.87 +// C9200000-FBFFFFFF Extra kernel mappings (I/O, RAM loaded device drivers)
1.88 +// FC000000-FDFFFFFF Page Info array
1.89 +// FFF00000-FFFFFFFF Exception vectors
1.90 +//
1.91 +
1.92 +// Linear addresses
1.93 +const TLinAddr KIPCAlias =0x00200000u;
1.94 +const TLinAddr KUserLocalDataBase =0x00400000u;
1.95 +const TLinAddr KUserSharedDataBase1GB =0x20000000u;
1.96 +const TLinAddr KUserSharedDataEnd1GB =0x40000000u;
1.97 +const TLinAddr KUserSharedDataBase2GB =0x40000000u;
1.98 +const TLinAddr KUserSharedDataEnd2GB =0x80000000u;
1.99 +
1.100 +const TLinAddr KRomLinearBase =0x80000000u;
1.101 +const TLinAddr KRomLinearEnd =0x90000000u;
1.102 +const TLinAddr KUserGlobalDataBase =0x90000000u;
1.103 +const TLinAddr KUserGlobalDataEnd =0xA0000000u;
1.104 +const TLinAddr KRamDriveStartAddress =0xA0000000u;
1.105 +const TInt KRamDriveMaxSize=0x20000000;
1.106 +const TLinAddr KRamDriveEndAddress =0xC0000000u;
1.107 +const TLinAddr KSuperPageLinAddr =0xC0000000u;
1.108 +const TLinAddr KExcptStacksLinearBase =0xC0038000u;
1.109 +const TLinAddr KAsidInfoBase =0xC0040000u;
1.110 +const TLinAddr KPageTableInfoBase =0xC0080000u;
1.111 +const TLinAddr KPageDirectoryBase =0xC1000000u;
1.112 +const TLinAddr KPageTableBase =0xC2000000u;
1.113 +const TLinAddr KPrimaryIOBase =0xC6000000u;
1.114 +const TLinAddr KKernelDataBase =0xC8000000u;
1.115 +const TLinAddr KKernelDataEnd =0xC9200000u;
1.116 +const TLinAddr KKernelSectionEnd =0xFC000000u;
1.117 +
1.118 +const TLinAddr KPageInfoLinearBase =0xFC000000u;
1.119 +
1.120 +const TLinAddr KMachineConfigLinAddr =0xC0000800u;
1.121 +const TLinAddr KDummyUncachedAddr =0xC000F000u;
1.122 +const TLinAddr KTempAddr =0xC0010000u;
1.123 +const TLinAddr KSecondTempAddr =0xC0014000u;
1.124 +const TLinAddr KDefragAltStackAddr =0xC001F000u;
1.125 +const TLinAddr KDemandPagingTempAddr =0xC0020000u; // used by demand paging (size of region is 0x10000)
1.126 +const TLinAddr KPageInfoMap =0xC0030000u;
1.127 +
1.128 +
1.129 +// Domain usage
1.130 +//
1.131 +// 0 All, except...
1.132 +// 1 RAM Drive
1.133 +// 2 IPC Alias chunk
1.134 +// 15 User memory when __USER_MEMORY_GUARDS_ENABLED__ defined
1.135 +const TInt KIPCAliasDomain = 2;
1.136 +const TInt KNumArmDomains = 16; /**< @internalTechnology */
1.137 +
1.138 +// default domain access is client of domain 0, no access to rest
1.139 +const TUint32 KDefaultDomainAccess = 0x00000001u; /**< @internalTechnology */
1.140 +const TUint32 KSupervisorInitialDomainAccess = 0x00000001u; /**< @internalTechnology */
1.141 +
1.142 +#define PDE_IN_DOMAIN(aPde, aDomain) (((aPde) & ~(15 << 5)) | ((aDomain) << 5))
1.143 +
1.144 +// Constants for ARM V6 MMU
1.145 +const TInt KPageShift=12;
1.146 +const TInt KPageSize=1<<KPageShift;
1.147 +const TInt KPageMask=KPageSize-1;
1.148 +const TInt KChunkShift=20;
1.149 +const TInt KChunkSize=1<<KChunkShift;
1.150 +const TInt KChunkMask=KChunkSize-1;
1.151 +const TInt KPageTableShift=KChunkShift-KPageShift+2; // PTE is 4 bytes
1.152 +const TInt KPageTableSize=1<<KPageTableShift;
1.153 +const TInt KPageTableMask=KPageTableSize-1;
1.154 +const TInt KPtClusterShift=KPageShift-KPageTableShift;
1.155 +const TInt KPtClusterSize=1<<KPtClusterShift;
1.156 +const TInt KPtClusterMask=KPtClusterSize-1;
1.157 +const TInt KPtBlockShift=KPageShift-3; /**< @internalTechnology */ // sizeof(SPageTableInfo)=8
1.158 +const TInt KPtBlockSize=1<<KPtBlockShift; /**< @internalTechnology */
1.159 +const TInt KPtBlockMask=KPtBlockSize-1; /**< @internalTechnology */
1.160 +const TInt KPagesInPDEShift=KChunkShift-KPageShift;
1.161 +const TInt KPagesInPDE=1<<KPagesInPDEShift;
1.162 +const TInt KPagesInPDEMask=KPagesInPDE-1;
1.163 +const TInt KLargePageShift=16;
1.164 +const TInt KLargePageSize=1<<KLargePageShift;
1.165 +const TInt KLargePageMask=KLargePageSize-1;
1.166 +
1.167 +const TInt KPageDirectoryShift=32-KChunkShift+2; // PDE is 4 bytes
1.168 +const TInt KPageDirectorySize=1<<KPageDirectoryShift;
1.169 +const TInt KPageDirectoryMask=KPageDirectorySize-1;
1.170 +
1.171 +const TInt KArmV6NumAsids=256;
1.172 +
1.173 +// Permissions - 3 bit field, APX most significant. When __CPU_MEMORY_TYPE_REMAPPING defined, LSB must be 1
1.174 +#if defined(__CPU_MEMORY_TYPE_REMAPPING)
1.175 +const TInt KArmV6PermRORO=7; /**< @internalTechnology */ // sup RO user RO
1.176 +#else
1.177 +const TInt KArmV6PermNONO=0; /**< @internalTechnology */ // no access for anyone
1.178 +const TInt KArmV6PermRWRO=2; /**< @internalTechnology */ // sup RW user RO
1.179 +const TInt KArmV6PermRORO=6; /**< @internalTechnology */ // sup RO user RO
1.180 +#endif
1.181 +const TInt KArmV6PermRWNO=1; /**< @internalTechnology */ // sup RW user no access
1.182 +const TInt KArmV6PermRWRW=3; /**< @internalTechnology */ // sup RW user RW
1.183 +const TInt KArmV6PermRONO=5; /**< @internalTechnology */ // sup RO user no access
1.184 +
1.185 +#if defined(__CPU_MEMORY_TYPE_REMAPPING)
1.186 +// ARM1176, ARM11MPCORE, ARMv7
1.187 +// TMemoryType is used to describe cache attributes
1.188 +// 3 bits are reserved in page table: TEX[0]:C:B
1.189 +#else
1.190 +// Attributes - 5 bit field, TEX in 2-4, CB in 1,0
1.191 +const TInt KArmV6MemAttSO =0x00; /**< @internalTechnology */ // strongly ordered
1.192 +const TInt KArmV6MemAttSD =0x01; /**< @internalTechnology */ // shared device
1.193 +const TInt KArmV6MemAttNSD =0x08; /**< @internalTechnology */ // non-shared device
1.194 +const TInt KArmV6MemAttNCNC =0x04; /**< @internalTechnology */ // normal, outer uncached, inner uncached
1.195 +const TInt KArmV6MemAttWTRAWTRA =0x02; /**< @internalTechnology */ // normal, outer WTRA cached, inner WTRA cached
1.196 +const TInt KArmV6MemAttWBRAWBRA =0x03; /**< @internalTechnology */ // normal, outer WBRA cached, inner WBRA cached
1.197 +const TInt KArmV6MemAttWBWAWBWA =0x15; /**< @internalTechnology */ // normal, outer WBWA cached, inner WBWA cached
1.198 +const TInt KArmV6MemAttNCWTRA =0x12; /**< @internalTechnology */ // normal, outer uncached, inner WTRA cached
1.199 +const TInt KArmV6MemAttNCWBRA =0x13; /**< @internalTechnology */ // normal, outer uncached, inner WBRA cached
1.200 +const TInt KArmV6MemAttNCWBWA =0x11; /**< @internalTechnology */ // normal, outer uncached, inner WBWA cached
1.201 +const TInt KArmV6MemAttWTRANC =0x18; /**< @internalTechnology */ // normal, outer WTRA cached, inner uncached
1.202 +const TInt KArmV6MemAttWTRAWBRA =0x1B; /**< @internalTechnology */ // normal, outer WTRA cached, inner WBRA cached
1.203 +const TInt KArmV6MemAttWTRAWBWA =0x19; /**< @internalTechnology */ // normal, outer WTRA cached, inner WBWA cached
1.204 +const TInt KArmV6MemAttWBRANC =0x1C; /**< @internalTechnology */ // normal, outer WBRA cached, inner uncached
1.205 +const TInt KArmV6MemAttWBRAWTRA =0x1E; /**< @internalTechnology */ // normal, outer WBRA cached, inner WTRA cached
1.206 +const TInt KArmV6MemAttWBRAWBWA =0x1D; /**< @internalTechnology */ // normal, outer WBRA cached, inner WBWA cached
1.207 +const TInt KArmV6MemAttWBWANC =0x14; /**< @internalTechnology */ // normal, outer WBWA cached, inner uncached
1.208 +const TInt KArmV6MemAttWBWAWTRA =0x16; /**< @internalTechnology */ // normal, outer WBWA cached, inner WTRA cached
1.209 +const TInt KArmV6MemAttWBWAWBRA =0x17; /**< @internalTechnology */ // normal, outer WBWA cached, inner WBRA cached
1.210 +#endif
1.211 +
1.212 +const TUint32 KArmV6PdePageTable =0x00000001;/**< @internalTechnology */ // L1 descriptor is page table
1.213 +const TUint32 KArmV6PdeSection =0x00000002;/**< @internalTechnology */ // L1 descriptor is section
1.214 +const TUint32 KArmV6PdeTypeMask =0x00000003;/**< @internalTechnology */
1.215 +const TUint32 KArmV6PdeECCEnable =0x00000200;/**< @internalTechnology */ // ECC enable (all L1 descriptors)
1.216 +const TUint32 KArmV6PdeSectionXN =0x00000010;/**< @internalTechnology */ // Section not executable
1.217 +const TUint32 KArmV6PdeSectionS =0x00010000;/**< @internalTechnology */ // Section shared
1.218 +const TUint32 KArmV6PdeSectionNG =0x00020000;/**< @internalTechnology */ // Section not global
1.219 +const TUint32 KArmV6PdePermMask =0x00008c00;/**< @internalTechnology */ // Section permission bits
1.220 +const TUint32 KArmV6PdeAttMask =0x0000700c;/**< @internalTechnology */ // Section memory attribute bits
1.221 +const TUint32 KArmV6PteLargePage =0x00000001;/**< @internalTechnology */ // L2 descriptor is large page
1.222 +const TUint32 KArmV6PteSmallPage =0x00000002;/**< @internalTechnology */ // L2 descriptor is small page
1.223 +const TUint32 KArmV6PteTypeMask =0x00000003;/**< @internalTechnology */
1.224 +const TUint32 KArmV6PteLargeXN =0x00008000;/**< @internalTechnology */ // Large page not executable
1.225 +const TUint32 KArmV6PteSmallXN =0x00000001;/**< @internalTechnology */ // Small page not executable
1.226 +const TUint32 KArmV6PteS =0x00000400;/**< @internalTechnology */ // Large or small page shared
1.227 +const TUint32 KArmV6PteNG =0x00000800;/**< @internalTechnology */ // Large or small page not global
1.228 +const TUint32 KArmV6PtePermMask =0x00000230;/**< @internalTechnology */ // Large or small page permission bits
1.229 +const TUint32 KArmV6PteLargeAttMask =0x0000700c;/**< @internalTechnology */ // Large page memory attribute bits
1.230 +const TUint32 KArmV6PteSmallAttMask =0x000001cc;/**< @internalTechnology */ // Small page memory attribute bits
1.231 +// Remapped Access Permission coding:
1.232 +const TUint32 KArmV6PteAPX =0x00000200;/**< @internalTechnology */ // RO / !RW
1.233 +const TUint32 KArmV6PteAP1 =0x00000020;/**< @internalTechnology */ // AllAccess / !KernelOnly
1.234 +const TUint32 KArmV6PteAP0 =0x00000010;/**< @internalTechnology */ // Must be set
1.235 +
1.236 +const TPde KPdePresentMask=KArmV6PdeTypeMask; /**< @internalTechnology */
1.237 +const TPde KPdeTypeMask=KArmV6PdeTypeMask; /**< @internalTechnology */
1.238 +const TPde KPdeSectionAddrMask=0xfff00000; /**< @internalTechnology */
1.239 +const TPde KPdePageTableAddrMask=0xfffffc00; /**< @internalTechnology */
1.240 +const TPte KPteLargePageAddrMask=0xffff0000; /**< @internalTechnology */
1.241 +const TPte KPteSmallPageAddrMask=0xfffff000; /**< @internalTechnology */
1.242 +const TInt KLargeSmallPageRatio=KLargePageSize/KPageSize; /**< @internalTechnology */
1.243 +const TPde KPdeNotPresentEntry=0; /**< @internalTechnology */
1.244 +const TPte KPteNotPresentEntry=0; /**< @internalTechnology */
1.245 +const TPte KPtePresentMask=KArmV6PteTypeMask; /**< @internalTechnology */
1.246 +const TPte KPteTypeMask=KArmV6PteTypeMask; /**< @internalTechnology */
1.247 +
1.248 +const TUint32 KTTBRExtraBitsMask =0x0000007f; /**< @internalTechnology */ // Extra bits in TTBR in addition to physical address
1.249 +
1.250 +const TInt KPageInfoShift = 5;
1.251 +
1.252 +const TInt KAbtStackSize=KPageSize; /**< @internalComponent */
1.253 +const TInt KUndStackSize=KPageSize; /**< @internalComponent */
1.254 +const TInt KIrqStackSize=KPageSize; /**< @internalComponent */
1.255 +const TInt KFiqStackSize=KPageSize; /**< @internalComponent */
1.256 +
1.257 +#endif // __MMBOOT_H__