1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/memmodel/epoc/moving/arm/mmboot.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,157 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\memmodel\epoc\moving\arm\mmboot.h
1.18 +//
1.19 +// WARNING: This file contains some APIs which are internal and are subject
1.20 +// to change without notice. Such APIs should therefore not be used
1.21 +// outside the Kernel and Hardware Services package.
1.22 +//
1.23 +
1.24 +/**
1.25 + @file
1.26 + @publishedPartner
1.27 + @released
1.28 +*/
1.29 +
1.30 +#ifndef __MMBOOT_H__
1.31 +#define __MMBOOT_H__
1.32 +#include <arm.h>
1.33 +#include <memmodel.h>
1.34 +#include <kernel/cache.h>
1.35 +
1.36 +//
1.37 +// Linear address map:
1.38 +// 00000000-003FFFFF Unmapped
1.39 +// 00400000-2FFFFFFF Moving process data
1.40 +// 30000000-3FFFFFFF DLL static data (=phys ram size/2 up to 128M, always ends at 40000000)
1.41 +// 40000000-5FFFFFFF RAM drive
1.42 +// 60000000-60001FFF Super page/CPU page
1.43 +// 60030000-600303FF KPageInfoMap
1.44 +// 60038000-6003FFFF IRQ, FIQ, UND, ABT stacks (4*4K for stacks + 4*4K for guard pages)
1.45 +// 61000000-61003FFF Page directory (16K)
1.46 +// 61020000-6103FFFF Page table info (4096 * 8bytes = 32K)
1.47 +// 61100000-611FFFFF Cache flush area
1.48 +// 61200000-612FFFFF Alternate cache flush area
1.49 +// 62000000-623FFFFF Page tables (up to 4096 * 1K)
1.50 +// 63000000-63FFFFFF Primary I/O mappings
1.51 +// 64000000-64FFFFFF Kernel .data/.bss, initial stack, kernel heap
1.52 +// 65000000-655FFFFF fixed processes - usually 2 or 3Mb each.
1.53 +// 65600000-F1FFFFFF Kernel section (includes extra I/O mappings)
1.54 +// F0000000-F1FFFFFF Kernel code (RAM size/2)
1.55 +// F2000000-F5FFFFFF User code (RAM size)
1.56 +// F6000000-F7FFFFFF Page Info array
1.57 +// F8000000-FFEFFFFF ROM
1.58 +// FFF00000-FFFFFFFF Exception vectors
1.59 +//
1.60 +
1.61 +// Linear addresses
1.62 +const TLinAddr KDataSectionBase =0x00400000u;
1.63 +const TLinAddr KDataSectionEnd =0x40000000u;
1.64 +const TLinAddr KRamDriveStartAddress =0x40000000u;
1.65 +const TInt KRamDriveMaxSize =0x20000000;
1.66 +const TLinAddr KRamDriveEndAddress =0x60000000u;
1.67 +
1.68 +const TLinAddr KPageInfoLinearBase =0xF6000000u;
1.69 +
1.70 +const TLinAddr KRomLinearBase =0xF8000000u;
1.71 +const TLinAddr KRomLinearEnd =0xFFF00000u;
1.72 +const TLinAddr KSuperPageLinAddr =0x60000000u;
1.73 +const TLinAddr KExcptStacksLinearBase =0x60038000u;
1.74 +const TLinAddr KPageDirectoryBase =0x61000000u;
1.75 +const TLinAddr KPageTableInfoBase =0x61020000u;
1.76 +const TLinAddr KPageTableBase =0x62000000u;
1.77 +const TLinAddr KPrimaryIOBase =0x63000000u;
1.78 +const TLinAddr KKernelDataBase =0x64000000u;
1.79 +const TLinAddr KKernelDataEnd =0x65000000u;
1.80 +const TLinAddr KKernelSectionEnd =0xFFF00000u; // we always use HIVECS
1.81 +
1.82 +const TLinAddr KMachineConfigLinAddr =0x60000800u;
1.83 +const TLinAddr KDummyUncachedAddr =0x6000F000u;
1.84 +const TLinAddr KTempAddr =0x60010000u;
1.85 +const TLinAddr KSecondTempAddr =0x60014000u;
1.86 +const TLinAddr KDefragAltStackAddr =0x6001F000u;
1.87 +const TLinAddr KPageInfoMap =0x60030000u;
1.88 +
1.89 +const TLinAddr KDCacheFlushArea =0x61100000u;
1.90 +const TInt KDCacheFlushAreaLimit =0x00080000; // 512k
1.91 +const TLinAddr KAltDCacheFlushArea =0x61200000u;
1.92 +const TInt KAltDCacheFlushAreaLimit=0x00080000; // 512k
1.93 +
1.94 +// Constants for ARM MMU
1.95 +const TInt KPageShift=12;
1.96 +const TInt KPageSize=1<<KPageShift;
1.97 +const TInt KPageMask=KPageSize-1;
1.98 +const TInt KChunkShift=20;
1.99 +const TInt KChunkSize=1<<KChunkShift;
1.100 +const TInt KChunkMask=KChunkSize-1;
1.101 +const TInt KPageTableShift=KChunkShift-KPageShift+2; // PTE is 4 bytes
1.102 +const TInt KPageTableSize=1<<KPageTableShift;
1.103 +const TInt KPageTableMask=KPageTableSize-1;
1.104 +const TInt KPtClusterShift=KPageShift-KPageTableShift;
1.105 +const TInt KPtClusterSize=1<<KPtClusterShift;
1.106 +const TInt KPtClusterMask=KPtClusterSize-1;
1.107 +const TInt KPtBlockShift=KPageShift-3; /**< @internalTechnology */ // sizeof(SPageTableInfo)=8
1.108 +const TInt KPtBlockSize=1<<KPtBlockShift; /**< @internalTechnology */
1.109 +const TInt KPtBlockMask=KPtBlockSize-1; /**< @internalTechnology */
1.110 +const TInt KPagesInPDEShift=KChunkShift-KPageShift;
1.111 +const TInt KPagesInPDE=1<<KPagesInPDEShift;
1.112 +const TInt KPagesInPDEMask=KPagesInPDE-1;
1.113 +const TInt KLargePageShift=16;
1.114 +const TInt KLargePageSize=1<<KLargePageShift;
1.115 +const TInt KLargePageMask=KLargePageSize-1;
1.116 +
1.117 +const TInt KPageDirectoryShift=32-KChunkShift+2; // PDE is 4 bytes
1.118 +const TInt KPageDirectorySize=1<<KPageDirectoryShift;
1.119 +const TInt KPageDirectoryMask=KPageDirectorySize-1;
1.120 +
1.121 +const TPde KPdePresentMask=3;
1.122 +const TPde KPdeTypeMask=0x3;
1.123 +const TPde KPdeSectionAddrMask=0xfff00000;
1.124 +const TPde KPdePageTableAddrMask=0xfffffc00;
1.125 +const TPte KPteLargePageAddrMask=0xffff0000;
1.126 +const TPte KPteSmallPageAddrMask=0xfffff000;
1.127 +const TInt KLargeSmallPageRatio=KLargePageSize/KPageSize;
1.128 +const TPde KPdeNotPresentEntry=0;
1.129 +const TPte KPteNotPresentEntry=0;
1.130 +const TPte KPtePresentMask=0x3;
1.131 +const TPte KPteTypeMask=0x3;
1.132 +
1.133 +
1.134 +// Domain usage
1.135 +//
1.136 +/** @internalComponent */
1.137 +enum TArmDomain
1.138 + {
1.139 + EDomainVarUserRun=0,
1.140 + EDomainClient=1,
1.141 + EDomainPageTable=2,
1.142 + EDomainRamDrive=3,
1.143 +
1.144 + ENumDomains=16
1.145 + };
1.146 +
1.147 +// default domain access is 0=manager, 1=client, 2,3=no access, 4-15=client
1.148 +const TUint32 KDefaultDomainAccess = 0x55555507u; /**< @internalComponent */
1.149 +const TUint32 KSupervisorInitialDomainAccess = 0x55555557u; /**< @internalTechnology */
1.150 +
1.151 +const TUint32 KManzanoTTBRExtraBits =0x00000018; /**< @internalTechnology On Manzano, page table walk is L2 cachable*/
1.152 +
1.153 +const TInt KPageInfoShift = 5;
1.154 +
1.155 +const TInt KAbtStackSize=KPageSize; /**< @internalComponent */
1.156 +const TInt KUndStackSize=KPageSize; /**< @internalComponent */
1.157 +const TInt KIrqStackSize=KPageSize; /**< @internalComponent */
1.158 +const TInt KFiqStackSize=KPageSize; /**< @internalComponent */
1.159 +
1.160 +#endif // __MMBOOT_H__