1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/memmodel/epoc/flexible/arm/mmboot.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,240 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +//
1.18 +
1.19 +/**
1.20 + @file
1.21 + @publishedPartner
1.22 + @prototype
1.23 +*/
1.24 +
1.25 +#ifndef __MMBOOT_H__
1.26 +#define __MMBOOT_H__
1.27 +
1.28 +#include <nk_cpu.h>
1.29 +
1.30 +// Linear address map
1.31 +// 00000000-003FFFFF Unmapped
1.32 +// 00400000-7EFFFFFF Local data
1.33 +// 7F000000-7FFFFFFF IPC Alias region
1.34 +// 80000000- ROM
1.35 +// -8FFFFFFF Global user area
1.36 +// 90000000-EFFFFFFF Kernel memory
1.37 +// F0000000-FFF00000 Fixed kernel mappings
1.38 +// FFF00000-FFFFFFFF Exception vectors
1.39 +//
1.40 +
1.41 +// Linear addresses
1.42 +
1.43 +const TLinAddr KUserLocalDataBase =0x00400000u;
1.44 +
1.45 +const TLinAddr KUserLocalDataEnd =0x7f000000u;
1.46 +
1.47 +const TLinAddr KIPCAlias =0x7f000000u;
1.48 +const TLinAddr KIPCAliasAreaSize =0x01000000u;
1.49 +
1.50 +/** Everything above here is global (visible to all processes).*/
1.51 +const TLinAddr KGlobalMemoryBase =0x80000000u;
1.52 +
1.53 +const TLinAddr KRomLinearBase =0x80000000u;
1.54 +
1.55 +/** Everything below here has user access permissions, everything above is supervisor only. */
1.56 +const TLinAddr KUserMemoryLimit =0x90000000u;
1.57 +
1.58 +const TLinAddr KKernelSectionBase =0x90000000u;
1.59 +
1.60 +const TLinAddr KPrimaryIOBase =0xC6000000u; // XXX This magic constant is hard coded into baseports!
1.61 +const TLinAddr KPrimaryIOEnd =0xC8000000u;
1.62 +
1.63 +const TLinAddr KKernelDataBase =0xC8000000u;
1.64 +
1.65 +const TLinAddr KKernelSectionEnd =0xF0000000u;
1.66 +
1.67 +const TLinAddr KSuperPageLinAddr =0xF0000000u;
1.68 +const TLinAddr KMachineConfigLinAddr =0xF0000800u;
1.69 +#ifdef __SMP__
1.70 +const TLinAddr KAPBootPageDirLin =0xF0004000u;
1.71 +const TLinAddr KAPBootPageTableLin =0xF0008000u;
1.72 +const TLinAddr KAPBootPageLin =0xF0009000u;
1.73 +#endif
1.74 +const TLinAddr KDummyUncachedAddr =0xF000F000u;
1.75 +const TLinAddr KPageInfoMap =0xF0010000u;
1.76 +const TLinAddr KExcptStacksLinearBase =0xF0040000u;
1.77 +const TLinAddr KExcptStacksLinearEnd =0xF0080000u;
1.78 +const TLinAddr KTempAddr =0xF0080000u;
1.79 +const TLinAddr KTempAddrEnd =0xF0100000u;
1.80 +
1.81 +const TLinAddr KPageTableInfoBase =0xF0C00000u;
1.82 +const TLinAddr KPageTableInfoEnd =0xF1000000u;
1.83 +
1.84 +const TLinAddr KPageArraySegmentBase =0xF1000000u;
1.85 +const TLinAddr KPageArraySegmentEnd =0xF2000000u;
1.86 +
1.87 +const TLinAddr KPageInfoLinearBase =0xF2000000u;
1.88 +const TLinAddr KPageInfoLinearEnd =0xF4000000u;
1.89 +
1.90 +const TLinAddr KPageDirectoryBase =0xF4000000u;
1.91 +const TLinAddr KPageDirectoryEnd =0xF8000000u;
1.92 +
1.93 +const TLinAddr KPageTableBase =0xF8000000u;
1.94 +const TLinAddr KPageTableEnd =0xFFF00000u;
1.95 +
1.96 +
1.97 +// Domain usage
1.98 +//
1.99 +// 0 All, except...
1.100 +// 2 IPC Alias chunk
1.101 +// 15 User memory when __USER_MEMORY_GUARDS_ENABLED__ defined
1.102 +const TInt KIPCAliasDomain = 2;
1.103 +const TInt KNumArmDomains = 16; /**< @internalTechnology */
1.104 +
1.105 +// default domain access is client of domain 0, no access to rest
1.106 +const TUint32 KDefaultDomainAccess = 0x00000001u; /**< @internalTechnology */
1.107 +const TUint32 KSupervisorInitialDomainAccess = 0x00000001u; /**< @internalTechnology */
1.108 +
1.109 +#define PDE_IN_DOMAIN(aPde, aDomain) (((aPde) & ~(15 << 5)) | ((aDomain) << 5))
1.110 +
1.111 +// Constants for ARM V6 MMU
1.112 +const TInt KPageShift=12;
1.113 +const TInt KPageSize=1<<KPageShift;
1.114 +const TInt KPageMask=KPageSize-1;
1.115 +const TInt KChunkShift=20;
1.116 +const TInt KChunkSize=1<<KChunkShift;
1.117 +const TInt KChunkMask=KChunkSize-1;
1.118 +const TInt KPageTableShift=KChunkShift-KPageShift+2; // PTE is 4 bytes
1.119 +const TInt KPageTableSize=1<<KPageTableShift;
1.120 +const TInt KPageTableMask=KPageTableSize-1;
1.121 +const TInt KPtClusterShift=KPageShift-KPageTableShift;
1.122 +const TInt KPtClusterSize=1<<KPtClusterShift;
1.123 +const TInt KPtClusterMask=KPtClusterSize-1;
1.124 +const TInt KPtBlockShift=KPageShift-4; /**< @internalTechnology */ // sizeof(SPageTableInfo)=16
1.125 +const TInt KPtBlockSize=1<<KPtBlockShift; /**< @internalTechnology */
1.126 +const TInt KPtBlockMask=KPtBlockSize-1; /**< @internalTechnology */
1.127 +const TInt KPagesInPDEShift=KChunkShift-KPageShift;
1.128 +const TInt KPagesInPDE=1<<KPagesInPDEShift;
1.129 +const TInt KPagesInPDEMask=KPagesInPDE-1;
1.130 +const TInt KLargePageShift=16;
1.131 +const TInt KLargePageSize=1<<KLargePageShift;
1.132 +const TInt KLargePageMask=KLargePageSize-1;
1.133 +
1.134 +const TInt KPageDirectoryShift=32-KChunkShift+2; // PDE is 4 bytes
1.135 +const TInt KPageDirectorySize=1<<KPageDirectoryShift;
1.136 +const TInt KPageDirectoryMask=KPageDirectorySize-1;
1.137 +
1.138 +const TInt KMmuAsidCount=256;
1.139 +const TInt KMmuAsidMask=KMmuAsidCount-1;
1.140 +
1.141 +const TUint KNumOsAsids=KMmuAsidCount;
1.142 +const TUint KKernelOsAsid=0;
1.143 +
1.144 +// Permissions - 3 bit field, APX most significant. When __CPU_MEMORY_TYPE_REMAPPING defined, LSB must be 1
1.145 +#if defined(__CPU_MEMORY_TYPE_REMAPPING)
1.146 +const TInt KArmV6PermRORO=7; /**< @internalTechnology */ // sup RO user RO
1.147 +#else
1.148 +const TInt KArmV6PermRORO=6; /**< @internalTechnology */ // sup RO user RO
1.149 +#endif
1.150 +const TInt KArmV6PermRWNO=1; /**< @internalTechnology */ // sup RW user no access
1.151 +const TInt KArmV6PermRWRW=3; /**< @internalTechnology */ // sup RW user RW
1.152 +const TInt KArmV6PermRONO=5; /**< @internalTechnology */ // sup RO user no access
1.153 +
1.154 +#if defined(__CPU_MEMORY_TYPE_REMAPPING)
1.155 +// ARM1176, ARM11MPCORE, ARMv7
1.156 +// TMemoryType is used to describe cache attributes
1.157 +// 3 bits are reserved in page table: TEX[0]:C:B
1.158 +#else
1.159 +// Attributes - 5 bit field, TEX in 2-4, CB in 1,0
1.160 +const TInt KArmV6MemAttSO =0x00; /**< @internalTechnology */ // strongly ordered
1.161 +const TInt KArmV6MemAttSD =0x01; /**< @internalTechnology */ // shared device
1.162 +const TInt KArmV6MemAttNSD =0x08; /**< @internalTechnology */ // non-shared device
1.163 +const TInt KArmV6MemAttNCNC =0x04; /**< @internalTechnology */ // normal, outer uncached, inner uncached
1.164 +const TInt KArmV6MemAttWTRAWTRA =0x02; /**< @internalTechnology */ // normal, outer WTRA cached, inner WTRA cached
1.165 +const TInt KArmV6MemAttWBRAWBRA =0x03; /**< @internalTechnology */ // normal, outer WBRA cached, inner WBRA cached
1.166 +const TInt KArmV6MemAttWBWAWBWA =0x15; /**< @internalTechnology */ // normal, outer WBWA cached, inner WBWA cached
1.167 +const TInt KArmV6MemAttNCWTRA =0x12; /**< @internalTechnology */ // normal, outer uncached, inner WTRA cached
1.168 +const TInt KArmV6MemAttNCWBRA =0x13; /**< @internalTechnology */ // normal, outer uncached, inner WBRA cached
1.169 +const TInt KArmV6MemAttNCWBWA =0x11; /**< @internalTechnology */ // normal, outer uncached, inner WBWA cached
1.170 +const TInt KArmV6MemAttWTRANC =0x18; /**< @internalTechnology */ // normal, outer WTRA cached, inner uncached
1.171 +const TInt KArmV6MemAttWTRAWBRA =0x1B; /**< @internalTechnology */ // normal, outer WTRA cached, inner WBRA cached
1.172 +const TInt KArmV6MemAttWTRAWBWA =0x19; /**< @internalTechnology */ // normal, outer WTRA cached, inner WBWA cached
1.173 +const TInt KArmV6MemAttWBRANC =0x1C; /**< @internalTechnology */ // normal, outer WBRA cached, inner uncached
1.174 +const TInt KArmV6MemAttWBRAWTRA =0x1E; /**< @internalTechnology */ // normal, outer WBRA cached, inner WTRA cached
1.175 +const TInt KArmV6MemAttWBRAWBWA =0x1D; /**< @internalTechnology */ // normal, outer WBRA cached, inner WBWA cached
1.176 +const TInt KArmV6MemAttWBWANC =0x14; /**< @internalTechnology */ // normal, outer WBWA cached, inner uncached
1.177 +const TInt KArmV6MemAttWBWAWTRA =0x16; /**< @internalTechnology */ // normal, outer WBWA cached, inner WTRA cached
1.178 +const TInt KArmV6MemAttWBWAWBRA =0x17; /**< @internalTechnology */ // normal, outer WBWA cached, inner WBRA cached
1.179 +#endif
1.180 +
1.181 +const TUint32 KArmV6PdePageTable =0x00000001;/**< @internalTechnology */ // L1 descriptor is page table
1.182 +const TUint32 KArmV6PdeSection =0x00000002;/**< @internalTechnology */ // L1 descriptor is section
1.183 +const TUint32 KArmV6PdeTypeMask =0x00000003;/**< @internalTechnology */
1.184 +const TUint32 KArmV6PdeECCEnable =0x00000200;/**< @internalTechnology */ // ECC enable (all L1 descriptors)
1.185 +const TUint32 KArmV6PdeSectionXN =0x00000010;/**< @internalTechnology */ // Section not executable
1.186 +const TUint32 KArmV6PdeSectionS =0x00010000;/**< @internalTechnology */ // Section shared
1.187 +const TUint32 KArmV6PdeSectionNG =0x00020000;/**< @internalTechnology */ // Section not global
1.188 +const TUint32 KArmV6PdePermMask =0x00008c00;/**< @internalTechnology */ // Section permission bits
1.189 +const TUint32 KArmV6PdeAttMask =0x0000700c;/**< @internalTechnology */ // Section memory attribute bits
1.190 +const TUint32 KArmV6PteLargePage =0x00000001;/**< @internalTechnology */ // L2 descriptor is large page
1.191 +const TUint32 KArmV6PteSmallPage =0x00000002;/**< @internalTechnology */ // L2 descriptor is small page
1.192 +const TUint32 KArmV6PteTypeMask =0x00000003;/**< @internalTechnology */
1.193 +const TUint32 KArmV6PteLargeXN =0x00008000;/**< @internalTechnology */ // Large page not executable
1.194 +const TUint32 KArmV6PteSmallXN =0x00000001;/**< @internalTechnology */ // Small page not executable
1.195 +const TUint32 KArmV6PteS =0x00000400;/**< @internalTechnology */ // Large or small page shared
1.196 +const TUint32 KArmV6PteNG =0x00000800;/**< @internalTechnology */ // Large or small page not global
1.197 +const TUint32 KArmV6PtePermMask =0x00000230;/**< @internalTechnology */ // Large or small page permission bits
1.198 +const TUint32 KArmV6PteLargeAttMask =0x0000700c;/**< @internalTechnology */ // Large page memory attribute bits
1.199 +const TUint32 KArmV6PteSmallAttMask =0x000001cc;/**< @internalTechnology */ // Small page memory attribute bits
1.200 +// Remapped Access Permission coding:
1.201 +const TUint32 KArmV6PteAP2 =0x00000200;/**< @internalTechnology */ // RO / !RW
1.202 +const TUint32 KArmV6PteSmallTEX2 =0x00000100;/**< @internalTechnology */
1.203 +const TUint32 KArmV6PteSmallTEX1 =0x00000080;/**< @internalTechnology */
1.204 +const TUint32 KArmV6PteSmallTEX0 =0x00000040;/**< @internalTechnology */
1.205 +const TUint32 KArmV6PteAP1 =0x00000020;/**< @internalTechnology */ // AllAccess / !KernelOnly
1.206 +const TUint32 KArmV6PteAP0 =0x00000010;/**< @internalTechnology */ // Must be set
1.207 +
1.208 +const TUint32 KPdePresentMask=KArmV6PdeTypeMask; /**< @internalTechnology */
1.209 +const TUint32 KPdeTypeMask=KArmV6PdeTypeMask; /**< @internalTechnology */
1.210 +const TUint32 KPdeSectionAddrMask=0xfff00000; /**< @internalTechnology */
1.211 +const TUint32 KPdePageTableAddrMask=0xfffffc00; /**< @internalTechnology */
1.212 +const TUint32 KPteLargePageAddrMask=0xffff0000; /**< @internalTechnology */
1.213 +const TUint32 KPteSmallPageAddrMask=0xfffff000; /**< @internalTechnology */
1.214 +const TInt KLargeSmallPageRatio=KLargePageSize/KPageSize; /**< @internalTechnology */
1.215 +const TUint32 KPdeUnallocatedEntry=0; /**< @internalTechnology */
1.216 +const TUint32 KPteUnallocatedEntry=0; /**< @internalTechnology */
1.217 +const TUint32 KPdeMatchMask=0; /**< @internalTechnology */
1.218 +const TUint32 KPteMatchMask=0; /**< @internalTechnology */
1.219 +const TUint32 KPtePresentMask=KArmV6PteTypeMask; /**< @internalTechnology */
1.220 +const TUint32 KPteTypeMask=KArmV6PteTypeMask; /**< @internalTechnology */
1.221 +
1.222 +const TUint32 KTTBRExtraBitsMask =0x0000007f; /**< @internalTechnology */ // Extra bits in TTBR in addition to physical address
1.223 +
1.224 +const TInt KPageInfoShift = 5;
1.225 +
1.226 +#ifdef __CPU_CACHE_HAS_COLOUR
1.227 +const TInt KPageColourShift=2;
1.228 +#else
1.229 +const TInt KPageColourShift=0;
1.230 +#endif
1.231 +const TInt KPageColourCount=(1<<KPageColourShift);
1.232 +const TInt KPageColourMask=KPageColourCount-1;
1.233 +
1.234 +const TInt KAbtStackSize=KPageSize; /**< @internalComponent */
1.235 +const TInt KUndStackSize=KPageSize; /**< @internalComponent */
1.236 +const TInt KIrqStackSize=KPageSize; /**< @internalComponent */
1.237 +const TInt KFiqStackSize=KPageSize; /**< @internalComponent */
1.238 +const TInt KExcStackAddressSpace = KIrqStackSize + KFiqStackSize + KUndStackSize + KAbtStackSize + 4*KPageSize; /**< @internalComponent */
1.239 +
1.240 +const TInt KMaxCPUs = 8;
1.241 +__ASSERT_COMPILE(KExcptStacksLinearEnd-KExcptStacksLinearBase >= (TLinAddr)KExcStackAddressSpace * (TUint)KMaxCPUs);
1.242 +
1.243 +#endif // __MMBOOT_H__