1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/drivers/uart16550.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,171 @@
1.4 +// Copyright (c) 1996-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// e32\include\drivers\uart16550.h
1.18 +//
1.19 +//
1.20 +
1.21 +/**
1.22 + @file
1.23 + @internalTechnology
1.24 +*/
1.25 +
1.26 +#ifndef __UART16550_H__
1.27 +#define __UART16550_H__
1.28 +#include <e32def.h>
1.29 +
1.30 +//
1.31 +// Register Definitions for 16550-type UARTs
1.32 +//
1.33 +
1.34 +const TUint8 K16550TXHROffset=0<<K16550OffsetShift; // Transmit Holding Register
1.35 +const TUint8 K16550RXHROffset=0<<K16550OffsetShift; // Receive Holding Register
1.36 +const TUint8 K16550BDLoOffset=0<<K16550OffsetShift; // Baud Rate Divisor Low
1.37 +const TUint8 K16550IEROffset=1<<K16550OffsetShift; // Interrupt Enable Register
1.38 +const TUint8 K16550BDHiOffset=1<<K16550OffsetShift; // Baud Rate Divisor High
1.39 +const TUint8 K16550ISROffset=2<<K16550OffsetShift; // Interrupt Status Register
1.40 +const TUint8 K16550FCROffset=2<<K16550OffsetShift; // FIFO Control Register
1.41 +const TUint8 K16550LCROffset=3<<K16550OffsetShift; // Line Control Register
1.42 +const TUint8 K16550MCROffset=4<<K16550OffsetShift; // Modem Control Register
1.43 +const TUint8 K16550LSROffset=5<<K16550OffsetShift; // Line Status Register
1.44 +const TUint8 K16550MSROffset=6<<K16550OffsetShift; // Modem Status Register
1.45 +const TUint8 K16550ScratchpadOffset=7<<K16550OffsetShift; // Scratchpad Register
1.46 +
1.47 +// Interrupt Enable Register
1.48 +
1.49 +const TUint8 K16550IER_RDAI=1; // Received Data Available
1.50 +const TUint8 K16550IER_THREI=2; // Transmit Holding Register Empty
1.51 +const TUint8 K16550IER_RLSI=4; // Receive Line Status (error or break)
1.52 +const TUint8 K16550IER_MSI=8; // Modem Status
1.53 +
1.54 +// Interrupt Status Register
1.55 +
1.56 +const TUint8 K16550ISR_NotPending=1; // Not Interrupt Pending
1.57 +const TUint8 K16550ISR_IntIdMask=6; // Mask for Interrupt Identification
1.58 +const TUint8 K16550ISR_RDAI=4; // Received Data Available
1.59 +const TUint8 K16550ISR_THREI=2; // Transmit Holding Register Empty
1.60 +const TUint8 K16550ISR_RLSI=6; // Receive Line Status
1.61 +const TUint8 K16550ISR_MSI=0; // Modem Status
1.62 +const TUint8 K16550ISR_RxTimeout=8; // Set if FIFO timeout (in conjunction with RDA)
1.63 +
1.64 +// FIFO control Register
1.65 +
1.66 +const TUint8 K16550FCR_Enable=1; // Enable TX and RX FIFOs
1.67 +const TUint8 K16550FCR_RxReset=2; // Reset RX FIFO (self-clearing)
1.68 +const TUint8 K16550FCR_TxReset=4; // Reset TX FIFO (self-clearing)
1.69 +const TUint8 K16550FCR_TxRxRdy=8; //
1.70 +const TUint8 K16550FCR_RxTrig1=0; // RX FIFO triggers when >=1 char received
1.71 +const TUint8 K16550FCR_RxTrig4=64; // RX FIFO triggers when >=4 chars received
1.72 +const TUint8 K16550FCR_RxTrig8=128; // RX FIFO triggers when >=8 chars received
1.73 +const TUint8 K16550FCR_RxTrig14=192; // RX FIFO triggers when >=14 chars received
1.74 +
1.75 +// Line Control Register
1.76 +
1.77 +const TUint8 K16550LCR_Data5=0; // 5 bit characters
1.78 +const TUint8 K16550LCR_Data6=1; // 6 bit characters
1.79 +const TUint8 K16550LCR_Data7=2; // 7 bit characters
1.80 +const TUint8 K16550LCR_Data8=3; // 8 bit characters
1.81 +const TUint8 K16550LCR_Stop1=0; // 1 stop bit
1.82 +const TUint8 K16550LCR_Stop2=4; // 2 stop bits
1.83 +const TUint8 K16550LCR_ParityEnable=8; // Use parity
1.84 +const TUint8 K16550LCR_ParityEven=16; // Use even parity
1.85 +const TUint8 K16550LCR_ParityMark=40; // Use mark parity
1.86 +const TUint8 K16550LCR_ParitySpace=56; // Use space parity
1.87 +const TUint8 K16550LCR_TxBreak=64; // Transmit a break
1.88 +const TUint8 K16550LCR_DLAB=128; // Divisor Latch Access
1.89 +
1.90 +// Modem Control Register
1.91 +
1.92 +const TUint8 K16550MCR_DTR=1;
1.93 +const TUint8 K16550MCR_RTS=2;
1.94 +const TUint8 K16550MCR_OUT1=4;
1.95 +const TUint8 K16550MCR_OUT2=8;
1.96 +const TUint8 K16550MCR_LocalLoop=16;
1.97 +
1.98 +// Line Status Register
1.99 +
1.100 +const TUint8 K16550LSR_RxReady=1; // Received data ready
1.101 +const TUint8 K16550LSR_RxOverrun=2; // Receiver overrun
1.102 +const TUint8 K16550LSR_RxParityErr=4; // Receiver parity error
1.103 +const TUint8 K16550LSR_RxFrameErr=8; // Receiver framing error
1.104 +const TUint8 K16550LSR_RxBreak=16; // Receive break detect
1.105 +const TUint8 K16550LSR_TXHREmpty=32; // Transmit Holding Register Empty (FIFO empty)
1.106 +const TUint8 K16550LSR_TxIdle=64; // Transmitter Idle
1.107 +const TUint8 K16550LSR_RxErrPending=128; // FIFO contains an error or break indication
1.108 +
1.109 +// Modem Status Register
1.110 +
1.111 +const TUint8 K16550MSR_DeltaCTS=1;
1.112 +const TUint8 K16550MSR_DeltaDSR=2;
1.113 +const TUint8 K16550MSR_TERI=4;
1.114 +const TUint8 K16550MSR_DeltaDCD=8;
1.115 +const TUint8 K16550MSR_CTS=16;
1.116 +const TUint8 K16550MSR_DSR=32;
1.117 +const TUint8 K16550MSR_RI=64;
1.118 +const TUint8 K16550MSR_DCD=128;
1.119 +
1.120 +// Wrapper class
1.121 +
1.122 +class T16550Uart
1.123 + {
1.124 +public:
1.125 + void ModifyFCR(TUint aClearMask, TUint aSetMask);
1.126 + void ModifyLCR(TUint aClearMask, TUint aSetMask);
1.127 + void ModifyMCR(TUint aClearMask, TUint aSetMask);
1.128 + void ModifyIER(TUint aClearMask, TUint aSetMask);
1.129 + void SetFCR(TUint aValue);
1.130 + void SetLCR(TUint aValue);
1.131 + void SetMCR(TUint aValue);
1.132 + void SetIER(TUint aValue);
1.133 + inline TUint FCR()
1.134 + {return iFCR;}
1.135 + inline TUint LCR()
1.136 + {return iLCR;}
1.137 + inline TUint MCR()
1.138 + {return iMCR;}
1.139 + inline TUint IER()
1.140 + {return iIER;}
1.141 + inline void SetTxData(TUint aData)
1.142 + {iBase[K16550TXHROffset]=(TUint8)aData;}
1.143 + inline TUint RxData()
1.144 + {return iBase[K16550RXHROffset];}
1.145 + inline TUint ISR()
1.146 + {return iBase[K16550ISROffset];}
1.147 + inline TUint LSR()
1.148 + {return iBase[K16550LSROffset];}
1.149 + inline TUint MSR()
1.150 + {return iBase[K16550MSROffset];}
1.151 + inline TUint TestISR(TUint aMask)
1.152 + {return iBase[K16550ISROffset]&aMask;}
1.153 + inline TUint TestLSR(TUint aMask)
1.154 + {return iBase[K16550LSROffset]&aMask;}
1.155 + inline TUint TestMSR(TUint aMask)
1.156 + {return iBase[K16550MSROffset]&aMask;}
1.157 + inline void SetScratch(TUint aValue)
1.158 + {iBase[K16550ScratchpadOffset]=(TUint8)aValue;}
1.159 + inline TUint Scratch()
1.160 + {return iBase[K16550ScratchpadOffset];}
1.161 + inline void SetBaudRateDivisor(TUint aValue)
1.162 + {iBase[K16550BDHiOffset]=(TUint8)(aValue>>8); iBase[K16550BDLoOffset]=(TUint8)aValue;}
1.163 +public:
1.164 + volatile TUint8* iBase; // base address
1.165 + TUint8 iFCR; // FCR follower
1.166 + TUint8 iLCR; // LCR follower
1.167 + TUint8 iMCR; // MCR follower
1.168 + TUint8 iIER; // IER follower
1.169 + };
1.170 +
1.171 +
1.172 +#endif
1.173 +
1.174 +