1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/kernel/eka/include/drivers/dmadefs.h Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,739 @@
1.4 +// Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// include/drivers/dmadefs.h
1.18 +// DMA Framework - General class, enum, constant and type definitions.
1.19 +//
1.20 +//
1.21 +
1.22 +#ifndef __DMADEFS_H__
1.23 +#define __DMADEFS_H__
1.24 +
1.25 +
1.26 +#include <e32def.h>
1.27 +
1.28 +
1.29 +/** The client request callback type */
1.30 +enum TDmaCallbackType
1.31 + {
1.32 + /** Transfer request completion callback */
1.33 + EDmaCallbackRequestCompletion = 0x01,
1.34 + /** Transfer request completion callback - source side */
1.35 + EDmaCallbackRequestCompletion_Src = 0x02,
1.36 + /** Transfer request completion callback - destination side */
1.37 + EDmaCallbackRequestCompletion_Dst = 0x04,
1.38 +
1.39 + /** Descriptor completion callback */
1.40 + EDmaCallbackDescriptorCompletion = 0x08,
1.41 + /** Descriptor completion callback - source side */
1.42 + EDmaCallbackDescriptorCompletion_Src = 0x10,
1.43 + /** Descriptor completion callback - destination side */
1.44 + EDmaCallbackDescriptorCompletion_Dst = 0x20,
1.45 +
1.46 + /** Frame completion callback */
1.47 + EDmaCallbackFrameCompletion = 0x40,
1.48 + /** Frame completion callback - source side */
1.49 + EDmaCallbackFrameCompletion_Src = 0x80,
1.50 + /** Frame completion callback - destination side */
1.51 + EDmaCallbackFrameCompletion_Dst = 0x100,
1.52 +
1.53 + /** H/W descriptor pause event callback */
1.54 + EDmaCallbackLinkedListPaused = 0x200,
1.55 + /** H/W descriptor pause event callback - source side */
1.56 + EDmaCallbackLinkedListPaused_Src = 0x400,
1.57 + /** H/W descriptor pause event callback - destination side */
1.58 + EDmaCallbackLinkedListPaused_Dst = 0x800
1.59 + };
1.60 +
1.61 +
1.62 +/** The outcome of the transfer request */
1.63 +enum TDmaResult
1.64 + {
1.65 + /** Completed without error */
1.66 + EDmaResultOK = 0,
1.67 + /** There was an error */
1.68 + EDmaResultError
1.69 + };
1.70 +
1.71 +
1.72 +
1.73 +/** To be used with address mode field of the DMA transfer config struct.
1.74 +
1.75 + @see TDmaTransferConfig::iAddrMode
1.76 +*/
1.77 +enum TDmaAddrMode
1.78 + {
1.79 + /** Constant addressing. The address remains the same for consecutive
1.80 + accesses.
1.81 + */
1.82 + KDmaAddrModeConstant,
1.83 + /** Post-increment addressing. The address increases by the element size
1.84 + after each access.
1.85 + */
1.86 + KDmaAddrModePostIncrement,
1.87 + /** Post-decrement addressing. The address decreases by the element size
1.88 + after each access.
1.89 + */
1.90 + KDmaAddrModePostDecrement,
1.91 + /** 1D-index addressing. The address always increases by the element size
1.92 + plus the element skip value after each access.
1.93 + */
1.94 + KDmaAddrMode1DIndex,
1.95 + /** 2D-index addressing. The address increases by the element size plus the
1.96 + element skip value - but only within a frame. Once a full frame has been
1.97 + transferred, the address increases by the element size plus the element
1.98 + skip value plus the frame skip value.
1.99 + */
1.100 + KDmaAddrMode2DIndex
1.101 + };
1.102 +
1.103 +
1.104 +/** To be used with the burst size field of the DMA transfer config struct.
1.105 +
1.106 + @see SDmacCaps::iBurstTransactions
1.107 + @see TDmaTransferConfig::iBurstSize
1.108 +*/
1.109 +enum TDmaBurstSize
1.110 + {
1.111 + /** Don't use burst transactions */
1.112 + KDmaNoBursts = -1,
1.113 + /** Don't care (the default) */
1.114 + KDmaBurstSizeAny = 0x00,
1.115 + /** 4 bytes */
1.116 + KDmaBurstSize4 = 0x04,
1.117 + /** 8 bytes */
1.118 + KDmaBurstSize8 = 0x08,
1.119 + /** 16 bytes */
1.120 + KDmaBurstSize16 = 0x10,
1.121 + /** 32 bytes */
1.122 + KDmaBurstSize32 = 0x20,
1.123 + /** 64 bytes */
1.124 + KDmaBurstSize64 = 0x40,
1.125 + /** 128 bytes */
1.126 + KDmaBurstSize128 = 0x80
1.127 + };
1.128 +
1.129 +
1.130 +/** To be used with the flags field of the DMA transfer config struct.
1.131 +
1.132 + @see TDmaTransferConfig::iFlags
1.133 +*/
1.134 +enum TDmaTransferFlags
1.135 + {
1.136 + /** Location is address of a memory buffer (as opposed to a peripheral or a
1.137 + register).
1.138 + */
1.139 + KDmaMemAddr = 0x01,
1.140 + /** Address is a physical address (as opposed to a linear one).
1.141 + If it is a memory address then KDmaMemIsContiguous will need to be set
1.142 + as well.
1.143 + */
1.144 + KDmaPhysAddr = 0x02,
1.145 + /** Target memory is known to be physically contiguous, hence there is
1.146 + no need for the framework to check for memory fragmentation.
1.147 + */
1.148 + KDmaMemIsContiguous = 0x04,
1.149 + /** Don't use packed access (if possible) */
1.150 + KDmaDontUsePacked = 0x08,
1.151 + /** Location is big endian (little endian if not set).
1.152 +
1.153 + To have any effect, this flag requires the DMAC to support endianness
1.154 + conversion.
1.155 +
1.156 + @see SDmacCaps::iEndiannessConversion
1.157 + */
1.158 + KDmaBigEndian = 0x10,
1.159 + /** Don't do endianness conversion even if applicable.
1.160 +
1.161 + To have any effect, this flag requires the DMAC to support endianness
1.162 + conversion.
1.163 +
1.164 + @see SDmacCaps::iEndiannessConversion
1.165 + */
1.166 + KDmaLockEndian = 0x20,
1.167 + /** Execute client request callback after each subtransfer (streaming /
1.168 + loop case).
1.169 +
1.170 + This option is only taken into account if the respective
1.171 + TDmaTransferConfig::iRepeatCount is non-zero.
1.172 +
1.173 + The callback will complete with a TDmaCallbackType of
1.174 + EDmaCallbackRequestCompletion (even if the repeat counts for source and
1.175 + destination are different), unless the flag
1.176 + TDmaPILFlags::KDmaAsymCompletionCallback is set too, in which case what
1.177 + is described there applies.
1.178 + */
1.179 + KDmaCallbackAfterEveryTransfer = 0x40,
1.180 + /** Execute client request callback after each completed hardware
1.181 + descriptor.
1.182 +
1.183 + Requires the DMAC to support this feature. Unless the DMAC supports
1.184 + asymmetric descriptor interrupts as well, this flag should not be set
1.185 + on only one (source or destination) side.
1.186 +
1.187 + @see SDmacCaps::iDescriptorInterrupt
1.188 + @see SDmacCaps::iAsymDescriptorInterrupt
1.189 + */
1.190 + KDmaCallbackAfterEveryDescriptor = 0x80,
1.191 + /** Execute client request callback after each completed frame.
1.192 +
1.193 + Requires the DMAC to support this feature. Unless the DMAC supports
1.194 + asymmetric frame interrupts as well, this flag should not be set on
1.195 + only one (source or destination) side.
1.196 +
1.197 + @see SDmacCaps::iFrameInterrupt
1.198 + @see SDmacCaps::iAsymFrameInterrupt
1.199 + */
1.200 + KDmaCallbackAfterEveryFrame = 0x100
1.201 + };
1.202 +
1.203 +
1.204 +/** To be used with the synchronization flags field of a DMA transfer
1.205 + config struct.
1.206 +
1.207 + @see SDmacCaps::iSynchronizationTypes
1.208 + @see TDmaTransferConfig::iSyncFlags
1.209 +*/
1.210 +enum TDmaTransferSyncFlags
1.211 + {
1.212 + /** Leave the decision on whether the transfer is hardware synchronized at
1.213 + this end (either source or destination) to the Framework. This is the
1.214 + default.
1.215 + */
1.216 + KDmaSyncAuto = 0x00,
1.217 + /** Transfer is not hardware synchronized at this end (either source or
1.218 + destination).
1.219 + */
1.220 + KDmaSyncNone = 0x01,
1.221 + /** Transfer is hardware synchronized at this end (either source or
1.222 + destination). This option can also be used on its own, without any
1.223 + of the following sync sizes.
1.224 + */
1.225 + KDmaSyncHere = 0x02,
1.226 + /** H/W synchronized at this end: transfer one ELEMENT (a number of
1.227 + bytes, depending on the configured element size) per sync event.
1.228 + */
1.229 + KDmaSyncSizeElement = 0x04,
1.230 + /** H/W synchronized at this end: transfer one FRAME (a number of
1.231 + elements, depending on the configured frame size) per sync event.
1.232 + */
1.233 + KDmaSyncSizeFrame = 0x08,
1.234 + /** H/W synchronized at this end: transfer one BLOCK (a number of
1.235 + frames, depending on the configured transfer size) per sync
1.236 + event. This is the most common use case.
1.237 + */
1.238 + KDmaSyncSizeBlock = 0x10,
1.239 + /** H/W synchronized at this end: transfer one PACKET (a number of
1.240 + elements, depending on the configured packet size) per sync event.
1.241 + In cases where the transfer block size is not a multiple of the
1.242 + packet size the last packet will consist of the remaining elements.
1.243 + */
1.244 + KDmaSyncSizePacket = 0x20
1.245 + };
1.246 +
1.247 +
1.248 +/** To be used with the Graphics operation field of a DMA transfer request.
1.249 +
1.250 + @see TDmaTransferArgs::iGraphicsOps
1.251 +*/
1.252 +enum TDmaGraphicsOps
1.253 + {
1.254 + /** Don't use any graphics acceleration feature (the default) */
1.255 + KDmaGraphicsOpNone = 0x00,
1.256 + /** Enable graphics acceleration feature 'Constant Fill' */
1.257 + KDmaGraphicsOpConstantFill = 0x01,
1.258 + /** Enable graphics acceleration feature 'TransparentCopy' */
1.259 + KDmaGraphicsOpTransparentCopy = 0x02
1.260 + };
1.261 +
1.262 +
1.263 +/** To be used with the PIL flags field of a DMA transfer request.
1.264 +
1.265 + @see TDmaTransferArgs::iFlags
1.266 +*/
1.267 +enum TDmaPILFlags
1.268 + {
1.269 + /** Request a different max transfer size (for instance for test
1.270 + purposes).
1.271 + */
1.272 + KDmaAltTransferLength = 0x01,
1.273 + /** Execute client request callback in ISR context instead of from a
1.274 + DFC.
1.275 + */
1.276 + KDmaRequestCallbackFromIsr = 0x02,
1.277 + /** Execute descriptor completion callback in ISR context instead of
1.278 + from a DFC. This option is to be used in conjunction with the
1.279 + TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag.
1.280 + */
1.281 + KDmaDescriptorCallbackFromIsr = 0x04,
1.282 + /** Execute frame completion callback in ISR context instead of
1.283 + from a DFC. This option is to be used in conjunction with the
1.284 + TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag.
1.285 + */
1.286 + KDmaFrameCallbackFromIsr = 0x08,
1.287 + /** Execute the client request callback separately for source and
1.288 + destination subtransfers.
1.289 +
1.290 + This flag also determines the TDmaCallbackType value returned. If set,
1.291 + the callback will complete with EDmaCallbackRequestCompletion_Src or
1.292 + EDmaCallbackRequestCompletion_Dst, respectively, instead of with
1.293 + EDmaCallbackRequestCompletion.
1.294 +
1.295 + Requires the DMAC to support this feature.
1.296 +
1.297 + @see SDmacCaps::iAsymCompletionInterrupt
1.298 + */
1.299 + KDmaAsymCompletionCallback = 0x10,
1.300 + /** Execute the descriptor completion callback separately for source
1.301 + and destination subtransfers.
1.302 +
1.303 + This flag modifies the behaviour of the
1.304 + TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag and also
1.305 + determines the TDmaCallbackType value returned. If set, the callback
1.306 + will complete with EDmaCallbackDescriptorCompletion_Src or
1.307 + EDmaCallbackDescriptorCompletion_Dst, respectively, instead of with
1.308 + EDmaCallbackDescriptorCompletion.
1.309 +
1.310 + Requires the DMAC to support this feature.
1.311 +
1.312 + @see SDmacCaps::iAsymDescriptorInterrupt
1.313 + */
1.314 + KDmaAsymDescriptorCallback = 0x20,
1.315 + /** Execute the frame completion callback separately for source and
1.316 + destination subtransfers.
1.317 +
1.318 + This flag modifies the behaviour of the
1.319 + TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. If set, the
1.320 + callback will complete with EDmaCallbackFrameCompletion_Src or
1.321 + EDmaCallbackFrameCompletion_Dst, respectively, instead of with
1.322 + EDmaCallbackFrameCompletion.
1.323 +
1.324 + Requires the DMAC to support this feature.
1.325 +
1.326 + @see SDmacCaps::iAsymFrameInterrupt
1.327 + */
1.328 + KDmaAsymFrameCallback = 0x40,
1.329 + /** This transfer (only) should use the channel priority indicated by
1.330 + TDmaTransferArgs::iChannelPriority.
1.331 + */
1.332 + KDmaRequestChannelPriority = 0x80
1.333 + };
1.334 +
1.335 +
1.336 +/** Values which can be used with the priority field when opening a channel
1.337 + and/or when fragmenting a transfer request.
1.338 +
1.339 + @see TDmaChannel::SCreateInfo::iPriority
1.340 + @see TDmaTransferArgs::iChannelPriority
1.341 +*/
1.342 +enum TDmaPriority
1.343 + {
1.344 + /** No transfer priority preference (don't care value) */
1.345 + KDmaPriorityNone = 0x0,
1.346 + /** Platform-independent transfer priority 1 (lowest) */
1.347 + KDmaPriority1 = 0x80000001,
1.348 + /** Platform-independent transfer priority 2 */
1.349 + KDmaPriority2 = 0x80000002,
1.350 + /** Platform-independent transfer priority 3 */
1.351 + KDmaPriority3 = 0x80000003,
1.352 + /** Platform-independent transfer priority 4 */
1.353 + KDmaPriority4 = 0x80000004,
1.354 + /** Platform-independent transfer priority 5 */
1.355 + KDmaPriority5 = 0x80000005,
1.356 + /** Platform-independent transfer priority 6 */
1.357 + KDmaPriority6 = 0x80000006,
1.358 + /** Platform-independent transfer priority 7 */
1.359 + KDmaPriority7 = 0x80000007,
1.360 + /** Platform-independent transfer priority 8 (highest) */
1.361 + KDmaPriority8 = 0x80000008
1.362 + };
1.363 +
1.364 +
1.365 +/** Contains the configuration values for either the source or the
1.366 + destination side of a DMA transfer.
1.367 +
1.368 + Note that some fields (notably iElementSize, iElementsPerFrame and
1.369 + iFramesPerTransfer) may only differ between source and destination if
1.370 + the underlying DMAC supports this.
1.371 +
1.372 + @see SDmacCaps::iSrcDstAsymmetry
1.373 + @see TDmaTransferArgs::iSrcConfig
1.374 + @see TDmaTransferArgs::iDstConfig
1.375 +*/
1.376 +struct TDmaTransferConfig
1.377 + {
1.378 +friend struct TDmaTransferArgs;
1.379 +
1.380 + /** Default constructor. Initializes all fields with meaningful default
1.381 + values.
1.382 + */
1.383 +#ifdef DMA_APIV2
1.384 + KIMPORT_C
1.385 +#endif
1.386 + TDmaTransferConfig();
1.387 +
1.388 + /** Intended for general use ie. not 2D or 1D transfers
1.389 + */
1.390 +#ifdef DMA_APIV2
1.391 + KIMPORT_C
1.392 +#endif
1.393 + TDmaTransferConfig (
1.394 + TUint32 aAddr,
1.395 + TUint aTransferFlags,
1.396 + TDmaAddrMode aAddrMode = KDmaAddrModePostIncrement,
1.397 + TUint aSyncFlags = KDmaSyncAuto,
1.398 + TDmaBurstSize aBurstSize = KDmaBurstSizeAny,
1.399 + TUint aElementSize = 0,
1.400 + TUint aElementsPerPacket = 0,
1.401 + TUint aPslTargetInfo = 0,
1.402 + TInt aRepeatCount = 0
1.403 + );
1.404 +
1.405 + /** Intended for 1D and 2D transfers
1.406 + */
1.407 +#ifdef DMA_APIV2
1.408 + KIMPORT_C
1.409 +#endif
1.410 + TDmaTransferConfig (
1.411 + TUint32 aAddr,
1.412 + TUint aElementSize,
1.413 + TUint aElementsPerFrame,
1.414 + TUint aFramesPerTransfer,
1.415 + TInt aElementSkip,
1.416 + TInt aFrameSkip,
1.417 + TUint aTransferFlags,
1.418 + TUint aSyncFlags = KDmaSyncAuto,
1.419 + TDmaBurstSize aBurstSize = KDmaBurstSizeAny,
1.420 + TUint aElementsPerPacket = 0,
1.421 + TUint aPslTargetInfo = 0,
1.422 + TInt aRepeatCount = 0
1.423 + );
1.424 +
1.425 + /** Transfer start address */
1.426 + TUint32 iAddr;
1.427 + /** Address mode */
1.428 + TDmaAddrMode iAddrMode;
1.429 + /** Element size in bytes (1/2/4/8) */
1.430 + TUint iElementSize;
1.431 + /** Number of elements per frame */
1.432 + TUint iElementsPerFrame;
1.433 + /** Number of elements per packet */
1.434 + TUint iElementsPerPacket;
1.435 + /** Number of frames to transfer (result is the transfer block) */
1.436 + TUint iFramesPerTransfer;
1.437 + /** Element skip in bytes (for addr modes E1DIndex or E2DIndex) */
1.438 + TInt iElementSkip;
1.439 + /** Frame skip in bytes (for addr mode E2DIndex) */
1.440 + TInt iFrameSkip;
1.441 + /** Use burst transactions of the specified size (in bytes)
1.442 + @see TDmaBurstSize
1.443 + */
1.444 + TInt iBurstSize;
1.445 + /** PIL src/dst config flags.
1.446 + @see TDmaTransferFlags
1.447 + */
1.448 + TUint32 iFlags;
1.449 + /** Transfer synchronization flags.
1.450 + @see TDmaTransferSyncFlags
1.451 + */
1.452 + TUint32 iSyncFlags;
1.453 + /** Information passed to the PSL */
1.454 + TUint iPslTargetInfo;
1.455 + /** How often to repeat this (sub-)transfer:
1.456 + 0 no repeat (the default)
1.457 + 1..n once / n times
1.458 + -1 endlessly.
1.459 + */
1.460 + TInt iRepeatCount;
1.461 + /** Structure contents delta vector (usage tbd) */
1.462 + TUint32 iDelta;
1.463 + /** Reserved for future use */
1.464 + TUint32 iReserved;
1.465 +
1.466 +private:
1.467 + /** Private constructor. Initializes fields with the values passed in by
1.468 + the legacy version of the DDmaRequest::Fragment() call.
1.469 + */
1.470 + TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc);
1.471 + };
1.472 +
1.473 +
1.474 +/** To be used by the client to pass DMA transfer request details to the
1.475 + framework.
1.476 +
1.477 + Also used internally by the framework as a pseudo descriptor if the
1.478 + controller doesn't support hardware descriptors (scatter/gather LLI).
1.479 +
1.480 + @see DDmaRequest::Fragment
1.481 +*/
1.482 +struct TDmaTransferArgs
1.483 + {
1.484 + friend class DDmaRequest;
1.485 + friend class TDmaChannel;
1.486 + friend class TDmac;
1.487 + friend class DmaChannelMgr;
1.488 +
1.489 + /** Default constructor. Initializes all fields with meaningful default
1.490 + values.
1.491 + */
1.492 +#ifdef DMA_APIV2
1.493 + KIMPORT_C
1.494 +#endif
1.495 + TDmaTransferArgs();
1.496 +
1.497 + /** For transfers where src and dst TDmaTransferConfig structs share some
1.498 + of the same options ie. iDmaTransferFlags, iAddrMode, iSyncFlags,
1.499 + iBurstSize, and iElementSize.
1.500 +
1.501 + @param aSrcAddr
1.502 + @param aDstAddr
1.503 + @param aCount Number of bytes to transfer
1.504 + @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst
1.505 + @param aDmaSyncFlags Bitmask of TDmaTransferSyncFlags for src and dst
1.506 + @param aMode Address mode for src and dst
1.507 + @param aDmaPILFlags Bitmask of TDmaPILFlags
1.508 + @param aElementSize In bytes (1/2/4/8) for src and dst
1.509 + @param aChannelPriority
1.510 + @param aBurstSize for src and dst
1.511 + @param aPslRequestInfo Info word passed to the PSL
1.512 + @param aGraphicOp Graphics operation to be executed
1.513 + @param aColour Colour value for graphics operation
1.514 + */
1.515 +#ifdef DMA_APIV2
1.516 + KIMPORT_C
1.517 +#endif
1.518 + TDmaTransferArgs (
1.519 + TUint aSrcAddr, TUint aDstAddr, TUint aCount,
1.520 + TUint aDmaTransferFlags, TUint aDmaSyncFlags = KDmaSyncAuto,
1.521 + TUint aDmaPILFlags = 0,
1.522 + TDmaAddrMode aMode = KDmaAddrModePostIncrement, TUint aElementSize = 0,
1.523 + TUint aChannelPriority = KDmaPriorityNone,
1.524 + TDmaBurstSize aBurstSize = KDmaBurstSizeAny, TUint aPslRequestInfo = 0,
1.525 + TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0
1.526 + );
1.527 +
1.528 + /** For transfers needing specific options for source and destination
1.529 + TDmaTransferConfig structs.
1.530 +
1.531 + @param aSrc Configuration values for the source
1.532 + @param aDst Configuration values for the destination
1.533 + @param aFlags @see TDmaPILFlags
1.534 + @param aChannelPriority Use for this request (only) the indicated
1.535 + channel priority. Requires KDmaRequestChannelPriority to be set in
1.536 + iFlags as well. @see TDmaPriority
1.537 +
1.538 + @param aPslRequestInfo Info word passed to the PSL
1.539 + @param aGraphicOp Graphics operation to be executed
1.540 + @param aColour Colour value for graphics operation
1.541 + */
1.542 +#ifdef DMA_APIV2
1.543 + KIMPORT_C
1.544 +#endif
1.545 + TDmaTransferArgs (
1.546 + const TDmaTransferConfig& aSrc,
1.547 + const TDmaTransferConfig& aDst,
1.548 + TUint32 aFlags = 0,
1.549 + TUint aChannelPriority = KDmaPriorityNone,
1.550 + TUint aPslRequestInfo = 0,
1.551 + TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0
1.552 + );
1.553 +
1.554 + /** Configuration values for the source */
1.555 + TDmaTransferConfig iSrcConfig;
1.556 + /** Configuration values for the destination */
1.557 + TDmaTransferConfig iDstConfig;
1.558 +
1.559 + /** Number of bytes to transfer (optional).
1.560 +
1.561 + A non-zero value here must be consistent with iElementSize,
1.562 + iElementsPerFrame and iFramesPerTransfer in iSrcConfig and iDstConfig
1.563 + if the latter are specified as well (or instead, they may be left at
1.564 + their default values of zero).
1.565 +
1.566 + If zero, the PIL will fill in a value calculated from multiplying
1.567 + iElementSize, iElementsPerFrame and iFramesPerTransfer in iSrcConfig,
1.568 + so that the PSL can rely on it being always non-zero and valid.
1.569 + */
1.570 + TUint iTransferCount;
1.571 + /** Graphics operation to be executed */
1.572 + TDmaGraphicsOps iGraphicsOps;
1.573 + /** Colour value for graphics operations */
1.574 + TUint32 iColour;
1.575 + /** PIL common flags
1.576 + @see TDmaPILFlags
1.577 + */
1.578 + TUint32 iFlags;
1.579 + /** Use for this request (only) the indicated channel priority.
1.580 + Requires KDmaRequestChannelPriority to be set in iFlags as well.
1.581 + @see TDmaPriority
1.582 + */
1.583 + TUint iChannelPriority;
1.584 + /** Info word passed to the PSL */
1.585 + TUint iPslRequestInfo;
1.586 +
1.587 + /** Structure contents delta vector (usage tbd) */
1.588 + TUint32 iDelta;
1.589 + /** Reserved for future use */
1.590 + TUint32 iReserved1;
1.591 +
1.592 +private:
1.593 + /** Private constructor. Initializes fields with the values passed in by
1.594 + the legacy version of the DDmaRequest::Fragment() call.
1.595 + */
1.596 + TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount,
1.597 + TUint aFlags, TUint32 aPslInfo);
1.598 + /** Stores the PSL cookie returned by TDmaChannel::PslId() at request
1.599 + fragmentation time.
1.600 + The value PslId() is often (but not necessarily) identical with the
1.601 + client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the
1.602 + PIL into DmaChannelMgr::Open() as 'aOpenId'.
1.603 + */
1.604 + TUint32 iChannelCookie;
1.605 + /** Reserved for future use */
1.606 + TUint32 iReserved2;
1.607 + };
1.608 +
1.609 +
1.610 +/** DMAC capabilities info structure.
1.611 +
1.612 + Instances are to be filled in by the PSL and then linked to via TDmaChannel
1.613 + objects after they have been opened.
1.614 +
1.615 + The contents may vary even between channels on the same DMAC (but will
1.616 + remain constant for a given channel for the duration that it is open),
1.617 + depending on static or dynamic factors which only the PSL knows about.
1.618 +
1.619 + @see TDmaChannel::Open
1.620 + @see TDmaChannel::DmacCaps
1.621 +*/
1.622 +struct SDmacCaps
1.623 + {
1.624 + /** DMAC supports n + 1 different channel priorities. */
1.625 + TUint iChannelPriorities;
1.626 + /** DMAC supports the pausing and resuming of channels. */
1.627 + TBool iChannelPauseAndResume;
1.628 + /** DMA addresses must be aligned on an element size boundary. */
1.629 + TBool iAddrAlignedToElementSize;
1.630 + /** DMAC supports 1D (element) index addressing in hardware. */
1.631 + TBool i1DIndexAddressing;
1.632 + /** DMAC supports 2D (frame) index addressing in hardware. */
1.633 + TBool i2DIndexAddressing;
1.634 + /** DMAC supports these transfer synchronization types (bitmap of values).
1.635 +
1.636 + @see TDmaTransferSyncFlags
1.637 + */
1.638 + TUint iSynchronizationTypes;
1.639 + /** DMAC supports burst transactions with these sizes (bitmap of values).
1.640 +
1.641 + @see TDmaBurstSize
1.642 + */
1.643 + TUint iBurstTransactions;
1.644 + /** DMAC supports a 'h/w descriptor complete' interrupt. */
1.645 + TBool iDescriptorInterrupt;
1.646 + /** DMAC supports a 'frame transfer complete' interrupt. */
1.647 + TBool iFrameInterrupt;
1.648 + /** DMAC supports a 'linked-list pause event' interrupt. */
1.649 + TBool iLinkedListPausedInterrupt;
1.650 + /** DMAC supports endianness conversion. */
1.651 + TBool iEndiannessConversion;
1.652 + /** DMAC supports these graphics operations (bitmap of values).
1.653 +
1.654 + @see TDmaGraphicsOps
1.655 + */
1.656 + TUint iGraphicsOps;
1.657 + /** DMAC supports repeated transfers (loops). */
1.658 + TBool iRepeatingTransfers;
1.659 + /** DMAC supports logical channel linking (chaining). */
1.660 + TBool iChannelLinking;
1.661 + /** DMAC supports scatter/gather mode (linked list items). */
1.662 + TBool iHwDescriptors;
1.663 + /** DMAC supports asymmetric source and destination transfer
1.664 + parameters (such as element size).
1.665 + */
1.666 + TBool iSrcDstAsymmetry;
1.667 + /** DMAC supports asymmetric h/w descriptor lists.
1.668 +
1.669 + ETrue here requires ETrue for iHwDescriptors and iSrcDstAsymmetry as
1.670 + well.
1.671 + */
1.672 + TBool iAsymHwDescriptors;
1.673 + /** DMAC with asymmetric descriptor support has the limitation that the
1.674 + number of bytes transferred in source and destination must be equal in
1.675 + every link segment (i.e. in each src/dst descriptor pair).
1.676 +
1.677 + ETrue here requires ETrue for iAsymHwDescriptors as well.
1.678 + */
1.679 + TBool iBalancedAsymSegments;
1.680 + /** DMAC supports separate transfer completion notifications for source and
1.681 + destination side subtransfers.
1.682 +
1.683 + This capability is required for the asymmetric transfer completion
1.684 + callback API feature.
1.685 +
1.686 + @see TDmaPILFlags::KDmaAsymCompletionCallback
1.687 + */
1.688 + TBool iAsymCompletionInterrupt;
1.689 + /** DMAC supports separate descriptor completion notifications for source and
1.690 + destination side.
1.691 +
1.692 + This capability is required for the asymmetric descriptor completion
1.693 + callback API feature.
1.694 +
1.695 + ETrue here requires ETrue for both iDescriptorInterrupt and
1.696 + iAsymHwDescriptors as well.
1.697 +
1.698 + @see TDmaPILFlags::KDmaAsymDescriptorCallback
1.699 + */
1.700 + TBool iAsymDescriptorInterrupt;
1.701 + /** DMAC supports separate frame completion notifications for source and
1.702 + destination side.
1.703 +
1.704 + This capability is required for the asymmetric frame completion
1.705 + callback API feature.
1.706 +
1.707 + ETrue here requires ETrue for iFrameInterrupt as well.
1.708 +
1.709 + @see TDmaPILFlags::KDmaAsymFrameCallback
1.710 + */
1.711 + TBool iAsymFrameInterrupt;
1.712 +
1.713 + /** Reserved for future use */
1.714 + TUint32 iReserved[5];
1.715 + };
1.716 +
1.717 +
1.718 +struct TDmaV2TestInfo
1.719 + {
1.720 + enum {KMaxChannels=32};
1.721 + /** Maximum transfer size in bytes for all channels (ie. the minimum of all channels' maximum size)*/
1.722 + TUint iMaxTransferSize;
1.723 + /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */
1.724 + TUint iMemAlignMask;
1.725 + /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */
1.726 + TUint32 iMemMemPslInfo;
1.727 + /** Number of test single-buffer channels */
1.728 + TInt iMaxSbChannels;
1.729 + /** Pointer to array containing single-buffer test channel ids */
1.730 + TUint32 iSbChannels[KMaxChannels];
1.731 + /** Number of test double-buffer channels */
1.732 + TInt iMaxDbChannels;
1.733 + /** Pointer to array containing double-buffer test channel ids */
1.734 + TUint32 iDbChannels[KMaxChannels];
1.735 + /** Number of test scatter-gather channels */
1.736 + TInt iMaxSgChannels;
1.737 + /** Pointer to array containing scatter-gather test channel ids */
1.738 + TUint32 iSgChannels[KMaxChannels];
1.739 + };
1.740 +
1.741 +
1.742 +#endif // #ifndef __DMADEFS_H__