1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/bsptemplate/asspandvariant/template_variant/variant.mmh Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,158 @@
1.4 +// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// template/template_variant/variant.mmh
1.18 +// TO DO: (mandatory)
1.19 +// Add here a definition for your CPU (list in CONFIG.INC)
1.20 +//
1.21 +//
1.22 +
1.23 +macro __CPU_ARM1176__
1.24 +
1.25 +// TO DO: (mandatory)
1.26 +//
1.27 +// Add here a definition for your Memory Model
1.28 +//
1.29 +#define MM_MULTIPLE
1.30 +
1.31 +// TO DO: (mandatory)
1.32 +//
1.33 +// Macro which generates the names for the binaries for this platform
1.34 +//
1.35 +#define VariantTarget(name,ext) _template_##name##.##ext
1.36 +#define VariantMediaDefIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(template)
1.37 +
1.38 +//Include debug support. Some e32 tests require debug support
1.39 +macro __DEBUGGER_SUPPORT__
1.40 +
1.41 +//
1.42 +// TO DO:
1.43 +//
1.44 +// If euser is built from the variant, uncomment the following line to build it
1.45 +// as ARM rather than Thumb
1.46 +//
1.47 +// #define __BUILD_VARIANT_EUSER_AS_ARM__
1.48 +
1.49 +// TO DO: (optional)
1.50 +//
1.51 +// To replace some of the generic utility functions with variant specific
1.52 +// versions (eg to replace memcpy with a version optimised for the hardware),
1.53 +// uncomment the two lines below and edit the files in the replacementUtils
1.54 +// directory.
1.55 +//
1.56 +// #define REPLACE_GENERIC_UTILS
1.57 +// #define VariantReplacementUtilsPath template/template_variant/replacement_utils
1.58 +
1.59 +// TO DO: (optional)
1.60 +//
1.61 +// Enable BTrace support in release versions of the kernel by adding
1.62 +// the following BTRACE macro declarations
1.63 +//
1.64 +// macro BTRACE_KERNEL_ALL
1.65 +
1.66 +// TO DO:
1.67 +//
1.68 +// Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
1.69 +//
1.70 +// macro __CPU_ARM1136_IS_R1__
1.71 +
1.72 +// TO DO:
1.73 +//
1.74 +// Include the following line if default memory mapping should use shared memory.
1.75 +// Should be on for multicore (SMP) devices.
1.76 +//
1.77 +// macro __CPU_USE_SHARED_MEMORY
1.78 +//
1.79 +
1.80 +// TO DO:
1.81 +//
1.82 +// Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
1.83 +// "CLREX instruction might be ignored during data cache line fill"
1.84 +// is fixed on this hardware.
1.85 +//
1.86 +// macro __CPU_ARM1136_ERRATUM_406973_FIXED
1.87 +
1.88 +// Uncomment next line if:
1.89 +// 1) using the ARM1136 processor and ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID"
1.90 +// is fixed on this hardware, or
1.91 +// 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID"
1.92 +// is fixed on this hardware.
1.93 +//
1.94 +// macro __CPU_ARM1136_ERRATUM_408022_FIXED
1.95 +
1.96 +// Uncomment if:
1.97 +// 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
1.98 +// operation might fail to invalidate some lines if coincident with linefill"
1.99 +// is fixed on this hardware, or
1.100 +// 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
1.101 +// operation might fail to invalidate some lines if coincident with linefill
1.102 +// is fixed on this hardware.
1.103 +// Workaround:
1.104 +// 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
1.105 +// 2) Replaces Invalidate ICache operation with the sequence defined in the errata document.
1.106 +// If this macro is enabled, it should be accompanied by:
1.107 +// "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
1.108 +//
1.109 +// macro __CPU_ARM1136_ERRATUM_411920_FIXED
1.110 +
1.111 +// Uncomment next line if using the ARM1176 processor and ARM1176 Erratum 720013 "Invalidate Instruction
1.112 +// Cache operations can fail" is fixed on this hardware.
1.113 +//
1.114 +// macro __CPU_ARM1176_ERRATUM_720013_FIXED
1.115 +
1.116 +// TO DO:
1.117 +//
1.118 +// Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136
1.119 +// Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly"
1.120 +// is fixed on this hardware.
1.121 +//
1.122 +// macro __CPU_ARM1136_ERRATUM_317041_FIXED
1.123 +
1.124 +// Uncomment the following line if Page Tables/Dirs have to be updated in main memory.
1.125 +// Standard platforms shouldn't have this feature switched on.
1.126 +// This must be accompanied by __ARM_L210_CACHE__ or __ARM_L220_CACHE__ macro.
1.127 +// Omission:: The solution doesn't update temporary mappings
1.128 +// of inter-process communication (IPC) - aka aliasing.
1.129 +//
1.130 +// macro __FLUSH_PT_INTO_RAM__
1.131 +
1.132 +// Uncomment the following line if Symbian OS is running in TrustZone non-secure state and the
1.133 +// secure state has prevented code executing in non-secure state from being able to mask FIQs by
1.134 +// setting the SCR.FW bit in the secure configuration register.
1.135 +//
1.136 +// macro __FIQ_RESERVED_FOR_SECURE_STATE__
1.137 +
1.138 +// Various PlatSec configuration options cannot be disabled even by clearing the appropriate
1.139 +// bits in the kernel configuration flags - they are enforced at compile time. Uncomment the
1.140 +// following to allow the clearing of bits in the kernel config flags to disable the relevant
1.141 +// options at run time.
1.142 +//
1.143 +//macro __PLATSEC_UNLOCKED__
1.144 +
1.145 +// If this macro is enabled then EMapAttrBufferedNC memory will be remapped as EMapAttrFullyBlocking
1.146 +//macro FAULTY_NONSHARED_DEVICE_MEMORY
1.147 +
1.148 +// Uncomment the following line if L210/20 cache is running in forced-WT mode.
1.149 +// (Forced_WT bit set in Debug Control Register of L210/20 cache controller.)
1.150 +// macro __ARM_L2_CACHE_WT_MODE
1.151 +
1.152 +// For the status of errata of L210 & L220 cache, see the header of source file:
1.153 +// e32\kernel\arm\cachel2.cpp
1.154 +
1.155 +#if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__)
1.156 +library VariantTarget(katemplate,lib)
1.157 +#endif
1.158 +
1.159 +// Uncomment the following if IIC Controller is required
1.160 +// library iic.lib // commented out as this iic.lib is now included from iic_channel.mmh
1.161 +