1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/bsptemplate/asspandvariant/template_variant/bootstrap/template.s Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,607 @@
1.4 +; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +; All rights reserved.
1.6 +; This component and the accompanying materials are made available
1.7 +; under the terms of the License "Eclipse Public License v1.0"
1.8 +; which accompanies this distribution, and is available
1.9 +; at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +;
1.11 +; Initial Contributors:
1.12 +; Nokia Corporation - initial contribution.
1.13 +;
1.14 +; Contributors:
1.15 +;
1.16 +; Description:
1.17 +; template/bootstrap/template.s
1.18 +; Template for platform specific boot code
1.19 +;
1.20 +
1.21 + GBLL __VARIANT_S__ ; indicates that this is platform-specific code
1.22 + GBLL __TEMPLATE_S__ ; indicates which source file this is
1.23 +
1.24 + INCLUDE bootcpu.inc
1.25 +
1.26 +;
1.27 +;*******************************************************************************
1.28 +;
1.29 +; Platform specific constant definitions
1.30 +
1.31 +RamBank0Base EQU 0x10000000
1.32 +RamBank0MaxSize EQU 0x00800000
1.33 +RamBank1Base EQU 0x20000000
1.34 +RamBank1MaxSize EQU 0x00000000
1.35 +
1.36 +PrimaryRomBase EQU 0x00000000
1.37 +PrimaryRomSize EQU 0x00800000
1.38 +ExtensionRomBase EQU 0x08000000
1.39 +ExtensionRomSize EQU 0x00000000
1.40 +
1.41 +Serial0PhysBase EQU 0x80000000
1.42 +Serial1PhysBase EQU 0x80000100
1.43 +
1.44 +;
1.45 +;*******************************************************************************
1.46 +;
1.47 +
1.48 + AREA |Boot$$Code|, CODE, READONLY, ALIGN=6
1.49 +
1.50 +;
1.51 +;*******************************************************************************
1.52 +;
1.53 +
1.54 +
1.55 +
1.56 +
1.57 +;*******************************************************************************
1.58 +; Initialise Hardware
1.59 +; Initialise CPU registers
1.60 +; Determine the hardware configuration
1.61 +; Determine the reset reason. If it is wakeup from a low power mode, perform
1.62 +; whatever reentry sequence is required and jump back to the kernel.
1.63 +; Set up the memory controller so that at least some RAM is available
1.64 +; Set R10 to point to the super page or to a temporary version of the super page
1.65 +; with at least the following fields valid:
1.66 +; iBootTable, iCodeBase, iActiveVariant, iCpuId
1.67 +; In debug builds initialise the debug serial port
1.68 +;
1.69 +; Enter with:
1.70 +; R12 points to TRomHeader
1.71 +; NO STACK
1.72 +; R14 = return address (as usual)
1.73 +;
1.74 +; All registers may be modified by this call
1.75 +;*******************************************************************************
1.76 + IF CFG_BootLoader
1.77 + ; For bootloader we only get here on a full reset
1.78 + ; Other resets will simply jump back into the previously-loaded image
1.79 + EXPORT DoInitialiseHardware
1.80 +DoInitialiseHardware ROUT
1.81 + ELSE
1.82 + EXPORT InitialiseHardware
1.83 +InitialiseHardware ROUT
1.84 + ENDIF
1.85 + MOV r13, lr ; save return address
1.86 + ADRL r1, ParameterTable ; pass address of parameter table
1.87 + BL InitCpu ; initialise CPU/MMU registers
1.88 +
1.89 + ; Put your hardware initialising code here
1.90 +
1.91 + IF CFG_DebugBootRom
1.92 + BL InitDebugPort
1.93 + ENDIF
1.94 +
1.95 +; Set up the required super page values
1.96 + LDR r10, =0xC0000000 ; initial super page
1.97 + LDR r0, =0x05040001 ; variant code
1.98 + STR r0, [r10, #SSuperPageBase_iActiveVariant]
1.99 + STR r0, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason (from hardware)
1.100 + ADD r1, r10, #CpuPageOffset
1.101 + STR r1, [r10, #SSuperPageBase_iMachineData]
1.102 + ADRL r0, BootTable
1.103 + STR r0, [r10, #SSuperPageBase_iBootTable] ; Set the boot function table
1.104 + STR r12, [r10, #SSuperPageBase_iCodeBase] ; Set the base address of bootstrap code
1.105 + MRC p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 (remove if no CP15)
1.106 + STR r0, [r10, #SSuperPageBase_iCpuId]
1.107 +
1.108 + MOV pc, r13 ; return
1.109 +
1.110 +
1.111 +
1.112 +
1.113 +
1.114 +;*******************************************************************************
1.115 +; Notify an unrecoverable error during the boot process
1.116 +;
1.117 +; Enter with:
1.118 +; R14 = address at which fault detected
1.119 +;
1.120 +; Don't return
1.121 +;*******************************************************************************
1.122 + EXPORT Fault
1.123 +Fault ROUT
1.124 + B BasicFaultHandler ; generic handler dumps registers via debug
1.125 + ; serial port
1.126 +
1.127 +
1.128 +
1.129 +
1.130 +
1.131 +;*******************************************************************************
1.132 +; Reboot the system
1.133 +;
1.134 +; Enter with:
1.135 +; R0 = reboot reason code
1.136 +;
1.137 +; Don't return (of course)
1.138 +;*******************************************************************************
1.139 + ALIGN 32, 0
1.140 + EXPORT RestartEntry
1.141 +RestartEntry ROUT
1.142 + ; save R0 parameter in HW dependent register which is preserved over reset
1.143 + ; put HW specific code here to reset system
1.144 + SUB pc, pc, #8
1.145 +
1.146 +
1.147 +
1.148 +
1.149 +
1.150 +;*******************************************************************************
1.151 +; Get a pointer to the list of RAM banks
1.152 +;
1.153 +; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where
1.154 +; BASE is the physical base address of the bank and MAXSIZE is the maximum
1.155 +; amount of RAM which may be present in that bank. MAXSIZE should be a power of
1.156 +; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the
1.157 +; specified range of addresses and determine the actual amount of RAM if any
1.158 +; present in the bank. The list is terminated by an entry with zero size.
1.159 +;
1.160 +; The pointer returned will usually be to constant data, but could equally well
1.161 +; point to RAM if dynamic determination of the list is required.
1.162 +;
1.163 +; Enter with :
1.164 +; R10 points to super page
1.165 +; R12 points to ROM header
1.166 +; R13 points to valid stack
1.167 +;
1.168 +; Leave with :
1.169 +; R0 = pointer
1.170 +; Nothing else modified
1.171 +;*******************************************************************************
1.172 +GetRamBanks ROUT
1.173 + ADR r0, %FT1
1.174 + MOV pc, lr
1.175 +1
1.176 + DCD RamBank0Base, RamBank0MaxSize
1.177 + DCD RamBank1Base, RamBank1MaxSize
1.178 + DCD 0,0 ; terminator
1.179 +
1.180 +
1.181 +
1.182 +
1.183 +
1.184 +;*******************************************************************************
1.185 +; Get a pointer to the list of ROM banks
1.186 +;
1.187 +; The pointer returned should point to a list of entries of SRomBank structures,
1.188 +; usually declared with the ROM_BANK macro.
1.189 +; The list is terminated by a zero size entry (four zero words)
1.190 +;
1.191 +; ROM_BANK PB, SIZE, LB, W, T, RS, SS
1.192 +; PB = physical base address of bank
1.193 +; SIZE = size of bank
1.194 +; LB = linear base if override required - usually set this to 0
1.195 +; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32)
1.196 +; T = type (see TRomType enum in kernboot.h)
1.197 +; RS = random speed
1.198 +; SS = sequential speed
1.199 +;
1.200 +; Only PB, SIZE, LB are used by the rest of the bootstrap.
1.201 +; The information given here can be modified by the SetupRomBank call, if
1.202 +; dynamic detection and sizing of ROMs is required.
1.203 +;
1.204 +; Enter with :
1.205 +; R10 points to super page
1.206 +; R12 points to ROM header
1.207 +; R13 points to valid stack
1.208 +;
1.209 +; Leave with :
1.210 +; R0 = pointer
1.211 +; Nothing else modified
1.212 +;*******************************************************************************
1.213 +GetRomBanks ROUT
1.214 + ADR r0, %FT1
1.215 + MOV pc, lr
1.216 +1
1.217 + ROM_BANK PrimaryRomBase, PrimaryRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0
1.218 + ROM_BANK ExtensionRomBase, ExtensionRomSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0
1.219 + DCD 0,0,0,0 ; terminator
1.220 +
1.221 +
1.222 +
1.223 +
1.224 +
1.225 +;*******************************************************************************
1.226 +; Get a pointer to the list of hardware banks
1.227 +;
1.228 +; The pointer returned should point to a list of hardware banks declared with
1.229 +; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list.
1.230 +; For the direct memory model, all hardware on the system should be mapped here
1.231 +; and the mapping will set linear address = physical address.
1.232 +; For the moving or multiple model, only the hardware required to boot the kernel
1.233 +; and do debug tracing needs to be mapped here. The linear addresses used will
1.234 +; start at KPrimaryIOBase and step up as required with the order of banks in
1.235 +; the list being maintained in the linear addresses used.
1.236 +;
1.237 +; HW_MAPPING PB, SIZE, MULT
1.238 +; This declares a block of I/O with physical base PB and address range SIZE
1.239 +; blocks each of which has a size determined by MULT. The page size used for
1.240 +; the mapping is determined by MULT. The linear address base of the mapping
1.241 +; will be the next free linear address rounded up to the size specified by
1.242 +; MULT.
1.243 +; The permissions used for the mapping are the standard I/O permissions (BTP_Hw).
1.244 +;
1.245 +; HW_MAPPING_EXT PB, SIZE, MULT
1.246 +; This declares a block of I/O with physical base PB and address range SIZE
1.247 +; blocks each of which has a size determined by MULT. The page size used for
1.248 +; the mapping is determined by MULT. The linear address base of the mapping
1.249 +; will be the next free linear address rounded up to the size specified by
1.250 +; MULT.
1.251 +; The permissions used for the mapping are determined by a BTP_ENTRY macro
1.252 +; immediately following this macro in the HW bank list or by a DCD directive
1.253 +; specifying a different standard permission type.
1.254 +;
1.255 +; HW_MAPPING_EXT2 PB, SIZE, MULT, LIN
1.256 +; This declares a block of I/O with physical base PB and address range SIZE
1.257 +; blocks each of which has a size determined by MULT. The page size used for
1.258 +; the mapping is determined by MULT. The linear address base of the mapping
1.259 +; is specified by the LIN parameter.
1.260 +; The permissions used for the mapping are the standard I/O permissions (BTP_Hw).
1.261 +;
1.262 +; HW_MAPPING_EXT3 PB, SIZE, MULT, LIN
1.263 +; This declares a block of I/O with physical base PB and address range SIZE
1.264 +; blocks each of which has a size determined by MULT. The page size used for
1.265 +; the mapping is determined by MULT. The linear address base of the mapping
1.266 +; is specified by the LIN parameter.
1.267 +; The permissions used for the mapping are determined by a BTP_ENTRY macro
1.268 +; immediately following this macro in the HW bank list or by a DCD directive
1.269 +; specifying a different standard permission type.
1.270 +;
1.271 +; Configurations without an MMU need not implement this function.
1.272 +;
1.273 +; Enter with :
1.274 +; R10 points to super page
1.275 +; R12 points to ROM header
1.276 +; R13 points to valid stack
1.277 +;
1.278 +; Leave with :
1.279 +; R0 = pointer
1.280 +; Nothing else modified
1.281 +;*******************************************************************************
1.282 +GetHwBanks ROUT
1.283 + ADR r0, %FT1
1.284 + MOV pc, lr
1.285 +1
1.286 + IF CFG_MMDirect
1.287 + ; for direct model we must map all peripherals here
1.288 + ; use section mappings to reduce number of page tables required
1.289 + HW_MAPPING 0x00100000, 31, HW_MULT_1M ; 0x00100000 - 0x01FFFFFF
1.290 + HW_MAPPING 0x08000000, 32, HW_MULT_1M ; 0x08000000 - 0x09FFFFFF
1.291 + HW_MAPPING 0x80000000, 1, HW_MULT_1M ; 0x80000000 - 0x800FFFFF
1.292 + HW_MAPPING 0x90000000, 1, HW_MULT_1M ; 0x90000000 - 0x900FFFFF
1.293 + HW_MAPPING 0xA0000000, 1, HW_MULT_1M ; 0xA0000000 - 0xA00FFFFF
1.294 + HW_MAPPING 0xB0000000, 1, HW_MULT_1M ; 0xB0000000 - 0xB00FFFFF
1.295 + HW_MAPPING 0xB0100000, 1, HW_MULT_1M ; 0xB0100000 - 0xB01FFFFF
1.296 + ELSE
1.297 + HW_MAPPING 0x80000000, 1, HW_MULT_4K ; 0x80000000 - 0x80000FFF mapped at KPrimaryIOBase + 0
1.298 + HW_MAPPING 0x80010000, 1, HW_MULT_4K ; 0x80010000 - 0x80010FFF mapped at KPrimaryIOBase + 0x1000
1.299 + HW_MAPPING 0x80020000, 1, HW_MULT_64K ; 0x80020000 - 0x8002FFFF mapped at KPrimaryIOBase + 0x10000
1.300 + HW_MAPPING_EXT 0x90000000, 1, HW_MULT_4K ; 0x90000000 - 0x90000FFF mapped at KPrimaryIOBase + 0x20000 ...
1.301 + DCD BTP_Rom ; ... with same permissions as ROM
1.302 + ENDIF
1.303 + DCD 0 ; terminator
1.304 +
1.305 +
1.306 +
1.307 +
1.308 +
1.309 +;*******************************************************************************
1.310 +; Set up RAM bank
1.311 +;
1.312 +; Do any additional RAM controller initialisation for each RAM bank which wasn't
1.313 +; done by InitialiseHardware.
1.314 +; Called twice for each RAM bank :-
1.315 +; First with R3 = 0xFFFFFFFF before bank has been probed
1.316 +; Then, if RAM is present, with R3 indicating validity of each byte lane, ie
1.317 +; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc.
1.318 +; For each call R1 specifies the bank physical base address.
1.319 +;
1.320 +; Enter with :
1.321 +; R10 points to super page
1.322 +; R12 points to ROM header
1.323 +; R13 points to stack
1.324 +; R1 = physical base address of bank
1.325 +; R3 = width (bottom 4 bits indicate validity of byte lanes)
1.326 +; 0xffffffff = preliminary initialise
1.327 +;
1.328 +; Leave with :
1.329 +; No registers modified
1.330 +;*******************************************************************************
1.331 +SetupRamBank ROUT
1.332 + MOV pc, lr
1.333 +
1.334 +
1.335 +
1.336 +
1.337 +
1.338 +;*******************************************************************************
1.339 +; Set up ROM bank
1.340 +;
1.341 +; Do any required autodetection and autosizing of ROMs and any additional memory
1.342 +; controller initialisation for each ROM bank which wasn't done by
1.343 +; InitialiseHardware.
1.344 +;
1.345 +; The first time this function is called R11=0 and R0 points to the list of
1.346 +; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup
1.347 +; before autodetection begins.
1.348 +;
1.349 +; This function is subsequently called once for each ROM bank with R11 pointing
1.350 +; to the current information held about that ROM bank (SRomBank structure).
1.351 +; The structure pointed to by R11 should be updated with the size and width
1.352 +; determined. The size should be set to zero if there is no ROM present in the
1.353 +; bank.
1.354 +;
1.355 +; Enter with :
1.356 +; R10 points to super page
1.357 +; R12 points to ROM header
1.358 +; R13 points to stack
1.359 +; R11 points to SRomBank info for this bank
1.360 +; R11 = 0 for preliminary initialise (all banks)
1.361 +;
1.362 +; Leave with :
1.363 +; Update SRomBank info with detected size/width
1.364 +; Set the size field to 0 if the ROM bank is absent
1.365 +; Can modify R0-R4 but not other registers
1.366 +;
1.367 +;*******************************************************************************
1.368 +SetupRomBank ROUT
1.369 + MOV pc, lr
1.370 +
1.371 +
1.372 +
1.373 +
1.374 +
1.375 +;*******************************************************************************
1.376 +; Reserve physical memory
1.377 +;
1.378 +; Reserve any physical RAM needed for platform-specific purposes before the
1.379 +; bootstrap begins allocating RAM for page tables/kernel data etc.
1.380 +;
1.381 +; There are two methods for this:
1.382 +; 1. The function ExciseRamArea may be used. This will remove a contiguous
1.383 +; region of physical RAM from the RAM bank list. That region will never
1.384 +; again be identified as RAM.
1.385 +; 2. A list of excluded physical address ranges may be written at [R11].
1.386 +; This should be a list of (base,size) pairs terminated by a (0,0) entry.
1.387 +; This RAM will still be identified as RAM by the kernel but will not
1.388 +; be allocated by the bootstrap and will subsequently be marked as
1.389 +; allocated by the kernel immediately after boot.
1.390 +;
1.391 +; Enter with :
1.392 +; R10 points to super page
1.393 +; R11 indicates where preallocated RAM list should be written.
1.394 +; R12 points to ROM header
1.395 +; R13 points to stack
1.396 +;
1.397 +; Leave with :
1.398 +; R0-R3 may be modified. Other registers should be preserved.
1.399 +;*******************************************************************************
1.400 +ReservePhysicalMemory ROUT
1.401 + MOV pc, lr
1.402 +
1.403 +
1.404 +
1.405 +
1.406 +
1.407 +;*******************************************************************************
1.408 +; Return parameter specified by R0 (see TBootParam enum)
1.409 +;
1.410 +; Enter with :
1.411 +; R0 = parameter number
1.412 +;
1.413 +; Leave with :
1.414 +; If parameter value is supplied, R0 = value and N flag clear
1.415 +; If parameter value is not supplied, N flag set. In this case the
1.416 +; parameter may be defaulted or the system may fault.
1.417 +; R0,R1,R2 modified. No other registers modified.
1.418 +;
1.419 +;*******************************************************************************
1.420 +GetParameters ROUT
1.421 + ADR r1, ParameterTable
1.422 + B FindParameter
1.423 +ParameterTable
1.424 + ; Include any parameters specified in TBootParam enum here
1.425 + ; if you want to override them.
1.426 + DCD BPR_UncachedLin, 0 ; parameter number, parameter value
1.427 + IF :DEF: CFG_CPU_ARM1136 :LAND: (:LNOT: :DEF: CFG_CPU_ARM1136_ERRATUM_364296_FIXED)
1.428 + DCD BPR_FinalMMUCRSet, ExtraMMUCR + MMUCR_FI
1.429 + DCD BPR_AuxCRSet, DefaultAuxCRSet + 0x80000000
1.430 + ENDIF
1.431 + DCD -1 ; terminator
1.432 +
1.433 +
1.434 +
1.435 +
1.436 +
1.437 +;*******************************************************************************
1.438 +; Do final platform-specific initialisation before booting the kernel
1.439 +;
1.440 +; Typical uses for this call would be:
1.441 +; 1. Mapping cache flushing areas
1.442 +; 2. Setting up pointers to routines in the bootstrap which are used by
1.443 +; the variant or drivers (eg idle code).
1.444 +;
1.445 +; Enter with :
1.446 +; R10 points to super page
1.447 +; R11 points to TRomImageHeader for the kernel
1.448 +; R12 points to ROM header
1.449 +; R13 points to stack
1.450 +;
1.451 +; Leave with :
1.452 +; R0-R9 may be modified. Other registers should be preserved.
1.453 +;
1.454 +;*******************************************************************************
1.455 +FinalInitialise ROUT
1.456 + STMFD sp!, {lr}
1.457 +
1.458 + IF CFG_Template
1.459 +
1.460 + ; set up main cache flush area
1.461 + MOV r1, #0xE0000000 ; physical address
1.462 + IF CFG_MMDirect
1.463 + MOV r0, r1 ; direct, linear = physical
1.464 + ELSE
1.465 + LDR r0, =KDCacheFlushArea ; linear
1.466 + ENDIF
1.467 + STR r0, [r10, #SSuperPageBase_iDCacheFlushArea]
1.468 + MOV r2, #BTP_MainCache ; permissions
1.469 + MOV r3, #0x100000 ; size
1.470 + MOV r4, #20 ; use section
1.471 + BL MapContiguous
1.472 +
1.473 + ; set up mini cache flush area
1.474 + ADD r1, r1, r3 ; physical address
1.475 + ADD r0, r0, r3 ; linear
1.476 + STR r0, [r10, #SSuperPageBase_iAltDCacheFlushArea]
1.477 + MOV r2, #BTP_MiniCache ; permissions
1.478 + BL MapContiguous
1.479 +
1.480 + MOV r3, #0x80000 ; wrap for cache flush
1.481 + STR r3, [r10, #SSuperPageBase_iDCacheFlushWrap]
1.482 + STR r3, [r10, #SSuperPageBase_iAltDCacheFlushWrap]
1.483 +
1.484 + ; set up idle code address
1.485 + ADR r0, IdleCode
1.486 + ADD r5, r10, #CpuPageOffset
1.487 + STR r0, [r5, #CPUPage_Idle]
1.488 +
1.489 + ENDIF
1.490 +
1.491 + LDMFD sp!, {pc}
1.492 +
1.493 +
1.494 +
1.495 +
1.496 +
1.497 +;*******************************************************************************
1.498 +; Output a character to the debug port
1.499 +;
1.500 +; Enter with :
1.501 +; R0 = character to output
1.502 +; R13 points to valid stack
1.503 +;
1.504 +; Leave with :
1.505 +; nothing modified
1.506 +;*******************************************************************************
1.507 +DoWriteC ROUT
1.508 + IF CFG_DebugBootRom
1.509 + STMFD sp!, {r1,lr}
1.510 + BL GetDebugPortBase
1.511 +
1.512 + ; wait for debug port to be ready for data
1.513 + ; output character to debug port
1.514 +
1.515 + LDMFD sp!, {r1,pc}
1.516 + ELSE
1.517 + MOV pc, lr
1.518 + ENDIF
1.519 +
1.520 + IF CFG_DebugBootRom
1.521 +
1.522 +;*******************************************************************************
1.523 +; Initialise the debug port
1.524 +;
1.525 +; Enter with :
1.526 +; R12 points to ROM header
1.527 +; There is no valid stack
1.528 +;
1.529 +; Leave with :
1.530 +; R0-R2 modified
1.531 +; Other registers unmodified
1.532 +;*******************************************************************************
1.533 +InitDebugPort ROUT
1.534 + MOV r0, lr
1.535 + BL GetDebugPortBase ; r1 = base address of debug port
1.536 +
1.537 + ; set up debug port
1.538 +
1.539 + MOV pc, r0
1.540 +
1.541 +;*******************************************************************************
1.542 +; Get the base address of the debug UART
1.543 +;
1.544 +; Enter with :
1.545 +; R12 points to ROM header
1.546 +; There may be no stack
1.547 +;
1.548 +; Leave with :
1.549 +; R1 = base address of port
1.550 +; No other registers modified
1.551 +;*******************************************************************************
1.552 +GetDebugPortBase ROUT
1.553 + LDR r1, [r12, #TRomHeader_iDebugPort]
1.554 + CMP r1, #1
1.555 + BNE %FA1 ; skip if not port 1
1.556 + GET_ADDRESS r1, Serial1PhysBase, Serial1LinBase
1.557 + MOV pc, lr
1.558 +1
1.559 + GET_ADDRESS r1, Serial0PhysBase, Serial0LinBase
1.560 + MOV pc, lr
1.561 +
1.562 + ENDIF ; CFG_DebugBootRom
1.563 +
1.564 +
1.565 +
1.566 +
1.567 +
1.568 +;*******************************************************************************
1.569 +; BOOT FUNCTION TABLE
1.570 +;*******************************************************************************
1.571 +
1.572 +BootTable
1.573 + DCD DoWriteC ; output a debug character
1.574 + DCD GetRamBanks ; get list of RAM banks
1.575 + DCD SetupRamBank ; set up a RAM bank
1.576 + DCD GetRomBanks ; get list of ROM banks
1.577 + DCD SetupRomBank ; set up a ROM bank
1.578 + DCD GetHwBanks ; get list of HW banks
1.579 + DCD ReservePhysicalMemory ; reserve physical RAM if required
1.580 + DCD GetParameters ; get platform dependent parameters
1.581 + DCD FinalInitialise ; Final initialisation before booting the kernel
1.582 + IF :LNOT: CFG_MMUPresent ; no mmu, so use stub version ...
1.583 + DCD AllocatorStub ; allocate memory
1.584 + ELSE
1.585 + DCD HandleAllocRequest ; allocate memory
1.586 + DCD GetPdeValue ; usually in generic code
1.587 + DCD GetPteValue ; usually in generic code
1.588 + DCD PageTableUpdate ; usually in generic code
1.589 + DCD EnableMmu ; Enable the MMU (usually in generic code)
1.590 + ENDIF
1.591 +
1.592 +; These entries specify the standard MMU permissions for various areas
1.593 +; They can be omitted if MMU is absent
1.594 + IF CFG_MMUPresent
1.595 + BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; ROM
1.596 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; kernel data/stack/heap
1.597 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; super page/CPU page
1.598 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page directory/tables
1.599 + BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; exception vectors
1.600 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; hardware registers
1.601 + DCD 0 ; unused (minicache flush)
1.602 + DCD 0 ; unused (maincache flush)
1.603 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page table info
1.604 + BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; user RAM
1.605 + BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, 0 ; temporary identity mapping
1.606 + BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; uncached
1.607 + ENDIF
1.608 +
1.609 +
1.610 + END